JPH0418496B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical field to which the invention pertains) The present invention relates to a receiving device using a matched filter in a direct spread spectrum communication system, which is a type of spread spectrum communication system, and particularly relates to a reception device using a matched filter. It is related to synchronous circuits.

(Prior art and its problems) In the spread spectrum communication system, the direct spread system using two-phase phase keying (PSK) modulates the carrier wave with two-phase phase modulation using information data, and then compares the signal transmission rate with the data. The signal is transmitted after being binary-phase modulated using a fast pseudo-random code, or the carrier wave is subjected to binary-phase modulation using the output obtained by multiplying the pseudo-random code and data and transmitted as a spread signal.

A to d in FIG. 2 are examples of waveforms on the transmitting side, where a is information data to be transmitted, b is a pseudorandom code, and c
is the product of both a and b, and d is a spread signal subjected to two-phase phase modulation with the product output c. Here, information data a
This shows a case where the length of one bit of b is equal to the length of one period of pseudorandom code b.

FIG. 1 is a diagram illustrating a configuration example of a demodulating section of a receiving apparatus that receives a spread signal. Although there are various demodulation methods, this figure shows a demodulation section circuit using a matched filter 1 in an intermediate frequency band.

2. e to g in FIG. 2 show examples of waveforms of each part of the reception demodulation section in FIG. 1. Matsushido filter 1 is
For example, it can be easily realized using a surface acoustic wave element or the like, and when a desired received signal is input to this, an output having a correlation peak at each period of the pseudorandom code as shown in waveform e is obtained. In the receiving device,
Data demodulation is performed in synchronization with the position of this peak. That is, when the output e of the matched filter 1 is input to the synchronous detector 2 and synchronously detected using the carrier wave regenerated by the carrier wave regeneration circuit 4, an output of waveform f is obtained. A demodulated output g is obtained by sampling this output f at the position of the peak in the sampling determination circuit 3 and determining whether it is positive or negative. By sampling at the peak position in this manner, it is possible to determine the S/N in a state where the S/N is improved by the ratio of the code rate of the pseudorandom code to the data transmission rate, that is, the spreading gain of the spread spectrum, relative to the input.

A timing synchronization circuit 24 is a synchronization circuit for adjusting the sampling timing to the position of this peak, which is comprised of a circuit from an envelope detector 5 to a clock generation circuit 9. The output e of the matched filter 1 is detected by the envelope detector 5, and the phase difference between the detected output and the output clock of the clock generation circuit 9 is determined by the phase difference detection circuit 6. The oscillation frequency and phase of a voltage controlled oscillator (VCO) 8 having a frequency equal to the repetition frequency are controlled to match the timing of the output clock of the clock generation circuit 9 obtained from the output of the VCO 8 with the peak position of the input signal.

Figure 3 shows the timing synchronization circuit 2 in Figure 1.
This is an example of the circuit configuration of the phase difference detection circuit 6 used in 4, in which 10 and 11 are analog gates (GATE), 12 is a subtraction circuit (SUB), 13, 14
is an input terminal for gate pulses that control the opening and closing of the two analog gates 10 and 11, and is an input from the clock generation circuit 9.

Figure 4 shows the waveforms of each part of the circuit in Figure 3, where h is the input from the envelope detector 5, i and j are the gate pulses input from 13 and 14, and k and l are the outputs of analog gates 10 and 11. , m are the outputs of the subtraction circuit 12. As shown in the figure, if the output h from the envelope detector 5 has a peak at the time of switching between the two gate pulses i and j, the DC components of the outputs of both gates 10 and 11 are equal, and the subtraction The DC component of the output m of the circuit 12 becomes 0V. However, if the switching point between the two gate pulses i and j and the peak position of the output h shift, one gate output becomes larger depending on the magnitude and direction of the phase difference, so the output m of the subtraction circuit 12 The DC component becomes a positive or negative voltage corresponding to the direction of the phase difference. The output m corresponding to this phase difference passes through the LPF 7 and controls the frequency and phase of the VCO 8 to achieve synchronization.

In order to detect the phase difference using the circuit shown in FIG. control and even a second
Accurate timing was adjusted using analog gates 10 and 11 at each step. In this way, it is necessary to configure a complex control circuit that spans two stages.
The drawback is that it takes time to synchronize. Furthermore, the degree of spreading was limited because it was difficult to manufacture high-speed analog gates capable of passing direct current, which is required when increasing the speed of pseudo-random codes and spreading the spectrum over a wide band.

(Objective of the Invention) An object of the present invention is to provide a spread spectrum signal receiving device equipped with a synchronization circuit that has accurate and stable synchronization pull-in operation with a simple circuit configuration and can cope with increased speed of spread signals. It's about doing.

(Structure of the invention) The present invention will be explained in detail below with reference to the drawings.

FIG. 5 shows an example of the circuit configuration of the phase difference detection circuit 6 in the timing synchronization circuit 24 implementing the present invention.
In the figure, 15 and 16 are analog delay lines having the same delay time t, and 17 is the output p of the delay line 16 and the input h from the envelope detector 5 to the delay line 15.
18 is a comparator that compares the output voltage n of the first stage delay line 15 with a preset threshold voltage. 19 is the logic of the outputs q and r of both comparators 17 and 18. AND
gate (AND); 20 is a sawtooth wave generation circuit that generates a "sawtooth wave" u having the same repetition period as the pseudo-random code based on the input 22 from the clock generation circuit 9; 21 is the output u of the sawtooth wave generation circuit 20; This is a sample hold circuit that samples the pulse output s from the AND gate (AND) 19. Clock input 2 from clock generation circuit 9
In the conventional case of FIG. 3, two 2, i and j, are required, but in the present invention, only one is required.

6 is an example of waveforms of each part of the phase difference detection circuit 6 of FIG. 5 according to the present invention, h is the input from the envelope detector 5, n is the output of the first stage delay line 15, and p is the 2
The output of the delay line 16 in the second stage, q is the output of the comparator 17, r is the output of the comparator 18, s is the output of the AND gate (AND) 19, u is the sawtooth wave generation circuit 2
It shows an output of 0.

The operation of the phase difference detection circuit 6 used in the present invention will be explained below with reference to FIGS. 5 and 6. The input h from the envelope detector 5 is input to the comparator 17 as an output p delayed by 2t by delay lines 15 and 16 having the same delay time t. delay time t
is a value smaller than about 1/2 of the width A of the correlation peak that appears every period of the pseudorandom code and larger than 0, taking into consideration the noise contained in the input h from the envelope detector and the accuracy of the comparator 17. 1/2A~1/4A
is appropriate. The comparator 17 compares the level of this delayed output p and the other input h, and is set to output an output q which is "1" if the former is large, and "0" if the latter is large. So this output q
changes from "0" to "1" at a position delayed by t from the position of the correlation peak of input h.

On the other hand, the comparator 18 obtains an output r that becomes "1" when the output n obtained by delaying the input h by t in the first stage delay line 15 is greater than a preset threshold voltage v. In the output q of the comparator 17, many changes from "0" to "1" due to the waveform w having a small level other than the correlation peak appear, but in the output r of the comparator 18, it is compared with the set threshold voltage v. will not appear in the output.

The threshold voltage v of the comparator 18 is a value such that the output of the comparator 18 does not become "1" due to the correlation waveform w of a small signal other than the correlation peak of the output of the matched filter 1 and noise input together with the signal. Moreover, it is set to a value that can sufficiently extract the correlation peak output that appears in each period of the pseudorandom code. The outputs q and r of both comparators 17 and 18 are
If we take AND, we get the output s. On the other hand, the sawtooth wave u created based on the input 22 from the clock generation circuit 9 is set using a simple offset circuit so that the 0 level of the voltage is 1/2 of the maximum value.
If the sawtooth wave u is sampled and held in the sample-and-hold circuit 21 using the pulse s obtained from the received data, it will be proportional to the amount of timing shift (phase difference) between the input and the clock, and for example, s' or
When s'', a DC voltage 23 having a polarity corresponding to the direction of the deviation such as u', u'' and a voltage proportional to the magnitude of the deviation is obtained, and operates as the phase difference detection circuit 6. . Therefore, with this DC output 23
A synchronous circuit 24 is constructed by controlling the voltage controlled oscillator 8 via the LPF 7.

Note that the method for detecting the phase difference between the output s of the AND gate 19 and the clock input 22 is not limited to the method using a sawtooth wave as shown in FIG. 5, but also the method using a set/reset (RS) flip-flop as a phase detector. Other circuit schemes can also be used, such as the method.

In the timing synchronization circuit 24 used in the present invention, the detection output corresponding to the timing phase difference of the phase difference detection circuit 6 is as understood from the waveform of FIG.
Since it exhibits a detection characteristic that is proportional to the magnitude of the deviation and has a polarity corresponding to the direction of the deviation, no matter what the timing of the signals 22 and s is, the two are automatically brought into a synchronized state. It turns out. Therefore, there is no need for complicated synchronization pull-in processing as in conventional circuits. Furthermore, since circuit elements such as analog switches are not used, a circuit suitable for high-speed operation can be constructed.

(Effects of the Invention) As explained in detail above, according to the present invention, by configuring a simple synchronization circuit 24 without using a conventional complicated control circuit, a stable and accurate synchronization state can be achieved. be able to. Also,
It can be used as a stable synchronization circuit even in the case of high-speed spread signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a demodulating section circuit of a receiving device to which the present invention is applied, FIG. 2 is an example diagram of transmission waveforms of a transmission section to which the present invention is applied, and waveforms of each part of the circuit in FIG. 1. 4 is a block diagram showing an example of a phase difference detection circuit used in a conventional receiver, FIG. 4 is an example of waveforms of each part of the circuit in FIG. 3, and FIG. 5 is a diagram showing a phase difference detection circuit used in a receiver of the present invention. FIG. 6 is a block diagram showing an example of the configuration of the detection circuit. FIG. 6 is a diagram showing an example of waveforms of each part of the configuration example of FIG. 1...Matched filter, 2...Synchronous detector,
3...Sampling judgment circuit, 4...Carrier regeneration circuit, 5...Envelope detector, 6...Phase difference detection circuit, 7...LPF, 8...VCO, 9...Clock generation circuit, 10, 11 ...GATE, 12...
SUB, 13, 14... Gate input terminal, 15,
16...Delay line, 17, 18...Comparator, 19
...AND, 20...Sawtooth wave generation circuit, 21
...Sample hold circuit, 22...Clock input, 23...Output, 24...Synchronization circuit.

Claims (1)

[Claims] 1. The position of the correlation peak of the envelope detection output obtained by envelope detection of the output of a matched filter that receives a spread spectrum signal as input, and the position of the correlation peak of the envelope detection output obtained by envelope detection of the output of a matched filter that inputs a spread spectrum signal, and A phase difference detection circuit detects a phase difference with a demodulation timing clock pulse generated from a voltage controlled oscillator, controls the voltage controlled oscillator based on the phase difference to create a demodulation timing clock pulse, and generates a demodulation timing clock pulse. In a spread spectrum signal receiving device that samples the output of a wave detector to obtain a demodulated output, the phase difference detection circuit converts the envelope detection output to a delay time smaller than about 1/2 of the width of its correlation peak. A first delay line and a second delay line are connected in cascade to sequentially delay the output of the envelope detector by comparing the voltages of the output of the second delay line and the output of the envelope detector, a first comparator that outputs an output when the first delay line output exceeds a preset threshold voltage; An AND gate that takes the logical product of each output of the comparator, a sawtooth wave generation circuit that generates a sawtooth wave synchronized with the demodulation timing clock pulse, and a sawtooth wave that is sampled and held using the output pulse of the AND gate. A receiving device for a spread spectrum signal, comprising a sample and hold circuit that obtains a direct current having a polarity proportional to the amount of the phase difference and corresponding to the direction thereof.