JPS6336622A - Method and apparatus for spread spectrum power line carrier communication - Google Patents

Abstract

PURPOSE:To ensure demodulation by obtaining the correlation between a M series code generated at the reception side and a received modulation signal and shifting the phase of the M series code so as to maximize the correlation. CONSTITUTION:A reception M series code generating circuit 21 generates a N series code of the same code pattern as that for spread spectrum based on clock pulses CP1, CP2 outputted from a power supply synchronizing clock generating circuit 20. The M series code is extracted via a phase shift section 32b and the extracted M series code M2 apd the received modulation signal are fed to a phase shift control section 32c to obtain correlation. A shift control signal is generated to maximize the absolute value of the correlation output to control the phase shift quantity of the phase shift section 32b.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to spread spectrum power line carrier communication that uses power lines as transmission paths, and particularly relates to a power source that uses a power source to synchronize operations on the transmitting side and the receiving side. The present invention relates to a synchronous communication method and device.

[Prior art]

Conventionally, when transmitting information signals using power lines, various modulation methods have been used depending on the type of transmission path. For example, in the case of a power transmission line transmission line, a single sideband modulation method is used, and in the case of a distribution line transmission line, a frequency modulation method or a phase modulation method is used. However, since power lines are not installed with signal transmission in mind, when attempting to transmit information signals, various types of noise may come in, or the transmission characteristics may vary significantly depending on the load condition. I have a problem. In other words, in the high frequency characteristics of power lines, corona noise and load noise vary greatly regardless of whether they are transmission lines or distribution lines. Therefore, it has been difficult to perform highly reliable signal transmission, and particularly high-speed data transmission has been impossible.

By the way, research has recently been underway to actively utilize spread spectrum communication methods in various fields.
Explanations of its principles and fields of application are disclosed on page 965 of the September issue of the Journal of the Institute of Electronics and Communication Engineers, and on page 1053 of the October issue. This spread spectrum communication method is characterized by a wide spectrum, the use of special codes, and correlated signals, and when used to transmit information signals using power lines, it becomes less susceptible to noise and transmission characteristics. This makes it possible to transmit high-speed data with high reliability. In other words, this spread spectrum communication method transmits narrowband information signals by spreading the spectrum evenly over a wide band.
Even if a zero point occurs in part of the transmission characteristics due to the load condition of the power line, the S is almost unaffected, and even if narrowband noise is mixed in, the correlation is taken on the receiving side, so the S /N becomes large.

FIG. 8 is an overall configuration diagram showing an example of the use of the spread spectrum communication method for power line transmission, in which modulation is performed using a pseudo-noise signal called PN spread or direct spread. An M-sequence code is used as the noise signal. This M-sequence code is the longest of the linear code sequences generated by a certain number of stages of shift registers and feedback circuits, and is such that the values at each instant are distributed in a quasi-noise state within one cycle. It is set.

In the figure, reference numeral 1.2 denotes a transmitting device and a receiving device connected via a power line 3. In the transmitter 1, 4 is a clock oscillation circuit that generates a clock pulse CP with a frequency of 250KH2, and 5 is a zero-cross detection circuit,
A zero-crossing detection signal Z is generated every time a zero-crossing point of the AC power supplied via the power line 3 is detected. 6 is a transmission M-sequence code generation circuit that generates an M-sequence code as a pseudo-noise signal, and as shown in FIG. 9, it includes, for example, a three-stage shift register 6a;
The exclusive OR gate 6b calculates the exclusive OR of the outputs of the second stage and the third stage and returns it to the input side. By sequentially shifting the input signal accordingly, the maximum code length from the final stage is 2”-1 (
n is the number of stages of the shift register).

Further, when the transmission M-sequence code generation circuit 6 is supplied with the zero-cross detection signal Z from the zero-cross detection circuit 5,
The flip-flop circuits FF, -FF3 constituting each stage of the shift register 6a shown in FIG. 8 are all reset to "1". Reference numeral 7 denotes a spread spectrum modulation circuit, which performs product modulation (calculating exclusive OR) on the M-sequence code supplied from the transmission M-sequence code generation circuit 6 and the transmission data, thereby converting the transmission data into a spectrum. It is converted into a spread modulated signal. Reference numeral 8 denotes a coupling circuit composed of a transformer 9 and capacitors 10a and 10b, which transmits the modulated signal supplied from the spread spectrum modulation circuit 7 to the power line 3 via a filter for removing low frequency components (not shown) and a transmission amplifier. supply to.

On the other hand, in the receiving device 2, 10 is a clock oscillation circuit that generates the same clock pulse CP as the clock oscillation circuit 4 of the transmitting device 1, and 11 is a zero-cross detection circuit,
A zero-cross detection signal Z is generated every time a zero-cross of the AC power supplied via the power line 3 is detected. Reference numeral 12 denotes an M-sequence code generation circuit for reception, which, like the M-series code generation circuit 6 for transmission, has the configuration shown in FIG. A coupler 13 takes out a spread spectrum modulated signal sent from the transmitter 1 via the power line 3, and is composed of a transformer 14 and capacitors 15a and 15b.

16 is a spectrum despread demodulation circuit, which is a receiving M
By multiplying the M-sequence code supplied from the sequence code generation circuit 12 by the modulation signal supplied from the coupler 13 via a reception amplifier (not shown) and a filter that removes low frequency components, correlation detection is performed to obtain the received data. Take out the.

In the spread spectrum communication device configured in this way, when the power switch is turned on, the clock oscillation circuit 4 provided in the transmitting device 1 and the receiving device 2,
10 sends out clock pulses CP of the same period. Furthermore, the zero-cross detection circuits 5 and 11 provided in the transmitting device 1 and the receiving device 2 generate a zero-cross detection signal Z every time a zero cross of the AC power supply supplied via the power line 3 is detected. Since the zero-cross detection circuits 5 and 11 perform zero-cross detection for the AC power flowing through the same power line 3, the zero-cross detection signals Z generated from both circuits are synchronized.

Here, since the transmission M-sequence code generation circuit 6 is configured as shown in FIG. 9, the zero-cross detection signal Z is generated from the zero-cross detection circuit 5 at time t1 in FIG. 10(f). Since the shift register 6a uses this zero cross detection signal Z as a reset input,
The output of the flip-flop circuit FF, ~FF, is the 10th
Figure fat, (b).

FC], all are reset to "1".

Therefore, the output signal of the exclusive OR gate 6b becomes "0" as shown in FIG. 10 Fdl. Next, when the 7th block CP rises as shown at time L2 of the 101st J (el), the shift register 6a is activated by the exclusive OR gate 6.
Since the output signal of b is read and shifted, the output signal of each flip-flop circuit FF, ~FF, is "0",
“1”, “1°”. Next, Kuro and Coupals CP are the first
When the signal rises as shown at time t3 in FIG. , each flip-flop circuit FF, ~F
The output signal of F3 is 0'', 0''.

It becomes “1”. Here, since the exclusive OR gate 6b uses the outputs of the flip-flop circuits FFz and FF1 as input signals, if a mismatch occurs in the outputs, the
"outputs the signal as shown in FIG. 10(d). Then,
The output signal of exclusive OR gate 6b is taken into shift register 6a at the next rising edge of clock pulse CP.

By sequentially performing such operations, a code on the 11 side with period T between time points t2 and t1 is obtained from the final stage flip-flop circuit FF, as shown in FIG. 10 (d+). Since this ~11 side code is generated while being reset by the zero-crossing detection signal Z, it is synchronized with the AC power flowing through the power line 3.

In this way, the M-sequence code generated in synchronization with the AC power supply is multiplicatively modulated with the transmission data synchronized with the high-frequency clock pulse CP in the spread spectrum modulation circuit 7, thereby converting the narrowband transmission data into It is output as a modulated signal whose spectrum is uniformly spread over a wide band. After low frequency components are removed from the modulated signal in a filter (not shown), the modulated signal is amplified to a predetermined level by a transmitting amplifier 8, and is sent to the power line 3 by being supplied to the coupler 8.

On the other hand, in the receiving device 2 as well, based on the clock pulses C and P output from the clock oscillation circuit 10, the receiving M-series code generating circuit 12 generates the transmitting M-sequence code generating circuit 6.
Similarly, M-sequence codes with the same pattern configuration are generated. Since this reception M-sequence code generation circuit 12 is reset by the output signal Z of the zero-cross detection circuit 11 that detects the zero-cross of the AC power flowing through the power line 3, the generated M-sequence code is It is synchronized with the AC power supply, that is, synchronized with the M-sequence code output from the transmission M-sequence code generation circuit 6. Combiner 13
extracts a modulated signal sent from the transmitting device 1 via the power line 3, and this modulated signal is amplified by a receiving amplifier (not shown), and then low frequency components are removed by a filter and sent to the spectrum despread demodulation circuit 16. supplied to The spectrum despread demodulation circuit 16 has a receiving M
By multiplying the M-sequence code supplied from the sequence code generation circuit 12 by the received modulated signal spread spectrum and sent, the spectrum is despread and the received data is extracted.

[Problems to be solved by the invention] However, the above-mentioned spread spectrum communication method
The transmission M-sequence code generation circuit and the reception M-series code generation circuit generate M-sequence codes based on the zero-cross point of the AC power flowing through the power line used as a transmission path, thereby achieving synchronization between the two. However, the following disadvantages occur. In other words, the zero-crossing point of an AC power source fluctuates depending on load fluctuations, impedance, and other factors. As a result, in cases where the transmitter and receiver are relatively far apart, a phase difference in the AC power supply may occur between the transmitter and the receiver depending on load fluctuations on the power line 3, and as a result, the zero-crossing point of the AC power supply may Since the phases of the synchronously generated M-sequence codes are shifted from each other, normal communication cannot be performed. Next, for example, when the clock pulse frequency is 250 KHz, 1 of the M sequence code
The chip width is 1/250 = 4 μsec. On the other hand, with the M-sequence codes used for modulation and demodulation in the transmitter/receiver, normal communication cannot be performed unless the mutual phase shift is at least within ±0.5 chips.7 chips. However, due to the characteristics of the zero-cross detection circuit, the timing of detecting a zero-cross is shifted by about 10 μsec, so the generated M-sequence code also has a phase shift of about 10 μsec, making it impossible to perform normal communication. In addition, the clock pulses generated in each transmitter and receiver are asynchronous,
Even if there is no deviation in the timing of zero cross detection, the maximum
Since a phase shift corresponding to the clock occurs, the phase of the M-sequence code shifts by ±1 chip, making it impossible to perform normal communication. Furthermore, when the M-sequence code is generated in synchronization with the zero-crossing point, since the period of the M-sequence code and the period of the AC power supply do not match, the M-sequence code is forcibly generated when the zero-crossing point is detected. There is a problem in that the operation is reset and interrupted, and as a result, normal communication cannot be performed in the periodic part of the M-sequence code that includes the zero-crossing detection point.

[Means for solving problems]

The spread spectrum power line carrier communication method and apparatus according to the present invention provides an M
By product-modulating the transmitted data using the sequence code, a modulated signal that is a spread spectrum of the transmitted data is generated and supplied to the power line, and the receiving side uses the M-sequence code generated in synchronization with the AC power supply. In a system that extracts received data by multiplying and demodulating a received modulated signal sent via a power line, the correlation between the M-sequence code synchronized with the AC power source generated on the receiving side and the received modulated signal is determined. , the phase of the M-sequence code is shifted so that the correlation value is maximized, and the code is used for demodulating the received modulated signal.

[For production]

In the spread spectrum power line carrier communication method and device configured in this way, the M-sequence code used for demodulating the received modulated signal on the receiving side has the maximum correlation value with the M-sequence code included in the received modulated signal. Since phase shift control is added, even if the phase of the AC power source is shifted due to the load connected to the power line, the M-sequence code used for demodulation is the same as the M-sequence code included in the received modulated signal. Since the signal is synchronized with the code, reliable demodulation can be obtained.

〔Example〕

FIG. 1 is a block diagram for explaining an embodiment of the spread spectrum power line carrier communication method and apparatus according to the present invention, and the same parts as in FIG. 8 are indicated using the same reference numerals. In the same figure, reference numeral 17 denotes a power synchronized clock generation circuit, which synchronizes with the AC power supplied via the power line 3, and where N is the maximum cycle length of the M-sequence code used and K is an arbitrary integer. /2X2N for power supply frequency
It is configured to generate a clock pulse CP having twice the frequency, and a clock pulse CP having a frequency 2N times higher than that frequency and synchronized with the AC power supply. 18 is a clock pulse CP output from the power supply synchronous clock generation circuit 17;

a transmission amplifier 19 that amplifies the spread spectrum modulation signal output from the spread spectrum modulation circuit 7 and supplies it to the coupling circuit 8; Reference numeral 20 denotes a power synchronization clock generation circuit, which supplies clock pulses C to the power supply synchronization clock generation circuit 17 provided in the transmitter 1.
A clock pulse CP having M times the frequency with respect to P
3 generation functions have been added. Reference numeral 21 denotes a reception M-series code generation circuit, which receives clock pulses CP+ and C generated from the power supply synchronization clock generation circuit 20.
Pz, CP:l and the output signal of the reception amplifier 22 which amplifies the modulation signal output from the coupler 13 and supplies it to the spectrum despread demodulation circuit 16, and synchronizes with the M-sequence code included in the reception modulation signal. The generated M-sequence code M2 is generated and supplied to the spectrum despread demodulation circuit 16.

FIG. 2 shows the power supply synchronous clock generation circuit 17 shown in FIG.
FIG. 2 is a circuit diagram showing a specific example of a transmission M-sequence code generation circuit 18. FIG. In the figure, 23 is an AC type a (AC100■) supplied via the power line 3, and a frequency divider 27, which will be described later.
24 is a phase comparator 23 which compares the phase with the output signal of and outputs a signal with a level corresponding to the phase difference.
A low-pass filter 25 smoothes the output of the low-pass filter 24, and a voltage-controlled variable frequency oscillator (hereinafter referred to as VC○) whose control input is the output of the low-pass filter 24, and generates a clock pulse CP. 26 is a frequency divider, and M for transmission.
When the maximum cycle length of the M-sequence code generated from the sequence code generation circuit 18 is N, the clock pulse CP is 1/2N.
A clock pulse CP2 whose frequency is divided into two is generated. 27 is the clock pulse CP2 output from the frequency divider 26 by 2/K.
(K is an arbitrary integer) and supplies the frequency to the phase comparator 23. These phase comparator 23, low-pass filter 24, VCO 25, and frequency divider 26, 27 constitute a phase-locked loop (PLL) circuit, so that they are synchronized with the AC power supply and the NXK
This means that a clock pulse CP2 having twice the frequency of the clock pulse CP1 which is synchronized with the AC power supply and having a frequency 2N times higher than the clock pulse CP1 is generated.

Next, the transmission M-sequence code generation circuit 18 includes flip-flop circuits FF, -F, as described in FIG.
The number of stages of the shift register 6a is set to n by the shift register 6a in which F3 is connected in series and the exclusive OR gate 6b which calculates the exclusive OR of the output signals of the flip-flop circuits FF2 to FF3 and returns it to the input side. When this happens, an M-sequence code having a maximum code length of 2''-1 is generated. 28 is an AND gate that calculates one loss for all stages of the output of the shift register 6a, and 29 is an AND gate that calculates one loss for all stages of the output of the shift register 6a. 30 is an exclusive OR gate that finds the mismatch between the output signal of the frequency divider 29 and the clock pulse CP2, and 31 is the output signal of the exclusive OR gate 30 and the clock pulse CP amount. The output signal is supplied to the clock input terminal CK of the shift register 6a.The AND gate 28, the frequency divider 29, the exclusive OR gate 30, and the AND gate 31 are , performs synchronization control for synchronizing the M-sequence code generated from the shift register 7a with the AC power supply.

FIG. 3 shows the power supply synchronous clock generation circuit 20 shown in FIG.
and circuits showing a specific example of the reception M-sequence code generation circuit 21, the same parts as in FIG. 2 are denoted by the same symbols, and detailed explanation thereof will be omitted.

In the figure, the power supply synchronous clock generation circuit 20
VC in the power supply synchronous clock generation circuit 17 shown in the figure
○Use a VCO 25a that oscillates a frequency M times higher than that of 25, and use a frequency divider 25b that divides the frequency by M on its output side.
By interposing the clock pulse CP3, a clock pulse CP3 having a frequency M times that of the clock pulse CP is extracted from the output side of the VCO 25a.

Next, the receiving M-sequence code generation circuit 21 includes an M-sequence code generation section 32a, a phase shift section 32b, and a phase shift control section 32C. Here, the M-sequence code generator 32a generates an M-sequence code having the same code pattern as the M-sequence code used for spread spectrum modulation of transmission data on the transmitting side, and
By having the same configuration as the transmission M-sequence code 18 shown in the figure, an M-sequence code synchronized with the AC power source is generated. Next, numeral 33 in the phase shift section 32b is a shift register, and the power supply synchronous clock generation circuit 2 described above
The number of stages is 2M for the frequency division value M of the frequency divider 25b at 0. In this case, the shift register 33 receives the output of the flip-flop circuit FF2 in the shift register 6a, and receives the clock pulse CPl output from the power synchronization clock generation circuit 20.
A clock pulse CP, which is outputted with a frequency M times as high as that of the clock pulse CP, is used as a clock input. 34 is a selector which selects the output of each stage of the shift register 33 according to the output of a counter 41, which will be described later, to select an M-sequence code M whose phase matches the M-sequence code included in the received modulated signal.
2 is generated and supplied to the spectrum despread demodulation circuit 16 shown in FIG. Next, 35 in the shift control section 32c
is the M sequence code M2 output from the selector 34 and the first
36 is an absolute value circuit that calculates and outputs the absolute value of the output signal of the correlator 25, and 37 is set by a variable resistor 38. A comparator 39 compares the output signal of the absolute value circuit 36 with the reference value Va, and 39 is a difference circuit that receives the output signal of the absolute value circuit 36. For example, as shown in FIG. Signal M
Delay circuit 39 that delays the sequence code for one cycle period
a, the output signal of this delay circuit 39a, and the absolute value circuit 39
The comparator 39b compares the output signal of the absolute value circuit 36 with the output signal of the absolute value circuit 36, and generates an output signal when the output signal of the absolute value circuit 36 stops increasing. 4
0 is an RS type flip-flop circuit with a reset input, which uses the output signal of the differential circuit 39 as the cent input, and uses the output signal of the comparator 37 as the reset input. 41 is a counter which pre-centers the data X supplied to the input terminal IN when the output signal of the comparator 37 is generated;
The output signal A of the differential circuit 39 is used as a clock input, and the output signal of the differential circuit 39 is used as an enable input. The count output signal of the counter 41 is supplied as a shift control signal to the selector 34, thereby controlling the select position for each output of the shift register 33 and controlling the shift amount.

In the spread spectrum power yA carrier communication system configured in this way, when power is supplied to the sending bag W1 and the receiving device 2, the power synchronized clock generation circuit 17.20
is electricity! AC power supplied via fy”R3
generates black pulses cp, CPz synchronized with looV). In other words, in FIG. 2, the clock signal H26,2
7, the signal is sequentially frequency-divided and then supplied to the phase comparator 23. The phase comparator 23 compares the phases of the output signal of the frequency divider 27 and the AC power source (AClooV), and outputs a control signal representing the phase difference by a level. This control signal is smoothed in the low-pass filter 24 and then
By being supplied to the control input terminal of O25, the value of the signal output from the phase comparator 23 is controlled to be small.

By repeating such control, that is, by performing phase-locked loop (PLL) control, the phase of the clock pulse CP10 shown in FIG. 5(b) output from the VCO 25 changes to the phase shown in FIG. 5(a). AC power supply A
It will be locked to the phase of C100V. and,
Since the frequency dividers 26 and 27 are provided in the phase-locked loop, the clock pulse CP in this case is a frequency that is NK times the frequency of the AC power supply, which is expressed as the product of the division values of both frequency dividers. will have. Further, the frequency divider 26 outputs a clock pulse CP2 obtained by dividing the clock pulse CP+ into 172N as shown in FIG. 5(f). And this clock pulse CP2
Since it is created based on the clock pulse cp+, it is synchronized with the total current m<Ac100V), and the frequency division value of the frequency divider 26 is 2N, so it is used in this system. A signal that inverts to H" and "L" every period that corresponds to one cycle length of the M-sequence code, that is, the fifth
As shown in Figure (f), the AC power supply (A
The signal is synchronized with ClooV) and has twice the frequency.

In this way, the clock pulses CP+ and CPz generated from the power synchronization clock generation circuit 17 are supplied to the transmission M-sequence code generation circuit 18. In the transmission M-sequence code generation circuit 18 shown in FIG.
Since r is supplied to the clock input terminal CK of the shift register 6a via the OR gate 31, the shift register 6a sequentially shifts the output signal of the exclusive OR gate 6b to each flip-flop circuit FF, to FF3. The output is as shown in FIG. 5 (C1 to (e)), and is the output of the shift register 6a, that is, the flip-flop circuit FF.

The output is output as an M-sequence code having a pattern determined by the input conditions of the exclusive OR gate 6b.

Here, when the shift register 6a is cleared at the time t2 shown in FIG. 5, for example, at the time of initialization when the power is turned on or in the reset mode, the output signal of the flip-flop circuits FF, ~FF:l becomes fc as shown in FIG.
As shown in (e), all are set to "I".

Each time the outputs of the flip-flop circuits FF, ~FF become all "1", the output signal A of the AND gate 28 becomes "H" as shown in FIG. After being frequency-divided, it is supplied to the exclusive OR gate 30 as an output signal B shown in FIG.

In other words, the signal B output from the frequency divider 29 is a signal that is inverted to RH11° "L" every cycle of the M-sequence code in normal times.

The output signal B generated in this manner is compared with the clock pulse CP2 in the exclusive OR gate 30, and if the two match, the generated M-sequence code is
AClooV). However, at time t, the clock pulse CP2 changes from "H" to "L".
Since the output signal B of the frequency divider 29 and the clock pulse CPz do not match, the output signal of the exclusive OR gate 30 becomes "H" as shown in FIG. 5 (hl). When the output signal C becomes "H", the OR gate 31 fixes the output signal to "H" as shown in FIG. 5 (11) even though the clock pulse CP1 is supplied. , an output signal B of the frequency dividing circuit 29 indicating the cycle of the M-sequence code actually generated, and a clock pulse C indicating the generation cycle of the M-series code synchronized with the AC power supply.
During the period of disagreement with P2, exclusive OR gate 3
Since the signal C shown in FIG. 5(h) output from 0 becomes "H", the "H" portion of this signal C is
1 by fixing the clock pulse CP1 in the "H" state.

It will be done. Therefore, in the shift register 6a,
As shown in FIG. 5(1), the clock pulses D shown by ■ to ■ are maintained in the supplied state. Then time t
4, when the clock pulse CPz is inverted to "H", the output signal B of the frequency divider 29 shown in FIG.
Since the clock pulses CP shown in FIG. 5(f) match, the output signal C of the exclusive OR gate 30 is
) becomes “L” as shown. As a result, ORGATE 3
1, the clock pulse CP + is again supplied to the shift register 6a as the clock pulse D shown in FIG. 5(i). Then, at time t shown in FIG. 5(i), after the clock pulse D indicated by ■ is generated, at time t6 the clock pulse D indicated by ■ rises, and the outputs of the flimp-flop circuits FF and -FF3 are Since the output signal A of the AND gate 28 becomes all "H" as shown in FIG.
As shown in J), it is inverted to "H" at time 1k. Then, this output signal A is inverted to "H" from time t2 to 2
Since this is the third time, the output signal B of the frequency divider 29 is inverted to "L" accordingly. When the output signal B becomes "L", there is a mismatch with the clock pulse CP2, so the output signal C of the exclusive OR gate 30 becomes "H", and the clock pulse D to the shift register 6a becomes "H". Block supply.

Next, at time t7, clock pulse CP2 goes “L”.
When the output signal C of the exclusive OR gate 30 is inverted to "L", the output signal C of the exclusive OR gate 31 is also inverted to "L".
The clock pulse D is shown in FIG. 5(i) at time t11+.
9+ tl.・・・・・・■、■、■・・・・・・
The signal is outputted as shown by and supplied to the shift register 6a. After this time t8, the numbers ■, ■, ■ shown in FIG.・・・・・・
..., and the clock pulse CP1 generated in synchronization with the AC power supply AC100V is counted repeatedly for each maximum code length of the M sequence code from the zero cross point of the AC power supply.
Numbers 2, 3, 4, etc. of the clock pulses CP shown in l.
...will match. In other words, each period of the M-sequence code generated from the shift register 6a is "H",
The output signal B of the frequency divider 29, which is inverted to "L", indicates the period when the M-sequence code is generated in synchronization with the AC power supply AC100V (it is inverted to "H" and 'L' every cycle). ) The clock pulses D supplied to the shift register 6a are thinned out so as to be synchronized with the clock pulse C'P2.
Once the M-sequence code generated from the AC power supply is synchronized with the AC power supply AC100V, this state is locked, and from then on, the power supply synchronization clock generation circuit 17 is completely synchronized with the AC power supply AC100V.

Since C20 continues to be generated, even if the phase of the AC power source fluctuates somewhat due to some reason, the generated M-sequence code will always be synchronized with the AC power source. and,
This operation is instantaneously performed when the power is turned on.

In this way, the M-sequence code synchronized with the AC power source generated from the transmission M-sequence code generation circuit 18 is multiplicatively modulated with the transmission data in the spread spectrum modulation circuit 7, so that the narrowband transmission data is It is output as a modulated signal whose spectrum is uniformly spread over a wide band. The modulated signal generated in this way is transmitted to the transmitting amplifier 19.
After being amplified at , it is sent out to power line 3 via coupler 8 .

On the other hand, the power supply synchronous clock generation circuit 2 in the receiving device 2
0, as shown in FIG. 3, converts the vCO 25 in the power synchronized clock generation circuit 17 shown in FIG. In addition to the clock pulses CP, CP2, a clock pulse CP having a frequency M times that of the clock pulse CPI can be extracted from the output side of the VCO 25a.

Next, the M-sequence code generator 32b in the receiving M-sequence generating circuit 21 converts the transmitting M-sequence code generator 32b shown in FIG.
Since it has the same configuration as the sequence code generation circuit 18, the M sequence code synchronized with the AC power supply is generated from the shift register 6a as in the case described above, and the M sequence code generated from the AND gate 28 is generated. A signal A is generated indicating the period of the code.

Next, the shift register 33 in the phase shift section 32b
is an M-sequence code generated from the M-series code generation section 32a (in this case, the output of the flip-flop circuit FF2 constituting the shift register 6a) every time the clock pulse CP supplied from the power supply synchronized clock generation circuit 20 is supplied. are gradually shifting to Therefore, from each stage of the shift register 33, the M-sequence code is sequentially phase-shifted and supplied to the selector 34. Selector 34
selects the output of the shift register 33 according to the output value of the counter 41, so that the selector 34 outputs the M-sequence code supplied from the M-sequence code generation section 32a in an amount corresponding to the instruction from the shift control section 32C. By being phase-shifted, it is supplied to the spectrum despread demodulation circuit 16 shown in FIG. 2 as an M-sequence code M2.

Next, the correlator 35 in the shift control section 32c inputs the M sequence code M2 output from the phase shift section 32b and the reception modulation signal supplied from the reception amplifier 22 shown in FIG. The correlation between the sequence code M2 and the M sequence code included in the received modulated signal is determined, and a correlation signal having a corresponding level according to the correlation characteristics shown in FIG. 7 is output.

Here, since the code pattern of the M-sequence code M2 is the same as the M-sequence code used for spread spectrum modulation of the transmission data on the transmitting side, the correlation signal output from the correlator 35 is the same as the received modulated signal. This represents the amount of phase shift of the M-sequence code M2 used for demodulation of the included M-sequence codes.

Correlator 3 representing the amount of phase shift extracted in this way
After the polarity of the output signal No. 5 is aligned in one direction in the absolute value circuit 36, the output signal is compared with the reference value Va supplied from the variable resistor 38 in the comparator 37. Here, before the transmitter 1 starts transmission, no correlation can be obtained in the correlator 35, so the output signal E of the absolute value circuit 36 is as shown in FIG. The output signal F of the comparator 37 during this period remains in the "H" state as shown in FIG. 6(b).The difference circuit 39 uses an absolute value circuit as its input signal. Since the output signal E of the comparator 36 continues to be in the zero state, its output signal G is "L" as shown in FIG. For this reason, the flip-flop circuit 40 with reset priority continues to be in the reset state,
The output signal H continues to be at the "L" level as shown in FIG. 6 (dl).The counter 41 has the input data Since the output signal H of the flip-flop circuit 40 continues to be in the "L" state, the M output from the AND gate 28 of the M sequence code generation section 32a
Even if the signal A shown in FIG. 6 tel indicating the cycle of the sequence code is supplied to the clock input terminal of the counter 41, the counted value is not the precented value X as shown in FIG. 6(f).
It will remain as it is.

Therefore, the value of the shift control signal ■ supplied from the counter 41 to the selector 34 is X, and the selector 34 selects and outputs the output of the shift register 33 in accordance with this X. In other words, the M-sequence code M2 that is phase-shifted by an amount corresponding to the X value is extracted from the M-sequence code supplied from the M-sequence code generator 32a.

Next, at a time point L1 shown in FIG. M-sequence code M2 output from
Find the correlation with In this case, the counter 41 is set so that a certain degree of correlation is obtained, that is, the output signal E of the absolute value circuit 36 is equal to or higher than the reference value Va.
Since a preset value X is determined for the output signal E, the output signal E rises above the reference value Va as shown at time t1 in FIG. 6(a). Furthermore, when the output signal E exceeds the reference value Va at time t1, the output signal F increases as shown in FIG.
Since I('' is reversed to "L" as shown in l,
Reset % light control for flip-flop circuit 40 is released. Furthermore, since the counter 41 uses the output signal F of the comparator 37 as a preset control input, the input data X remains preset while the signal F is "H" as shown in FIG. 6(f). However, when the signal F is reversed from "H" to "L" at a certain point, the preset state is canceled and the M-sequence code generator 3
Each time the signal A shown in FIG. 6(8), which is supplied every cycle of the M-sequence code generated from 2a, is supplied, this signal A is sequentially changed from the preset value X to X+1. X+2...
... and count. The count value of this counter 41 is then supplied as a phase shift control signal I to the selector 34 of the phase shift section 32b. The selector 34 selects and outputs the output of each stage of the shift register 33, which outputs M-sequence codes whose phases are sequentially shifted, according to the phase shift control signal I. Therefore, in this case, the phase shift control signal I causes every cycle of the M-sequence code generated from the M-sequence code generating section 32a, that is, the entire M-sequence code is
” and every time signal A is generated, shift register 3
The selection position for the third output stage is stepped up, and the phase of the output M-sequence code M2 is sequentially shifted. In this way, when the phase of the M-sequence code M2 is shifted, the phase shift with the M-sequence code included in the received modulated signal supplied from the receiving amplifier 22 is reduced.
As the output of the correlator 35 increases, the output signal E of the absolute value circuit 36 sequentially increases as shown in FIG. 6(d) after time t1. Then, when the synchronization condition of the correlation characteristics shown in FIG. 7 is satisfied, the output signal E of the absolute value circuit 36 reaches the maximum value as shown at time t2. When the maximum value is reached, there is no subsequent increment, so that the difference circuit 39 generates a signal G shown at time t2 in FIG. 6(C). Therefore, the difference circuit 39 generates the output signal H when the maximum value portion of the signal E, that is, the M-sequence code M2 is synchronized with the M-sequence code included in the received modulated signal. When the output signal G is generated from the differential circuit 39, the flip-flop circuit 40 is set by this signal G, so that the output signal H becomes 6H'' as shown at time t2 in FIG. 6 (dl). It is supplied to the enable control terminal of the counter 41.

As a result, the counter 41 subsequently receives M at the clock input terminal.
Since counting of the signal A supplied from the sequence code generator 32a is stopped, the value of the shift control signal I output from this counter 41 is changed to the preset value X at time 1. From t
X, which is the sum of the number α of signals A generated in the period up to t
Fixed at +α. Therefore, the M-sequence code M2 supplied from the phase shifter 32b to the correlator 35 and the spectrum despread demodulation circuit 16 shown in FIG. 1 is in phase with the M-sequence code included in the received modulated signal.

That is, in the power line 3, the phase of the transmitting side and the receiving side changes due to the load, and the zero-crossing point often fluctuates. Therefore, even if the transmitting side and the receiving side simply generate M-sequence codes having the same code pattern in synchronization with the zero-crossing point of the AC power supply, the demodulation generated on the receiving side will Since complete synchronization between the M-sequence code and the M-sequence code included in the received modulated signal cannot be obtained, demodulation processing becomes unstable. On the other hand, in the receiving M-series code generation circuit 21, first, the power supply synchronous clock generation circuit 2
The clock pulse CP+ output from 0 is synchronized with the AC power supply by the M-sequence code generation unit 32a based on CF2, and is the same code as the M-sequence code for spread spectrum that is generated in synchronization with the AC power supply on the transmitting side. The M-sequence code of the pattern is generated. Then, this M-sequence code is extracted via the phase shift section 32b, and by supplying the M-sequence code M2 outputted from this phase shift section 32b and the received modulation signal to the phase shift control section 32c,
The correlation between the M-sequence code M2 and the M-sequence code included in the received modulated signal is determined, and a shift control signal is generated to control the phase shift amount of the phase shifter 32b so that the absolute value of this correlation output becomes the maximum. ing. That is, this receiving M-sequence code generation circuit 21 calculates the correlation between the M-sequence code generated in synchronization with the AC power source and the M-sequence code included in the received modulated signal, and the absolute value of this correlation output is the maximum value. For example, by shifting the phase of the M-sequence code over the range of the shift width S between the transmitter and receiver as shown in FIG. 7, the phase is aligned with the M-sequence code included in the received modulated signal. Become.

As a result, even if the zero-crossing points on the transmitting side and the receiving side deviate depending on the state of the load connected to the power line 3, the phase shift control section 32C controls the phase shift section 32b to generate the M-sequence code for reception. This means that the phase of M2 is instantaneously matched to the M sequence code included in the received modulated signal.

The reason why the preset value is obtained by generating an output signal E greater than the reference value Va from the absolute value circuit 36 and changing the output signal F of the comparator 39 from "H" to "
When the selector 34 is configured to select the M-sequence code M2 that satisfies the above conditions in the initial state, the counter 41 starts counting. Preset operation becomes unnecessary.

On the other hand, the spectrum despread demodulation circuit 16 shown in FIG.
The received data is extracted by multiplying and demodulating 2. Here, the demodulating M-sequence code M2 generated from the receiving M-sequence code generation circuit 21 is subjected to synchronization control so as to be synchronized with the M-sequence code included in the received modulated signal output from the receiving amplifier 22. Therefore, the demodulation operation in the spectrum despread demodulation circuit 16 is reliable.

Next, at time t3 shown in FIG. 6(a), when the transmission operation of the transmission data by spread spectrum modulation from the transmitting device 1 is completed, the phase shift control unit 3 shown in FIG.
The correlator 35 constituting the 2C can no longer correlate the M-sequence code M2 generated from the phase shifter 32b with the output signal of the receiving amplifier 22, and the output signal E of the absolute value circuit 36 becomes as shown in FIG. In a), it becomes zero as shown at time t3. When the signal E becomes zero, the output signal F of the comparator 37
As shown at time t3 in FIG. 6 (bl), from "L" to "
Since it is inverted to "H", first flip-flop circuit 4
0 is reset and its output signal "H" becomes "L", enabling the counter 41 to perform a counting operation. Also,
When the output signal F of the comparator 37 is inverted to "H",
Since the counter 41 is set to the preset mode, the value of the counter 41 changes to the preset value X as shown after time t3 in FIG. Fixed.

Here, the reason why the preset value This is to set the correlation condition of the correlator 35 such that

In the above embodiment, the case where the transmitting device and the receiving device are made independent has been explained, but if the transmitting device and the receiving device are provided with a transmitting and receiving function, the same parts of the transmitting device 1 and the receiving device shown in Fig. 1 can be shared. It would be good if they were integrated.

Further, in the above embodiment, a case was explained in which a special circuit configuration was used to generate an M-sequence code synchronized with an AC power supply, but if the M-sequence code synchronized with an AC power supply is generated, Needless to say, any configuration may be used.

〔Effect of the invention〕

As explained above, the spread spectrum power line carrier communication method and apparatus according to the present invention is capable of transmitting data by product modulating the transmitted data using an M-sequence code generated in synchronization with an AC power source on the transmitting side. A spread spectrum modulation signal is generated and supplied to the power line, and on the receiving side, an M-sequence code generated in synchronization with the AC power source is used.
Correlation between the M-sequence code synchronized with the AC power source generated on the receiving side and the received modulated signal in spread spectrum power line carrier communication in which received data is extracted by multiplying and demodulating the received modulated signal sent via the power line. The phase of the M-sequence code is shifted so that the correlation value is maximized, and the M sequence code is used to demodulate the received modulated signal.
This is used as a series code. Therefore, even if the phase of the AC power supply on the receiving side shifts depending on the state of the load connected to the power line, the correlation between the M-sequence code generated in synchronization with the AC power supply and the M-sequence code included in the received modulated signal The phase of the M-sequence code for demodulation is adjusted so that it is synchronized with the M-sequence code included in the received modulated signal, since the phase-shifted code that has the maximum value is used as the M-sequence code for demodulation. This has an excellent effect in that demodulated data can always be reliably extracted.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration for explaining one embodiment of the spread spectrum power line carrier communication method and device according to the present invention, and FIG. 2 is a power synchronization clock generation circuit used in the transmitting device shown in FIG. 1. and FIG. 3 is a circuit diagram showing a specific example of a transmission M-series code generation circuit, and FIG. , FIG. 4 is a circuit diagram showing a specific example of the differential circuit shown in FIG. 3, and FIG.
) to (J) are operation waveform diagrams of each part of the circuit shown in Figure 2, and Figure 6.
Figures (a) to (f) are operational waveform diagrams of each part of the circuit shown in Figure 3, Figure 7 is a diagram showing the correlation characteristics of the correlator shown in Figure 3, and Figure 8 is a diagram of conventional spread spectrum power line carrier communication. FIG. 9 is a block diagram showing the apparatus; FIG. 9 is a circuit diagram showing a specific example of the transmission M-sequence code generation circuit shown in FIG. 8; FIGS.
1 is an operation waveform diagram of each part of the circuit shown in FIG. 9. 1 is a transmitting device, 2 is a receiving device, 3 is a power line, 7 is a spread spectrum modulation circuit, 8.13 is a combiner, 16 is a spectrum despread demodulation circuit, 17.20 is a power synchronization clock generation circuit, 18 is for transmission M-sequence code generation circuit, 19 is a transmission amplifier, 21 is a reception M-series code generation circuit, 22 is a reception amplifier, 32a is an M-series code generation section, 32b is a phase shift section, 32C is a phase shift control section, 33 is a shift 34 is a selector, 35 is a correlator, 36 is an absolute value circuit, 37 is a comparator, 38 is a variable resistor, 39 is a differential circuit, 40 is a flip-flop circuit, and 41 is a counter.

Claims (2)

[Claims] (1) By multiply modulating the M-sequence code generated on the transmitting side and the transmitting data, a modulated signal in which the transmitting data is spread spectrum is generated and supplied to the power line. In a spread spectrum power line carrier communication method in which received data is multiplied and demodulated using an M-sequence code having a code pattern and a received modulated signal received via a power line, the M-sequence code on the transmitting side is synchronized with an AC power supply. The M-sequence code for demodulation on the receiving side is generated in such a way that the correlation value between the M-sequence code generated in synchronization with the AC power source and the M-sequence code included in the received modulated signal is maximized. A spread spectrum power line carrier communication method characterized by using a phase-shifted power line. (2) A transmission M-sequence code generation circuit that generates an M-series code synchronized with the AC power flowing through the power line used as a transmission path, and an M-series code generation circuit that outputs the M-series code from this transmission M-series code generation circuit.
a transmitting device having a spread spectrum modulation circuit that supplies a modulated signal in which transmission data is spectrum-spread to a power line by performing product modulation on a sequence code and transmission data;
A receiving M-sequence code generation circuit that generates an M-sequence code for demodulation, and an M-series code generation circuit that generates an M-sequence code for demodulation, and
A receiving device includes a spectrum despreading demodulation circuit that extracts received data by multiplying and demodulating a sequence code and a received modulated signal received via a power line, and the receiving M-sequence code generating circuit is connected to an AC power source. an M-sequence code generation unit that generates an M-sequence code synchronized with the M-sequence code; a phase shift unit that shifts the phase of the M-sequence code output from the M-sequence code generation unit; and an M-sequence code output from the phase shift unit. and a phase shift control unit that controls the phase shift amount of the phase shift unit so that the correlation value with the M-sequence code included in the received modulated signal is maximized, and the output of the phase shift unit is used for demodulation. A spread spectrum power line carrier communication device characterized in that the M-sequence code is supplied to the spectrum despread demodulation circuit.