JPS6230427A - Method and equipment for spread spectrum power line carrier communication - Google Patents

Abstract

PURPOSE:To prevent the influence to be exerted upon other appliances by selecting function adding the 2nd clock pulse frequency for moreover modulating a signal obtained by modulating transmitting data by using a clock pulse frequency for generating an M-sequence code and the M-sequence code. CONSTITUTION:A power supply synchronizing clock generating circuit 4 in a transmitting device 1 generates the 1st clock pulse CP1 synchronized with an AC power supply and having 2N times the frequency of the AC power supply when the maximum period length of the M-sequence code is N and an optional integer is K and a synchronizing pulse S synchronized with the AC power supply and having 2N times the frequency. A transmitting M-sequence code generating circuit 5 generates an M-code by using the 1st clock pulse CP1 as a reference clock. A spectrum diffusion modulating circuit 6 outputs a spread spectrum modulating signal in which transmitting data in a narrow band are uniformly distributed over a wide band by modulating the product of the M-sequence code and the transmitting data. A clock oscillating circuit 7 generates the 2nd clock pulse CP2 and a modulating circuit 8 modulates the product of the 2nd clock pulse CP2 and the spread spectrum modulating signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to spread spectrum power line carrier communication that uses power lines to transmit data, and in particular, to reduce the influence on other equipment connected to the power lines. The present invention relates to a communication method and device.

[Prior art]

Conventionally, when transmitting data using power lines, various modulation methods have been used depending on the type of transmission path. For example, in the case of a power transmission line transmission line, a single sideband modulation method is used, and in the case of a distribution line transmission line, a frequency modulation method or a phase modulation method is used. Here, power lines are not laid with data transmission in mind, so if you try to transmit data,
The problem is that various types of noise enter, or that the transmission characteristics fluctuate significantly depending on the load situation. In other words, the high-frequency characteristics of a power line, regardless of whether it is a power transmission line or a power distribution line, have large corona noise and load noise, and vary greatly depending on the load state of the power line. Therefore, it has been difficult to perform highly reliable data transmission, and particularly high-speed data transmission has been impossible.

By the way, research has recently been underway to actively utilize spread spectrum communication methods in various fields.
Explanations of its principles and fields of application are disclosed in the September issue of the Journal of the Institute of Electronics and Communication Engineers, page 965 of the September issue of 1981, and page 1053 of the October issue of the Journal. This spread spectrum communication method is characterized by a wide spectrum, the use of special codes, and correlated signals, and when used for data transmission using power lines, it is less susceptible to noise and transmission characteristics. , it becomes possible to perform high-speed data transmission with high reliability. In other words, this spread spectrum power line carrier communication system transmits narrowband transmission data by spreading the spectrum evenly over a wide band, so zero points may occur in the transmission characteristics depending on the load condition of the power line. The signal-to-noise ratio is almost unaffected, and even if narrowband noise is mixed, the correlation is taken on the receiving side, resulting in a large S/N ratio.

[Problem that the invention seeks to solve]

However, even in the above spread spectrum power line carrier communication method, if the transmission characteristics of the power line become extremely poor, normal communication becomes difficult. Therefore, in such a case, it is necessary to increase the transmission output on the transmitting side, but when the transmission output is increased, the transmission signal is broadened by spectrum spread, so it is possible to connect to the same power line. This may affect other devices. In other words, in an intercom using a power line carrier, the frequency is 230KHz or 270KHz, as shown in FIG.

It uses one of six bands of ±15 KHz with center frequencies of 310 KHz, 350 KHz, 390 KHz, and 430 KHz, and when the transmission output is increased, a spread spectrum modulated wideband output signal is transmitted using the above-mentioned power line carrier communication. This will affect the band used by the intercom.

[Means for solving problems]

Therefore, the spread spectrum power line carrier communication method and device according to the present invention spread spectrum modulates transmission data using an M sequence code supplied from a transmission M sequence code generation circuit, and transmits this modulated signal via a coupler. On the receiving side, the modulated signal sent via the power line is extracted using a coupler.
A receiving M which generates an M-sequence code whose phase and code pattern match the M-sequence code outputted from the transmission M-sequence code generation circuit from the modulated signal taken out from the coupler.
In spread spectrum power line carrier communication in which received data is extracted by despread spectrum demodulation using the output signal of the sequence code generation circuit, the spread spectrum modulated signal is re-modulated using a second clock pulse and outputted, By selecting the frequency of the first clock pulse for generating the M-sequence code used in spread spectrum modulation and the sequence length of the M-sequence code and the frequency of the second clock pulse, the transmission output can be adjusted to the frequency band used by other equipment. This is a setting requirement for setting a spectrum distribution that has no influence.

[For production]

In the spread spectrum power line carrier communication method and apparatus configured in this way, the relationship between the frequency of the first clock pulse used to generate the M-sequence code and the code length of the M-sequence code, or the relationship between the frequency of the first clock pulse used to generate the M-sequence code and the code length of the M-sequence code, By selecting a relationship in which the frequency of the second clock pulse that further modulates the spread spectrum modulation signal used to modulate the transmission data is added, the spectrum distribution of the transmission signal can be prevented from overlapping with the frequency band used by other equipment. Therefore, even if the transmission output is increased when the transmission characteristics of the power line become extremely poor, the effect on other devices connected to the same power line will be reliably prevented.

〔Example〕

FIG. 1 is a block diagram for explaining an embodiment of a spread spectrum power line carrier communication method and apparatus according to the present invention. In the figure, numerals 1 and 2 are a transmitting device and a receiving device connected via a power line 3. In the transmitting device 1, 4 is a power synchronized clock generation circuit, which is synchronized with the AC power supplied via the power line 3, and has a maximum cycle length of the M-sequence code to be used, where N is an arbitrary integer. a first clock pulse CP having a frequency /2X2N times the frequency of the AC power supply when
and is configured to generate. 5 is the first clock pulse CP output from the power supply synchronous clock generation circuit 4
, a transmission M-series code generation circuit that generates an M-series code whose generation cycle is synchronized with the synchronization pulse S using , as a basic clock;
Reference numeral 6 denotes a spread spectrum modulation circuit, which performs product modulation on the M-sequence code generated from the transmission M-sequence code generation circuit 5 and transmission data, thereby generating a spectrum in which narrow-band transmission data is uniformly distributed over a wide band. Outputs a spread modulation signal. 7 is a clock oscillation circuit that generates the second clock pulse CP2, and 8 is a modulation circuit that performs product modulation on the spread spectrum modulation signal supplied from the spread spectrum modulation circuit 6 and the second clock pulse CP, and outputs the product modulated signal. . 9 is a transmission amplifier that amplifies the modulated output of the modulation circuit 8;
10 connects the transmission output output from the transmission amplifier 9 to the power line 3.
This is a coupler for supplying the power to the inverter, and is composed of a transformer 11 and capacitors 12a and 12b.

Next, in the receiving device 2, 13 is a power synchronized clock generation circuit having the same configuration as the aforementioned power supply synchronized clock generation circuit 4, and 14 is a receiving M sequence code generation circuit having the same configuration as the aforementioned transmission M sequence code generation circuit 5. A code generation circuit 15 is a coupler for taking out a transmission signal supplied via the power line 3, and is composed of a transformer 16 and capacitors 17a and 17b. 18 is a reception amplifier that amplifies the output of the coupler 15; 20 is a clock oscillation circuit that generates the second clock pulse cP2; 2o is a demodulation circuit;
A spread spectrum modulation signal is extracted by product demodulating the output signal of the receiving amplifier 18 using the clock pulse CPt. Reference numeral 21 denotes a spectrum despread demodulation circuit, which receives M output from the reception M-series code generation circuit 14.
Received data is output by product demodulating the spread spectrum modulation signal output from the demodulation circuit 20 using the sequence code.

FIG. 2 shows the power supply synchronous clock generation circuit 4 shown in FIG.
13 and a circuit diagram showing a specific example of the transmitting/receiving M-sequence code generation circuit 5.14. In the figure, 22 is the power line 3
23 is a phase comparator that compares the phase of an AC power supply (AClooV) supplied via a frequency divider 26 and an output signal of a frequency divider 26, which will be described later, and outputs a signal with a level corresponding to the phase difference. A low-pass filter that smoothes the output of 2
4 is a voltage-controlled variable frequency oscillator (hereinafter referred to as VCO) whose controller is the output signal of the low-pass filter 23, and generates a first clock pulse CP. 25 is a frequency divider which divides the first clock pulse CP into 1/2N, where N is the maximum period of the M-sequence code generated from the transmitting/receiving M-sequence code generation circuits 5 and 14. synchronized pulse S
occurs.

26 is the synchronization pulse S output from the frequency divider 25 by 2/K
(K is an arbitrary integer) and supplies the frequency to the phase comparator 22. These phase comparators 22.
Low pass filter 23. VCO24, frequency divider 25.26
By configuring a phase-lon loop (PLL) circuit, the first clock pulse CP1 is synchronized with the AC power supply and has a frequency NXK times that of the AC power supply, and the first clock pulse CP1 is synchronized with the AC power supply and has a frequency of 2N with respect to that frequency. This means that twice as many synchronizing pulses S are generated.

Next, the transmitting/receiving M-series code generation circuit 5.14 includes a shift register 27 in which a flip-flop circuit F r -F F * is connected in series and a flip-flop circuit F.
Fz, FF An exclusive OR gate 28 calculates an exclusive OR for the output signal of F3 and returns it to the input side.
” An M-sequence code with a maximum code length of −1 is generated. Reference numeral 29 is an AND gate that obtains a match for all stage outputs of the shift register 27, and 30 is an AND gate that divides the output of the AND gate 29 into 1/2. 31 is an exclusive OR gate for determining the mismatch between the output signal of the frequency divider 3o and the synchronization pulse S; 32 is an exclusive OR gate that calculates the mismatch between the output signal of the exclusive OR gate 31 and the first
It is an OR gate that receives a clock pulse CP, and its output signal is supplied to the clock input terminal CK of the shift register 27. And these AND gates 291
Frequency divider 30. The exclusive OR gate 31 and the OR get 32 constitute a synchronization control circuit for synchronizing the M-sequence code generated from the shift register 27 with the AC power supply.

In the spread spectrum power line carrier communication system configured in this way, when power is supplied to the sending bag W1 and the receiving device 2, first the power synchronized clock generating circuits 4, 13
is supplied via the power line 3 (AClooV>
A first clock pulse CP and a synchronization pulse S are generated in synchronization with the first clock pulse CP and the synchronization pulse S.

That is, in FIG. 2, the clock pulse CP generated from the VCO 24 is sequentially divided in frequency by frequency dividers 25 and 26 and then supplied to the phase comparator 22. The phase comparator 22 connects the output signal of the frequency divider 26 and the AC power supply (ACloo).
V), and outputs a control signal that expresses the shift direction of the phase difference by a polarity and expresses the phase difference by a level.

This control signal is smoothed in the low-pass filter 23 and then supplied to the control signal input terminal of the VCO 24, thereby controlling the value of the control signal output from the phase comparator 22 to be small.

By repeating such control, that is, by performing phase-locked loop (PLL) control, the phase of the first clock pulse CP1 shown in FIG. 3) output from the VCO 24 changes to that shown in FIG. 3(a). It will be clocked to the phase of the AC power supply (AClooV) shown in FIG.

In this case, the first clock pulse CP is such that the frequency of the AC power source is expressed as the product of the frequency division values of both frequency dividers because the frequency dividers 25 and 26 are provided in the phase-locked loop. It has twice the frequency as N-. Also, from the frequency divider 25, the first clock pulse C
The synchronizing pulse S whose frequency is divided by 1/2N is shown in Fig. 3 (f
) is output as shown. And this synchronization pulse S
Since it is generated based on the first clock pulse CP+, it is synchronized with the AC power supply (AClooV), and the frequency division value of the frequency divider 25 is 2N, so it is used in this system. The AC power supply (AClooV) shown in FIG. ) and has twice the frequency.

In this way, the first clock pulse CP and synchronization pulse S generated from the power synchronization clock generation circuit 4 are as follows:
The signal is supplied to the transmission M-sequence code generation circuit 5. In FIG. 2, the first clock pulse CP + is the OR gate 32.
Since the output signal of the exclusive OR gate 28 of the shift register 27 is sequentially shifted, the output of each flip-flop FF I=FF 3 is supplied to the clock input terminal CK of the shift register 27 through Figure 3 (C
) to (e), the output of the shift register 27, that is, the output of the flip-flop FF, is output as an M-sequence code having a code pattern determined by the input conditions of the exclusive OR gate 28.

Here, when turning on the power or in reset mode,
For example, at point 1 shown in FIG. When the shift register 27 is cleared as shown in FIG.
The output signals of F are set to all "1's" as shown in FIG. The output signal A of 29 becomes "H" as shown in FIG. 3 U), and after being divided by 2 in the frequency divider 30, it is output as the output signal B shown in FIG.
1. In other words, in normal times, the signal B output from the frequency divider 29 is "H" every cycle of the M-sequence code.
", the signal is inverted to "L". The output signal B generated in this way is compared with the synchronizing pulse S in the exclusive OR gate 31, and if the two match, the output signal B is generated. This means that the M-sequence code is synchronized with the AC power supply (AClooV).

However, when the synchronization pulse S is inverted from "H'" to "L" at time t, the output signal B of the frequency divider 30 and the synchronization pulse S do not match, so the exclusive OR gate 3
The output signal C of 1 becomes "H" as shown in FIG. 3(h). Here, when the output signal C becomes H", the OR gate 3
2 fixes its output signal to "H" as shown in FIG. 3(1) even though the first clock pulse CP1 is supplied. In other words, during the period when the output signal B of the frequency dividing circuit 30 indicating the cycle of the actually generated M-sequence code does not match the synchronization pulse S indicating the generation cycle of the M-series code synchronized with the AC power supply, Since the signal C shown in FIG. 3(h) output from the OR gate 31 becomes "H", the "H" portion of this signal C causes the first clock pulse CP passing through the OR gate 32 to become "H". ``By fixing it in a state, you end up cutting it. Therefore, as shown in FIG. 3(1), the shift register 27 maintains the state in which the clock pulses D indicated by ■ to ■ are supplied.

Next, at time t4, when the synchronizing pulse S is inverted to "H", the output signal C of the frequency divider 3o shown in FIG.
As shown in FIG.
1) as the clock pulse D shown in shift register 27.
will be supplied again.

In FIG. 3(1), after the clock pulse D indicated by ■ is generated at time t, when the clock pulse D indicated by ■ rises at time t, the flip-flops FF, ~FF, Since the outputs of the AND gate 29 are all "H" as shown in FIG. 3(C) to (e), the output signal A of the AND gate 29 becomes H at time t6 as shown in FIG.
Since this inversion of the output signal A to "H" is the second time since time 1, the output signal B of the frequency divider 30 is inverted to "L" accordingly. When the output signal B becomes "L", there is a mismatch with the synchronizing pulse S, so the output signal C of the exclusive OR gate 31 becomes "H", and the clock pulse D is supplied to the shift register 27. to prevent

Next, at time t, when the synchronizing pulse S is inverted to "L", the output signal C of the exclusive OR gate 31 is also inverted to "L", so the clock pulse is output from the OR gate 32. D at time tI+ 9+ in FIG. 3(1)
tl. −・・−−−−−−−−・■、■、■−・−
It is outputted as shown as and supplied to the shift register 27. After this time t8, the clock pulse D supplied to the shift register 27 is
The numbers ■, ■, ■ shown in FIG. 3 (1) are counted repeatedly for each maximum code length of the M-sequence code from time 1t.
Figure 3 (bl The numbers 2.3, 4.-- of the first clock pulse CP1 shown in FIG.

In other words, the output signal B of the frequency divider 29, which is inverted to "H" and "L" every cycle of the M-sequence code generated from the shift register 27, generates the M-sequence code in synchronization with the AC power supply AC100V. Indicates the period when the
A clock pulse D is supplied to the shift register 27 in synchronization with a synchronizing pulse S (inverted to H'', 'L'').
will be thinned out.

In this way, once the M-sequence code generated from the shift register 27 is synchronized with the AC 100V AC power supply, this state is locked, and from then on, the power supply synchronous clock generation circuit 4 generates the first clock pulse CP completely synchronized with the AC power supply 100V AC. , and since the synchronization pulse S continues to be generated,
Even if the phase of the AC power source fluctuates somewhat for some reason, the generated M-sequence code will always be synchronized with the AC power source. Such an operation is performed instantaneously when the power is turned on.

In this way, the M-sequence code generated from the transmission M-sequence code generation circuit 5 is multiplicatively modulated with the transmission data in the spread spectrum modulation circuit 6, so that the narrowband transmission data is uniformly spread over a wide band. It is output as a spread spectrum modulated signal. The generated modulation signal is subjected to product modulation in the modulation circuit 8 with the second clock pulse CP supplied from the clock oscillation circuit 7, so that the distribution position of the spread spectrum modulation signal becomes the first For example, the frequency of the first clock pulse CP is set to 280 KHz, which is adjusted in relation to the frequency of the clock pulse cP1 and the maximum code length of the M-sequence code.
, the maximum code length of the M-sequence code is 2''-1-7, and the frequency of the second clock pulse CP: is 210 KHz, the signal distribution of the spread spectrum modulation signal is as shown in Fig. 4, and as shown in Fig. 5. This results in a state where the band used by the intercom using power line carrier communication shown in is not affected at all.

The output signal of this modulation circuit 8 is amplified in a transmission amplifier 9 and then supplied to the power line 3 via a coupler 10.

On the other hand, the power supply synchronous clock generation circuit 1 in the transmitter 2
3 and the reception M-series code generation circuit 14 have the same configuration as the power synchronization clock generation circuit 4 and the transmission M-series code generation circuit 5 in the transmitter 1, as shown in FIG. As in the case of the transmitter 1 described above, as the first clock pulse CP synchronized with the AC fi (AClooV) and the synchronization pulse S are generated, the M synchronized with the AC power supply is generated. The sequence code is M for reception.
It will be generated from the series code generation circuit 14. The coupler 15 extracts only the modulated signal supplied from the transmitter 1 via the power line 3. This modulated signal is then amplified in the reception amplifier 18 and then supplied to the demodulation circuit 20. The demodulation circuit 20 performs product demodulation on the second clock pulse CP supplied from the clock oscillation circuit 19 and the modulation signal supplied from the reception amplifier 18 to extract a spread spectrum modulated signal and send it to the spectrum despread demodulation circuit 21. supply Spectrum despread demodulation circuit 2
1 extracts received data by performing product demodulation on the M-sequence code supplied from the reception M-sequence code generation circuit 14 and the spread spectrum modulation signal supplied from the demodulation circuit 20 .

Here, M output from the transmission M-sequence code generation circuit 5
Since both the series code and the M-sequence code generated from the reception M-sequence code generation circuit 14 are generated in synchronization with the AC power supply, they are completely synchronized. Therefore, since the spectrum despread demodulation circuit 21 performs product demodulation of the received spread spectrum modulated signal using the same M-sequence code as used during modulation, it is possible to reliably extract received data that is the same as transmitted data. . Furthermore, if the transmission characteristics of the power line 3 as a transmission path are significantly degraded for some reason, erroneous reception will occur frequently.
In this case, since the spectrum distribution of the transmitted signal has been adjusted so as not to affect other equipment as described above, the gain of the transmitting amplifier 9 in the transmitting device 1 is increased to ensure reliable reception. Transmission power can be increased so that

In addition, in the above embodiment, the case was explained in which consideration was given only to the band used in an intercom using high frequency carrier communication, but the present invention is not limited to this, and may be applied to other Similarly, the spectrum distribution can be easily set without affecting the frequency band used in the equipment. Furthermore, the clock pulses used to generate the M-series code do not necessarily have to be synchronized with the power supply; in short, any generation circuit can be used as long as the clock pulses for transmission and reception are synchronized. good.

〔Effect of the invention〕

As explained above, in the spread spectrum power line carrier communication method and device according to the present invention, the spectrum distribution of the transmission output can be easily and variably set as desired. By setting a spectrum distribution that does not overlap with the frequency band used by the equipment being used, it is possible to increase the transmission output without affecting other equipment. It has the excellent effect of measuring the reliability of communication.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram for explaining an embodiment of the spread spectrum power line carrier communication method and device according to the present invention, and FIG. 2 is a power synchronization clock generation circuit and M-series codes for transmission and reception shown in FIG. 1. A block diagram showing an example of a generating circuit, FIG. 3 (al to 0) is a waveform diagram of each part to explain the operation of FIGS. 1 and 2, and FIG. 4 is a diagram showing output from the transmitting device shown in FIG. 1. FIG. 5 is a diagram showing an example of a spectrum distribution of transmission output, and FIG. 5 is a diagram showing an example of a frequency band used by an intercom using power line carrier communication. DESCRIPTION OF SYMBOLS 1... Transmitting device, 2... Receiving device, 3... Power line, 4.13... Power supply synchronous clock generation circuit, 5.14
... M-sequence code generation circuit for transmission/reception, 6... Spread spectrum modulation circuit, 7.19... Clock oscillation circuit, 8.20... Modulation circuit, 9... Transmission amplifier, 10
゜15...Coupler, 18...Reception amplifier, 21...
・Spectrum despread demodulation circuit.

Claims (4)

[Claims] (1) By multiply modulating the M-sequence code generated on the transmitting side and the transmitting data, a modulated signal in which the transmitting data is spread spectrum is generated and supplied to the power line, and the transmitting side In a spread spectrum power line carrier communication method in which received data is multiplied and demodulated using the same M-sequence code and a modulated signal received via a power line, the spread spectrum modulated signal on the transmitting side is transmitted using a clock pulse. transmitting the M-sequence code to the receiving side via the power line after re-modulating the M-sequence code, and selecting the relationship between the frequency of the clock pulse used when generating the M-sequence code and the clock pulse used during re-modulation and the maximum code length. A spread spectrum power line carrier communication method, characterized in that the spectral distribution of transmission output is set in a state that does not affect other devices connected to the power line. (2) By setting the frequency of the clock pulse used to generate the M-sequence code to 280 KHz, the frequency of the clock pulse used for remodulation to 210 KHz, and the maximum code length of the M-sequence code to 7 bits, the spectral distribution of the transmission output can be improved. 230KHz, 270KHz, 310KHz, 3
Spread spectrum power line carrier according to claim 1, characterized in that the spread spectrum power line carrier is set so as not to affect the frequency band of an intercom system having a band of ±15 KHz with one of 50 KHz, 390 KHz and 430 KHz as the center frequency. Communication method. (3) Consisting of a transmitting device and a receiving device connected via a power line used as a transmission path, the transmitting device includes a clock generating circuit that generates a first clock pulse, and a first clock pulse that is output from the clock generating circuit. A transmission M-sequence code generation circuit that generates an M-sequence code in response to a clock pulse, a spread spectrum modulation circuit that spread-spectrum modulates transmission data using the M-series code, and a clock oscillation circuit that generates a second clock pulse. a modulation circuit that modulates the output of the spread spectrum modulation circuit using the second clock pulse; and a coupler that supplies the output of the modulation circuit to the power line, and the receiving device uses the first clock pulse to modulate the output of the spread spectrum modulation circuit. a clock generation circuit that generates a first clock pulse having the same frequency as the clock pulse, and an M-sequence code that uses the clock pulse to generate an M-sequence code that has the same code pattern as the M-sequence code generated in the transmitter. a second clock oscillation circuit that generates a second clock pulse having the same frequency as the second clock pulse in the transmitting device; and a second clock pulse generated from the second clock oscillation circuit. a demodulation circuit that extracts a spread spectrum modulated signal by demodulating the output of a coupler connected to the power line, and demodulating the output of the demodulation circuit using an M-sequence code generated from the M-sequence generation circuit. and a spectrum despread demodulation circuit that extracts received data by the transmitting/receiving device, and the frequencies of the first and second clock pulses and the maximum code length of the M-sequence code in the transmitting/receiving device are determined by the transmission rate sent out from the transmitting device. A spread spectrum power line carrier communication device characterized in that the output is selected to have a spectrum distribution that does not affect other devices. (4) Spread spectrum power line carrier communication according to claim 3, wherein the clock generation circuit in the transmitting/receiving device generates the first clock pulse in synchronization with the AC power flowing through the power line. Device.