JPH08274685A - Spread spectrum reception equipment - Google Patents

Abstract

PURPOSE: To provide the spread spectrum reception equipment which accurately makes the spread code on the transmission side and that on the reception side coincide with each other. CONSTITUTION: A frequency dividing circuit 14 which divides the frequency or the output signal or a VCO 10 synchronized with the phase or the output signal of a multiplier 2 by PLL operation, a first spread code generation circuit 3 which generates a spread code PO in accordance with the output signal of the frequency dividing circuit 14, a second spread code generation circuit 15 which generates first to third spread codes P1 to P3 in accordance with the spread code PO, a second selection circuit 16 which selects one of first to third spread codes P1 to P3 and applies the selected spread code to the multiplier 2, a correlation detection circuit 18 which detects correlations in accordance with the output signal of the multiplier 2, and a control circuit 18 which generates a second control signal in accordance with the output signal of the correlation detection circuit 18 are provided. The output generation timing of the frequency dividing circuit 10 is controlled in accordance with the second control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct sequence spread spectrum receiver, and prevents generation of a phase error between a PN code on a transmission side and a PN code on a reception side when a phase locked loop is used for synchronization acquisition and holding. Spread spectrum receiver.

[0002]

2. Description of the Related Art Conventionally, as one of wireless communication systems,
Spread spectrum communication systems are widely known. In this spread spectrum system, a carrier side is modulated with an information signal such as voice or data on the transmitting side, and M is added to the information modulated signal.
Spread spectrum is performed by multiplying by a spreading code such as a sequence. Then, the spread spectrum signal is transmitted from the antenna. On the other hand, on the receiving side, the received spread spectrum signal is multiplied by the same spreading code as on the transmitting side to perform despreading, and further information demodulation is performed to obtain an information signal.

In such a spread spectrum communication system, when despreading on the receiving side, the spreading code created on the receiving side and the spreading code in the received signal must be synchronized and multiplied. Therefore, conventionally, as shown in FIG. 2, a spread spectrum receiving apparatus has been proposed which maintains the synchronization relationship between the spreading code created on the receiving side and the spreading code in the received signal. In FIG. 2, the received spread spectrum signal is a frequency conversion circuit (1).
After the frequency is converted to a low frequency so that it can be easily processed by the circuit in the subsequent stage, the spread code generation circuit (3) is applied to the multiplier (2).
Is multiplied by the spreading code generated from The output signal of the multiplier (2) is phase-compared with the output signal of the VCXO (voltage controlled crystal oscillator circuit) (5) in the phase comparison circuit (4). The output signal of the phase comparison circuit (4) according to the result of the phase comparison is smoothed by the LPF (6) and then applied to the VCXO (5) as a control signal, and the VCXO (5) is supplied with the VCXO according to the control signal.
The oscillation frequency of O (5) is changed. The output signal of the VCXO (5) is applied to the phase comparison circuit (4), frequency-divided by the frequency dividing circuit (7) and then applied to the spread code generation circuit (3). Here, the multiplier (2), the phase comparison circuit (4), the VCXO (5), the LPF (6), the frequency dividing circuit (7) and the spreading code generating circuit (8) are so-called PLLs.
(Phase locked loop), and the PLL operates so that the phase difference between the two input signals of the phase comparison circuit (4) becomes zero. Therefore, the generation timing of the spread code from the spread code generation circuit (3) changes according to the change in the oscillation frequency of the VCXO (5), and the PLL causes the phases of the two input signals of the phase comparison circuit (4) to change. Operate in synchronization with each other, the output signal of the multiplier (2) and the VCXO (5)
The phase is synchronized with the output signal of.

After the PLL is locked, a spread code synchronized with the spread spectrum signal is generated, and the spread spectrum signal and the spread code are multiplied by the multiplier (2) to perform despreading. Then, the output signal of the multiplier (2) generated by despreading is passed through the BPF (8),
An information signal can be obtained by being applied to the demodulation circuit (9) and demodulated.

[0005]

In FIG. 2, since the PLL operates so that the phases of two input signals of the phase comparison circuit (4) are synchronized, the output signal of the multiplier (2) and the VCXO ( The phase difference with the output signal of 5) becomes zero. However, the phase of the spread code created on the receiving side does not exactly match the phase of the spread code in the spread spectrum signal due to the delay of the elements constituting the circuit of FIG. I couldn't.

[0006]

The present invention has been made in view of the above points, and is a spread spectrum receiving apparatus for receiving a spread spectrum signal, and a despreading circuit for despreading the spread spectrum signal. A phase synchronization circuit for generating an output signal synchronized with the phase of the output signal of the despreading circuit, and a clock signal generation circuit for generating a clock signal for spreading code according to the output signal of the phase synchronization circuit. , A spreading code generating circuit that generates a plurality of spreading codes according to an output signal of the clock signal generating circuit, and a correlation between the spread spectrum signal and the plurality of spreading codes according to an output signal of the despreading circuit. A correlation detection circuit for detecting, and a control circuit for generating a control signal for controlling an output phase of the clock signal generation circuit according to an output signal of the correlation detection circuit. And it features.

Further, the spreading code generating circuit is responsive to the output signal of the clock signal generating circuit to generate a first spreading code,
It is characterized in that a second spreading code advanced by a predetermined phase from the first spreading code and a third spreading code delayed by a predetermined phase from the first spreading code are generated. Further, the correlation detection circuit includes a level detection circuit that detects the level of the output signal of the first despreading circuit, and a holding circuit that holds the output signal of the level detection circuit.

Furthermore, the holding circuit comprises a capacitor for holding an output signal of the level detection circuit. Furthermore, the spreading code generating circuit is configured to output a first spreading code, a second spreading code advanced from the first spreading code by a predetermined phase, and a predetermined spreading code according to the output signal of the clock signal generating circuit. Generating a third spreading code delayed by the phase of, the holding circuit includes first to third holding circuits, and the first holding circuit includes the first holding circuit.
The output signal of the level detection circuit according to the spread code is held, the second holding circuit holds the output signal of the level detection circuit according to the second spread code, and the third holding circuit is An output signal of the level detection circuit according to the third spreading code is held.

Further, the level detection circuit detects the minimum value of the output signal level of the first despreading circuit. Further, the holding circuit is characterized by comprising an A / D conversion circuit for converting the output signal of the level detection circuit into a digital signal, and a memory for storing output data of the A / D conversion circuit.

Furthermore, the control circuit includes a comparison circuit and a control signal generation circuit, and the comparison circuit detects the changing direction of the correlation output according to the output signal of the correlation detection circuit, and performs the control. The signal generating circuit is characterized by generating a lead or lag control signal according to the output signal of the comparison circuit. Furthermore, the spreading code generation circuit is configured to advance the first spreading code and a second phase advanced from the first spreading code by a predetermined phase according to the output signal of the clock signal generation circuit.
A third holding code that generates a third spreading code delayed from the spreading code and the first spreading code by a predetermined phase, and the holding circuit holds a first holding circuit that holds the output signal of the level detection circuit according to the first spreading code. A second holding circuit that holds an output signal of the level detection circuit according to the second spreading code, and a third holding circuit that holds an output signal of the level detection circuit according to the third spreading code. The comparison circuit comprises: a first comparator for comparing output signals of the first and second holding circuits; a second comparator for comparing output signals of the first and third holding circuits; And a determination circuit that determines the direction of the correlation output according to the output signals of the first and second comparators.

When the output signal of the second holding circuit is larger than the output signal of the first holding circuit, the advance control signal is generated, and the output signal of the third holding circuit is the first holding circuit. The delay control signal is generated when the output signal is larger than the output signal of the circuit.

[0012]

According to the present invention, the output signal of the phase synchronization circuit generated in synchronization with the output signal of the despreading circuit is applied to the clock signal generating circuit to generate a clock signal for generating the spread code. The spread code generating circuit generates the first to third spread codes in accordance with the clock signal, and the spread code causes the spread spectrum signal to be reverse spread by the reverse spread circuit.
The output signal of the despreading circuit is applied to the correlation detection circuit,
By detecting the output signal level of the despreading circuit by the level detection circuit, the correlation between the spread spectrum signal and the spread code is detected. The output signal of the level detection circuit is held in the holding circuit, and the respective correlation outputs are compared by the comparison circuit. A control signal is generated from the control signal generation circuit according to the comparison result. The second spreading code is a code that is advanced from the first spreading code by a predetermined amount, and the third spreading code is the first spreading code.
Since the spread code is delayed by a predetermined amount from the spread code, it is possible to detect the phase shift between the spread code and the spread spectrum signal, and the phase control circuit advances the phase of the output signal of the phase locked loop circuit according to the control signal. , The phase of the input signal of the spread code generator is adjusted by controlling so that it is delayed, so the transmitter and the receiver can receive while maintaining the synchronization relationship between the output signal of the phase lock circuit and the carrier in the spread spectrum signal. It is possible to establish a synchronization relationship of the spreading code with the side. Therefore, accurate spectrum despreading can be performed, and good information demodulation can be performed in the subsequent circuit.

[0013]

FIG. 1 is a diagram showing an embodiment of the present invention,
(10) is a VCO whose oscillation frequency is variable, (11) is a DC voltage source for applying a DC voltage to the VCO (10), and (12) is either the output signal of the LPF (6) or the DC voltage. A first selection circuit for selecting one, (13)
Is a capture detection circuit for detecting synchronous capture according to the output signal of the first multiplier (2), (14) is a frequency divider circuit which is a clock signal generation circuit for generating a spread code, and (15) is a first A second spreading code generating circuit for generating first to third spreading codes P1 to P3 according to the spreading code P0 from the spreading code generating circuit (3), and (16) the first to third spreading code P
A second selection circuit for selecting one spread code from 1 to P3, (17) a correlation detection circuit for detecting the correlation between the spread spectrum signal and the spread code, and (18) a second selection circuit (16). A control circuit for controlling and controlling the frequency dividing circuit (14) according to the output signal of the correlation detecting circuit (17). The same circuits as those in the conventional example shown in FIG. 2 are designated by the same reference numerals as those in the conventional example shown in FIG. Also, V
The variable range of the frequency of CO (10) is VCX in FIG.
Since it is wider than that of O (5), it is used instead of VCXO (5).

In FIG. 1, a received spread spectrum signal is frequency-converted into a low frequency by a frequency conversion circuit (1), and then a second spread code described later by a first multiplier (2) (first despreading circuit). It is multiplied by the spread code generated from the generation circuit (15). Then, the output signal of the first multiplier (2) is phase-compared with the output signal of the VCO (10) in the phase comparison circuit (4). The output signal of the phase comparison circuit (4) corresponding to the result of the phase comparison is smoothed by the LPF (6) and then applied to the VCO (10) as its control signal via the first selection circuit (12). It Where the first multiplier (2),
Phase comparator circuit (4), LPF (6), VCO (10),
The frequency dividing circuit (14) and the first and second spreading code generating circuits (3) and (15) constitute a phase synchronization circuit, so-called PLL, and the phase difference between the two input signals of the phase comparison circuit (4) is 0. The PLL operates as described above.

Further, the output signal of the VCO (10) is applied to the phase comparison circuit (4) and the frequency division circuit (1
It is also applied to 4) and divided by m. Then, the spreading code P0 is generated from the first spreading code generation circuit (3) based on the frequency division output signal of the frequency division circuit (14). Further, according to the spread code, the second spread code generator circuit (15) serves as a reference first spread code P1, a second spread code P2 advanced from the first spread code P1 by a predetermined phase, and the second spread code P2. A third spreading code P3 which is delayed from the one code P1 by a predetermined phase is generated.

Here, the first spreading code generating circuit (3) is
For example, it is a well-known circuit that includes a shift register and an exclusive OR gate, and generates an M-sequence code according to an output signal of a VCO (10) that is a clock signal. Further, the second spreading code generating circuit (15), for example, uses the spreading code P0 of the first spreading code generating circuit (3).
Is used as data, and the output signal of the VCO (10) is used as a clock signal. The spread code P0 is sequentially transmitted to the shift registers of the first to third stages. The output signal of the second-stage shift register is set to the first spreading code P1, and the VCO (1
0) of the output signal, the second spreading code P2 advanced by one clock from the first spreading code from the first-stage shift register, and the third spreading code P3 delayed by one clock from the third-stage shift register. It will be generated.

Further, the spread signal from the second spread signal generating circuit (15) is applied to the first multiplier (2). Therefore, the generation timing of the spread code generated from the first spread code generation circuit (3) changes in accordance with the change in the oscillation frequency of the VCO (5), and therefore the PLL includes the first multiplier (2).
Of the VCO (10) and the output signal of the VCO (10) are synchronized in phase. Therefore, the widely known PL
By using the method of L, it is possible to maintain the synchronization between the output signal of the first multiplier (2) and the output signal of the VCO (10).

By the way, the synchronization acquisition must be performed before the synchronization is held, and the operation during the synchronization acquisition will be described here. Since the first selection circuit (12) selects the DC voltage source (11), a predetermined oscillation frequency signal is generated from the VCO (10), and the PLL is synchronously captured. The predetermined oscillation frequency is set so as to have a desired lock frequency. Then, when the output signal of the first multiplier (2) becomes equal to or higher than a predetermined level in the synchronization acquisition circuit (13),
When it is detected that the synchronization of the PLL has been captured, the first selection circuit (1) is output according to the output signal of the capture detection circuit (13).
2) selects the output signal of the LPF (6). Therefore, the oscillation frequency of the VCO (10) is changed so that the phase difference between the two input signals of the phase comparison circuit (4) becomes 0,
The output oscillation frequency of (10) becomes the lock frequency of the PLL.

On the other hand, the control circuit (18) is connected to the VCO (10).
Output signal is applied, the first control signal is applied from the control circuit (18) to the second selection circuit (16) according to the output signal of the VCO (10), and the second selection circuit (16) performs a selection operation. . Further, the correlation between the received spread spectrum signal and the spread code is detected by the correlation detection circuit (17). The control circuit (18) determines whether the phase of the spread code is behind or ahead of the phase of the spread spectrum signal according to the detected correlation output, and the second control signal outputs the control circuit ( 18) occurs. Then, the output generation timing of the frequency dividing circuit (14) is varied according to the second control signal. That is, when it is determined that the phase of the spread code is behind the phase of the spread spectrum signal according to the comparison result, the output generation timing of the frequency dividing circuit (14) is advanced by the second control signal, and as a result,
The phase of the spreading code advances. Conversely, if it is determined that the phase of the spread code is ahead of the phase of the spread spectrum signal, the output generation timing of the frequency dividing circuit (14) is delayed, so that the phase of the spread code is delayed.

Therefore, by the above operation, the spread code synchronized with the spread code in the spread spectrum signal is generated,
Accurate despreading is performed by multiplying the spread spectrum signal and the spread code by the first multiplier (2). The output signal of the first multiplier (2) is the BPF.
An information signal can be obtained by applying to the demodulation circuit (9) via (8) and demodulating the output signal.

FIG. 3 shows a concrete example of the configuration of the control circuit (18) shown in FIG. 1. (19) is a frequency dividing circuit for dividing the output signal of the VCO (10) by n, and (20) is a frequency dividing circuit. A timing circuit for generating a timing signal according to the output signal of (19), (21) a BPF for limiting the output signal of the multiplier (2) to a predetermined band, and (22) a level detection.
An envelope detection circuit that performs envelope detection of the output signal of (21),
(23) is a smoothing circuit for smoothing the output signal of the envelope detection circuit (22), (24) is a first switch for distributing the output signal of the smoothing circuit (23) to capacitors C1, C2 and C3, ( 25) is a second switch, (26) is a first comparator that compares the output levels of the capacitors C1 and C2, (27) is a second comparator that compares the output levels of the capacitors C1 and C3, and (28) is a second comparator. A determination circuit that determines the output signals of the first and second comparators (26) and (27), and (29) is a second control signal that controls the output generation timing of the frequency dividing circuit (14). It is a control signal generation circuit. However, the frequency division number n is sufficiently larger than the frequency division number m, and the selection cycle of the second selection circuit (16) is at least one cycle of the spreading code (one cycle: time corresponding to one pattern of the spreading code) or more. To be set.

In FIG. 3, the frequency dividing circuit (19) is a VCO.
The output signal of (10) is divided by n to generate a clock divided by n. The clock is applied to a timing circuit (20) and the timing signals a to d are applied according to the clock.
From the timing circuit (20). First, according to the timing signals a to c, the second selection circuit (16) selects the first switch (2) so as to select the first spread code P1.
4) is designed so that the second switch (25) is turned off so that its movable terminal is connected to the capacitor C1. In this state, the multiplier (2) multiplies the first spread code P1 by the spread spectrum signal, and then the BPF (21).
The output signal of the multiplier (2) is limited to a predetermined band. The output signal of the BPF (21) is the envelope detection circuit (2
It is detected in 2). Here, the envelope detection output signal is a signal indicating the correlation between the spread spectrum signal and the spread code, and becomes high output when synchronized as shown in FIG.
This is a triangular wave signal that becomes 0 level if it is shifted by more than one chip (one chip: the time corresponding to one bit of the spread code). Then, the envelope detection output signal is output to the smoothing circuit (2
Smoothed in 4). The output signal of the smoothing circuit (24) is held in the capacitor C1 via the first switch (24).

Next, the second selection circuit (16) selects the second spread code P2 according to the timing signals a and b, and the first selection circuit (16) selects the first spread code P2.
The movable terminal of the switch (24) is connected to the condenser C2 side. Therefore, a correlation output between the second spread code P2 and the spread spectrum signal is obtained at the output end of the smoothing circuit (23), and the correlation output is held in the capacitor C2 via the first switch (24).

Further, according to the timing signals a and b,
The second selection circuit (16) selects the third spreading code P3, and the movable terminal of the first switch (24) is connected to the capacitor C3 side. Therefore, the third end is provided at the output end of the smoothing circuit (23).
A correlation output between the spread code P3 and the spread spectrum signal is obtained, and the correlation output is held in the capacitor C3 via the first switch (24).

After that, the second selection circuit (16) selects the first spreading code according to the timing signals a to c, the movable terminal of the first switch (24) is connected to the terminal (24 '), The 2 switch (25) is turned on. Therefore, the first comparator (26) includes capacitors C1 and C1.
The second comparator (27) compares the output levels of the capacitors C1 and C2. Therefore, the first and second spreading codes P1 are generated by the first comparator (26).
, P2 and the spread spectrum signal are compared with each other, and the second comparator (27) compares the correlation outputs of the first and third spread codes P1 and P2 with the spread spectrum signal. Then, the first and second comparators (26) and (27)
Generates an "H" level output signal when the output level of the capacitor C2 or C3 is higher than the output level of the capacitor C1. The "H" level output signal of the first comparator (26) or the second comparator (27) is applied to the decision circuit (28), and the phase of the first spread code P1 leads the phase of the spread spectrum signal. It is determined whether or not it is late. Then, according to the determination result, the determination circuit (2
8) generate output signals e, f, and g, and at the time of generation of the timing signal d, a second control signal, which is a lead or delay according to the output signals e and f, is output from the second control signal generation circuit
It occurs from 9).

Here, when the first spread code P1 is behind the spread spectrum code, the first to third spread codes P1.
To P3 and the spread outputs of the spread spectrum signal are a, b and a in FIG. 4, respectively. Therefore, the first comparator (2
An output signal of "H" level is generated from 6), and an output signal e is further generated from the determination circuit (28). Then, according to the output signal e, the second control signal is generated, and the output generation timing of the frequency dividing circuit (14) is advanced. Therefore, the correlation outputs of the first to third spreading codes P1 to P3 and the spread spectrum signal are C, D and A in FIG. 4, respectively.

On the other hand, when the first spread code P1 is ahead of the spread spectrum code, the correlation outputs of the first to third spread codes P1 to P3 and the spread spectrum signal are as shown in FIG. Become. Therefore, the second comparator (26)
Causes an output signal of "H" level to be generated, and an output signal f is further generated from the determination circuit (28). Then, a delayed second control signal is generated according to the output signal f, and the frequency dividing circuit (1
The output generation timing of 4) is delayed. Therefore, the correlation outputs of the first to third spreading codes and the spread spectrum signal are O, K and D in FIG. 4, respectively.

By repeating such operations, the spread code and the spread spectrum signal are synchronized. When synchronized, the correlation outputs of the first to third spreading codes P1 to P3 and the spread spectrum signal are respectively shown in FIG.
Oh and u. Therefore, the first comparator (26) and the second comparator
Since the "H" level output signal is not generated from the comparator (27), the determination circuit (28) generates the output signal g. According to the output signal g, the second control signal generating circuit (29)
Stop the generation of control signals. The timing circuit (20) to which the output signal g is applied generates predetermined timing signals a to c, and the first selection circuit (16) selects the first spread code P1. 24), the movable terminal of which is connected to the terminal on the side of the capacitor C1, and the second switch (25) is fixed to be in the ON state, so that the state where the spread code and the spread spectrum signal are synchronized is maintained.

Further, in such a synchronization maintaining state, the first comparator (26) outputs the correlation output of the first spread code P1 and the spread spectrum signal and the correlation output of FIG. The second comparator (27) constantly compares the correlation output of the first spread code P1 and the spread spectrum signal with the correlation output of E of FIG. 4 held in the capacitor C2. When the spread code and the spread spectrum signal are out of synchronization, the first comparator (26), or
The "H" level output signal is generated from the second comparator (27), and the determination circuit (28) stops generating the output signal g.
Therefore, the operation state for synchronizing the spread code and the spread spectrum signal is restarted.

In FIG. 3, the output signal of the BPF (21) may be applied to the demodulation circuit (9), in which case the BPF (8) can be eliminated.
Also, in FIG. 3, the output level of the envelope detection circuit (22) changes slightly. Therefore, the minimum value detection circuit is connected instead of the smoothing circuit (23) in FIG. 3, the minimum value of the correlation output between the spread code and the spread spectrum signal is held, and the phases are controlled by comparing them with each other. You can go.

FIG. 5 shows an example of a configuration in which a memory is used instead of the capacitor as the holding circuit in the circuit of FIG. In FIG. 5, an A / D conversion circuit (30) digitally converts the output signal of the smoothing circuit (23). Memory (3
1) stores and holds the digital data of the A / D conversion circuit (30), and stores the digital data in the memories 1, 2 and 3 in the memory (31) according to the timing signal from the timing circuit (20). Digital data of correlation outputs of the three spread codes P1 to P3 and the spread spectrum code are stored and held, respectively. The determination circuit (32) is the determination circuit (28)
It has the same function as the above, and compares the output data of the memory (31) to determine whether the spread code is ahead of or behind the spread spectrum signal. Further, although an example in which a capacitor, an A / D conversion circuit and a memory are used as the holding circuit has been shown, other means may be used for the holding circuit without being limited to this.

Next, the operation of the frequency dividing circuit (14) will be described with reference to the timing chart of FIG. Frequency divider (1
4) is composed of, for example, m-stage rising detection flip-flops, and the first-stage flip-flops are cleared or preset according to the second control signal of the control circuit (18). A VCO as shown in Fig. 6 (a) which becomes a clock
When the output signal of (10) is applied to the frequency dividing circuit (14), the signal obtained by dividing the output signal of the VCO (10) by 2 is obtained as shown in FIG.
The solid lines of (b) and (f) are shown, and the signal of the frequency division by 4 is as shown by the solid lines of (c) and (g) of FIG. The output signal of
It becomes like the solid line of (d) and (h).

Here, of the second control signals, when the advancing second control signal as shown in FIG. 6 (e) is applied to the frequency dividing circuit (14), the first-stage flip-flop is cleared, and FIG. 6 (b).
As described above, the frequency-divided signal changes from "H" level to "L" level. Therefore, the signal of the second frequency division becomes the dotted line of FIG. 6B, and the signal of the fourth frequency division becomes the dotted line of FIG. 6C. As a result, the output signal of the frequency dividing circuit (14) becomes as shown by the dotted line in FIG. 6 (d), and the output generation timing of the frequency dividing circuit (14) is advanced as compared with the solid line in FIG. 6 (d).

When the delayed second control signal as shown in FIG. 6 (i) is applied to the frequency dividing circuit (14), the first-stage flip-flop is preset and responds to the rising of the clock as shown in FIG. 6 (f). Without doing so, the signal divided by two maintains the “H” level. Therefore, the signal of the subsequent frequency division by 2 is shown in Fig. 6 (f).
It becomes like the dotted line of, and the signal of frequency division by 4 is shown in Fig. 6 (g).
It becomes like the dotted line. As a result, the output signal of the frequency dividing circuit (14) becomes as shown by the dotted line in FIG. 6 (h), and the output generation timing of the frequency dividing circuit (14) is delayed as compared with the solid line in FIG. 6 (h).

[0035]

As described above, according to the present invention, the correlation output between the spread code and the spread spectrum signal is detected, and the spread code and the spread spectrum signal are synchronized according to the detection result. Therefore, the spreading codes on the transmitting side and the receiving side are synchronized, and accurate spectrum despreading can be performed.

Further, in the process of generating the input signal of the spread code generating circuit, the generation timing of the input signal is adjusted to adjust the phase of the spread code, so that temperature change, power supply voltage change, time change, VCO change. It is possible to always carry out accurate spectrum despreading regardless of variations in the free-running frequency and without limiting the adjustment range.
Also, if the phase of the spreading code is adjusted in a unit that is sufficiently smaller than the chip period of the spreading code, synchronization can be achieved with high accuracy.

Furthermore, since the correlation between the spread code and the spread spectrum signal is detected and held by time division, the circuit can be simplified. Furthermore, since the number of means for despreading the spectrum is one, it is possible to prevent erroneous determination due to offset of the elements due to variations in the elements and gain ratios that occur when a plurality of despreading means are used, and to simplify the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a block diagram showing a main part of the present invention.

FIG. 4 is a waveform diagram for explaining the present invention.

FIG. 5 is a block diagram showing another main part of the present invention.

FIG. 6 is a timing chart for explaining an essential part of the present invention.

[Explanation of symbols]

 10 VCO 14 Frequency Dividing Circuit 15 Second Spreading Code Generating Circuit 16 Second Selecting Circuit 17 Correlation Detection Circuit 18 Control Circuit 19 Frequency Dividing Circuit 20 Timing Circuit 21 BPF 22 Envelope Detection Circuit 23 Smoothing Circuit 24 First Switch 25 Second Switch 26 1st comparator 27 2nd comparator 28 Judgment circuit 29 2nd control signal generation circuit 30 A / D conversion circuit 31 Memory 32 Judgment circuit

Claims (10)

[Claims] 1. A spread spectrum receiver for receiving a spread spectrum signal, comprising a despreading circuit for despreading the spread spectrum signal, and a phase for generating an output signal synchronized with the phase of the output signal of the despreading circuit. A synchronizing circuit, a clock signal generating circuit for generating a clock signal for a spread code according to an output signal of the phase synchronizing circuit, and a spreader for generating a plurality of spreading codes according to an output signal of the clock signal generating circuit. A code generation circuit, a correlation detection circuit for detecting a correlation between the spread spectrum signal and the plurality of spread codes according to an output signal of the despreading circuit, and the clock according to an output signal of the correlation detection circuit. A spread spectrum receiver, comprising: a control circuit that generates a control signal for controlling an output phase of the signal generation circuit. 2. The spreading code generation circuit, according to an output signal of the clock signal generation circuit, a first spreading code, a second spreading code advanced from the first spreading code by a predetermined phase, and a first spreading code. The spread spectrum receiver according to claim 1, wherein the third spread code delayed by a predetermined phase is generated. 3. The correlation detection circuit comprises a level detection circuit for detecting the level of the output signal of the first despreading circuit, and a holding circuit for holding the output signal of the level detection circuit. The spread spectrum receiver according to claim 1. 4. The spread spectrum receiving apparatus according to claim 3, wherein the holding circuit comprises a capacitor for holding the output signal of the level detection circuit. 5. The spreading code generation circuit, according to an output signal of the clock signal generation circuit, a first spreading code, a second spreading code advanced from the first spreading code by a predetermined phase, and a first spreading code. A third spreading code delayed by a predetermined phase is generated, the holding circuit includes first to third holding circuits, and the first holding circuit is a level detection circuit corresponding to the first spreading code. An output signal is held, the second holding circuit holds an output signal of the level detection circuit according to the second spreading code, and the third holding circuit detects the level according to the third spreading code. 4. The spread spectrum receiver according to claim 3, which holds an output signal of the circuit. 6. The spread spectrum signal receiving apparatus according to claim 3, wherein the level detection circuit detects a minimum value of an output signal level of the first despreading circuit. 7. The holding circuit is an A / D for digitally converting an output signal of the level detection circuit.
The spread spectrum receiver according to claim 3, comprising a D conversion circuit and a memory for storing output data of the A / D conversion circuit. 8. The control circuit includes a comparison circuit and a control signal generation circuit, wherein the comparison circuit detects a changing direction of a correlation output according to an output signal of the correlation detection circuit, The spread spectrum receiving apparatus according to claim 1, wherein the generating circuit generates a lead or lag control signal according to the output signal of the comparison circuit. 9. The spreading code generating circuit is configured to respond to an output signal of the clock signal generating circuit, a first spreading code, a second spreading code advanced from the first spreading code by a predetermined phase, and a first spreading code. A third spreading code delayed by a predetermined phase is generated, and the holding circuit stores the output signal of the level detection circuit according to the first spreading code in the first holding circuit and the second spreading code. The second holding circuit for holding the output signal of the corresponding level detection circuit, and the third holding circuit for holding the output signal of the level detection circuit according to the third spreading code. A first comparator for comparing the output signals of the first and second holding circuits, a second comparator for comparing the output signals of the first and third holding circuits, and a first comparator for comparing the output signals of the first and second holding circuits. Determine the direction of the correlation output according to the output signal It consists of a determination circuit for spread spectrum receiver according to claim 8, wherein. 10. The output signal of the second holding circuit is the first signal.
A lead control signal is generated when it is larger than the output signal of the holding circuit, and a delay control signal is generated when the output signal of the third holding circuit is larger than the output signal of the first holding circuit. 10. The spread spectrum receiver according to claim 9.