JP3251464B2 - Clock recovery circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit, and more particularly to a clock recovery circuit using a direct spread passive correlator.

[0002]

2. Description of the Related Art In conventional data communication, communication using a narrow band modulation method is generally used. These can realize demodulation in a receiver with a relatively small circuit, but have a drawback that they are vulnerable to multipath and narrow-band colored noise as in a room (office or factory).

On the other hand, the spread spectrum communication system is
Since the spectrum of the data is spread by the spread code and transmitted in a wide band, not all the bands are destroyed by the noise, so that there is an advantage that these disadvantages can be solved.

In such a system, since the transmitter and the receiver operate on different clocks, the receiver needs a clock recovery circuit having the same phase as that of the transmitter.

FIG. 8 shows a configuration of a clock recovery circuit in such a conventional spread spectrum communication. In the figure, 102 is a gate, 103 is a filter, 104 is PL
L (Phase Locked Loop), 105 is VCO (Volt Control)
lled Oscilator) 108 is a phase shifter.

[0006] The correlation output obtained by the demodulator (not shown) is compared with a set threshold value and passed through a gate 102.
Thereafter, the clock frequency component is extracted using the filter 103. In order to generate a stable clock using this component as a reference, a VCO
The control voltage is generated by comparing the
5 is controlled to generate a clock.

[0007] The phase shifter 108 is used to match the synchronization timing 107. By doing so, the VCO 105 can generate a reception clock synchronized with the transmission clock.

[0008]

However, in such a clock recovery circuit, an analog filter 10 is required.
(3) Since the VCO 105 and the like are required, and it is difficult to integrate the analog circuit, there is a disadvantage that the circuit scale becomes large.

[0009] In addition, a digital / analog mixed circuit is:
There is a problem of interference at the time of substrate production, and there is a problem that know-how is required for design, assembly, and shielding, and adjustment is required for mass production. Digital NCO (Num
An arrangement using an eric controlled oscillator (OS), a digital filter, and the like has also been proposed. However, in this case, NC
O: To construct a digital filter, a considerable amount of numerical calculation is required, so that the circuit scale becomes large, and it is not suitable for high-speed operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a clock recovery circuit for spread spectrum communication which can be realized by a digital circuit and can be realized by a relatively simple circuit.

[0011]

In order to achieve the above object, a clock recovery circuit for spread spectrum communication according to the present invention divides a sampling clock used for data demodulation by using a spread spectrum synchronization pulse as a start signal. In a clock recovery circuit in spread spectrum communication for generating a clock, a plurality of frequency dividers whose frequency division ratios are changed by 1 by means of frequency division of the sampling clock, and the correlation timing is obtained from a correlation signal. An early / late control signal forming circuit for determining whether the pulse is early or late and generating an early / late control signal; and selecting outputs of the plurality of frequency dividers based on the early / late control signal and outputting as a reproduction clock. And a circuit for forming the early / late control signal.
Multiple correlation signals for each input of intermittently input sync pulse
A delay circuit for sampling at a sampling point of
By comparing the output for each sampling point with a common threshold
A plurality of comparators that output binary signals, and the output of each comparator
A weighting circuit for weighting the force;
An addition circuit for cumulatively adding the output of the path for each correlation signal,
It is characterized by comprising .

The present invention also provides a clock recovery circuit in spread spectrum communication for generating a clock by dividing a sampling clock used for data demodulation by using a spread spectrum synchronization pulse as a start signal, wherein the frequency of the sampling clock is divided. The division ratio is set to 1
A plurality of frequency dividers each of which has been changed at a time, an early / late control signal forming circuit which determines whether a correlation timing is earlier or later than the synchronization pulse from a correlation signal and generates an early / late control signal, and the plurality of frequency dividers It includes a circuit for outputting a selected reproduction clock based on the output of vessels in the early late control signal, wherein the early late
The control signal forming circuit is used to generate the intermittently input synchronization pulse.
The correlation signal is sampled at multiple sampling points for each input.
The delay circuit to be ringed and the output of each delay circuit are weighted.
A weighting circuit for performing weighting, and an output of each of the weighting circuits.
And an adder circuit for accumulative addition for each correlation signal .

[0013]

[0014]

[0015]

[0016]

[0017]

According to the first aspect of the present invention, there is provided a clock recovery circuit in spread spectrum communication for generating a clock by dividing a sampling clock used for data demodulation using a spread spectrum synchronization pulse as a start signal. A plurality of frequency dividers whose frequency division ratios are changed by one by means of clock division and a correlation signal are used to determine whether the correlation timing is earlier or later than the synchronization pulse, and to generate an early / late control signal. A circuit for generating an early / late control signal, and a circuit for selecting an output of the plurality of frequency dividers based on the early / late control signal and outputting the selected output as a reproduction clock ;
And the early / late control signal forming circuit is intermittently input.
For each sync pulse input, the correlation signal is
A delay circuit for sampling at the sampling point;
The output of each bin is compared with a common threshold to generate a binary signal.
Weighted comparators and the output of each comparator
A weighting circuit for performing
And an addition circuit that performs cumulative addition for each correlation signal.
It can be realized by a digital circuit and can be realized by a relatively simple circuit.

According to the second aspect of the present invention, the spectrum spread is the same.
Using the initial pulse as a start signal for data demodulation
Specified for generating clock by dividing clock for pulling
In clock recovery circuits in vector spread communication,
Divide the sampling clock by means of frequency division
Correlation from correlation signals with multiple frequency dividers with ratio changed by 1
Determine whether the timing is earlier or later than the sync pulse
An early / late control signal forming circuit for generating an early / late control signal;
Output of the plurality of frequency dividers based on the early / late control signal
A circuit for selecting and outputting as a reproduction clock.
The early / late control signal forming circuit is provided with an intermittently input synchronous signal.
The correlation signal at multiple sampling points for each input
The sampling delay circuit and the output of each delay circuit
A weighting circuit for performing weighting;
An adder circuit for accumulating the output for each correlation signal.
Therefore, it can be realized by a digital circuit and can be realized by a relatively simple circuit.

[0019]

[0020]

[0021]

[0022]

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a clock recovery circuit for spread spectrum communication according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of the configuration of the clock recovery circuit according to the first embodiment of the present invention. In the figure, 1 is a synchronous pulse generating circuit, 2 is 2 × k−1
Frequency divider, 3 is a 2 × k frequency divider, 4 is a 2 × k + 1 frequency divider, 5
Is an early / late control signal forming circuit, and 6 is a selector.

The synchronization pulse is supplied from a synchronization pulse generation circuit in the spread spectrum section to a 2 × k−1 frequency divider 2, 2 × k
The signal is distributed to the frequency divider 3 and the 2 × k + 1 frequency divider 4. Here, these 2 × k−1 frequency dividers 2, 2 × k frequency dividers 3 and 2 × k + 1 frequency dividers 4 divide the frequency of the sampling clock, but the output is synchronized with the start point by the synchronization pulse. Since the frequency division ratio is different, the next rise is 2 ×
In the (k-1) frequency divider 2, the frequency is early, and in the (2 × k + 1) frequency divider 4, the frequency is low.

The outputs of these 2 × k−1 frequency dividers 2, 2 × k frequency dividers 3 and 2 × k + 1 frequency dividers 4 are switched by selector 6 in accordance with the output of early / late control signal forming circuit 5. The early / late control signal forming circuit 5 is controlled by a correlation signal.

[0026] Figure 9, the configuration of the clock recovery circuit according to a first embodiment of the present invention was more generalized, a block diagram illustrating another example. In the figure, a synchronization pulse generating circuit 1 and an early / late control signal forming circuit 5 are the same as those in FIG. 1, and a detailed description thereof will be omitted. 7 is a frequency division number determining circuit, and 8 is a frequency divider. The output of the early / late control signal forming circuit 5 is multi-valued information generated in the frequency dividing number determining circuit 7 and sent to the frequency dividing number determining circuit 7 to control the frequency dividing ratio in the frequency divider 8 to generate the reproduced clock. Output. As this method, R
A numerical value corresponding to the output of the early / late control signal forming circuit 5 may be stored in the frequency division number determining circuit 7 in the OM table.

The configuration of the early / late control signal forming circuit 5 for controlling the selector 6 and the frequency division number determining circuit is as shown in FIG. In the figure, 11 is a window control unit, 12 to 16 are delay units, 13 is a threshold input terminal, 17
21 to 21 are comparators, 22 to 26 are adders, and 27 is a clock reproducing unit. Among these, the window control unit 11,
Delay devices 12 to 16, threshold input terminal 13, comparator 17 to
21, adders 22 to 26 constitute the early / late control signal forming circuit in FIG.

A correlation signal obtained from a demodulator (not shown) is processed by a delay unit (for example, a shift register) 12 for processing.
By 16, it is spread on the time axis. This signal is shown in FIG.
(A) and (b), and it is assumed that quantization is performed on two samples per chip.

The synchronization pulse is input intermittently and is repeated at regular intervals. The reproduction clock is synchronized with the cycle. Window control unit 11
Accumulates such intermittent inputs in the delay units 12 to 16 only in the portion having this correlation peak.

The outputs of the delay units 12 to 16 are respectively input to comparators 17 to 21 and compared with threshold values given from a threshold input terminal 13, and the result is obtained at five points as shown in FIG. If the center portion exceeds the threshold value, the logic "1" is output from the comparator 19 as shown in the figure, and if it is late, the logic "1" is output as shown in FIG. Output from the comparator 20. Conversely, if earlier, although not shown, for example, the comparator 17 outputs a logic “1”.

The outputs of the comparators 17 to 21 are supplied to an adder 2
Cumulative addition is performed in each of 2 to 26, and the location where the overflow has occurred is specified, and the frequency dividing circuit having the switching means is switched. This situation is shown in FIGS. In FIG. 4A, when the timing of the reproduced clock is correct, the output c of the comparator 19 takes a logic 1, and if the adder 24 overflows, the selector 6
Selects the 2 × k frequency divider 3 and outputs a reproduced clock as shown in the figure. Note that the value of the full adder is reset by the signal that overflows first in the adders 22 to 26, and 0
Becomes

If the correlation signal is slow, FIG.
For example, when the output of the comparator 20 becomes logic "1" and the adder 25 overflows, the selector 6 selects the 2 × k-1 frequency divider 2, and at the next rising edge as shown in FIG. Advance the playback clock. Conversely, as shown in FIG. 4C, for example, when the comparator 18 becomes logic "1" and the adder 23 overflows, the timing of the reproduced clock is delayed at the next rising edge as shown. Note that the early / late control signal is not output unless the adder overflows, but when it does not come, the normal sampling clock is divided by 2 × k.

The ideal correlation signal is as shown in FIG. 3A, and only the comparator 19 exceeds the threshold value. As a result, only the adder 24 counts up by one. The actual correlation signal may be deformed due to noise components, but when the timing is correct, the addition amount of the adder 24 is the largest on average and overflows quickly. As a result,
The clock reproducing unit 27 determines that this timing is correct, and maintains the timing.

On the other hand, if the timing is not correct,
As shown in FIG. 3B, only the adder 25 counts up by one when the threshold value is exceeded. In this case as well, the form of the correlation signal may be distorted due to the noise component, but the adder 25 has the largest amount of addition on average and overflows quickly. In this case, the clock reproducing unit 27 determines that the clock timing is late, and advances the clock timing by one sample, so that the clock timing becomes the correct clock timing.

As described above, in the present embodiment, the clock timing is properly controlled so that the clock can be reproduced at the center of the correlation. For example, 100H between sending and receiving
If it is determined that there is a z shift, an operation of advancing every 1/2 × k × 100 seconds is performed.

As described above, according to this embodiment, the data recovery
Since the clock is reproduced digitally using the sampling timing used for the tone , the circuit becomes all digital as compared with the conventional case where analog and digital are mixed, and the size can be reduced by using an IC. In addition to being unadjusted, it is also suitable for board design and mass production. Further, the circuit scale can be smaller than the configuration using the NCO and the digital filter.

Although the time window is set to 5 sample clocks in this embodiment, the size (number of samples) of the time window may be changed depending on the system design, such as 3 samples or 7 samples. Also, the case where the adder overflows has been described, but the case where the value exceeds a predetermined threshold may be used.

In the case where the adder 24 for the center timing of the window overflows first in the clock recovery unit 27, the clock recovery unit 27 maintains the current timing, while the adders 22 and 23 of the earlier timings maintain the current timing. When the overflow occurs, the timing is delayed by one. When the adders 25 and 26 at the later timing overflow first, the timing of the clock recovery unit 27 is advanced by one. When the overflow occurs, there is a possibility that the timing of the clock recovery unit 27 is largely shifted as compared with the case where the adder 23 overflows.

Therefore, in this case, the feature of the second embodiment is that the timing is shifted by two samples. As a result, when the clock timing is greatly shifted for some reason, it is possible to quickly recover. In this method, the frequency division is performed by performing 2k + 1, 2k-1 twice for one early / late control signal, or 2k + 2, 2k-
There is a method of preparing a circuit for dividing the frequency by two.

When the time window is set to 7 samples, the outermost adder is shifted by 3 samples, and the second adder is shifted by 2 samples. Also in the embodiment, the generality is maintained even if the size of the time window is changed.

FIG. 5 is a schematic block diagram showing the configuration of the second embodiment of the present invention. In FIG.
Reference numeral 0 denotes a weighting circuit, which includes a window control unit 11, delay units 12 to 16, comparators 17 to 21, adders 22 to 26,
The clock reproducing unit 27 is the same as that of the first embodiment, and the description is omitted.

The signals of logic "0" or "1" output from the comparators 17 to 21 are weighted by weighting circuits 56 to 60, respectively, added by adders 22 to 26, respectively, and the overflow signals are received. The clock reproducing unit 27 controls the clock timing in the same manner as in the first embodiment.

Here, the weighting circuits 56 to 60 increase the weighting from the center of the time window toward the outside. As a result, even if the same number of count-ups is performed, overflow occurs earlier as it is located outside. Therefore, the clock timing is corrected more quickly as the clock timing is greatly shifted to the outside, and the performance can be improved.

Here, the weighting circuits 56 to 60
An example is shown in which weighting is performed from the center of the time window to the outside using the adder 22 and the adder 22 to 26, but the overflow value is changed only by the adder (in the center, the added value is “32”). , But overflow on the outside at "16", etc.), it is also possible to carry out weighting, and it is possible to obtain the same effect as the present embodiment.

In addition, as described in the description of "Note" in the first embodiment, the clock timing to be shifted may be increased as the outside overflows. This makes it possible to establish synchronization even earlier.

FIG. 6 is a schematic block diagram showing the configuration of the clock recovery circuit according to the third embodiment of the present invention. In the figure, a window control unit 11, a delay unit 12
To 16, the adders 22 to 26, and the clock recovery unit 27 are the same as those in the first embodiment, and the detailed description is omitted.

A correlation signal obtained from a demodulator (not shown) is spread on a time axis by delay units 12 to 16.
At this time, it is assumed that sampling is performed with two samples per chip. On the other hand, the window control unit 11 is controlled by the synchronization pulse, and correlation signals for several samples before and after the synchronization pulse are used for clock recovery.

The correlation signals in this window are added by adders 22 to 26 for each sampling, and
Upon receiving the overflow signal, the clock recovery unit 27
Use to control clock recovery. When the adder 24 at the center of the window overflows first, the clock reproducing unit 27 maintains the current clock timing.

On the other hand, if the adder 22 or 23 with an earlier timing overflows, the timing of the clock recovery unit is delayed by one. Conversely, when the adder 25 or 26 with a late timing overflows, the timing of the clock reproducing unit 27 is advanced by one. Thus, the reproduction clock is controlled.

In the first and second embodiments, the threshold value is set, and the logic "0" or "1" is determined based on whether or not the threshold value has been exceeded. Is added.

Since the correlation signal itself is a multi-bit signal as shown in FIG. 3 (a) or (b), if the multi-bit signal is added without bit determination, the result of the addition is substantially correlated. It is possible to have an output similar to the signal within the time window. As a result, even when the form of the correlation signal is broken by the noise component, the correlation signal is averaged and the clock can be reproduced at a more correct timing.

As described in the first embodiment, the clock timing to be shifted may be increased as the outside overflows. This makes it possible to establish synchronization even earlier.

That is, when the adder 24 of the center timing of the window overflows first in the clock recovery unit 27, the clock recovery unit 27 maintains the current timing, while the adders 22 and 23 of the earlier timings When the overflow occurs, the timing is delayed by one. When the adders 25 and 26 at the later timing overflow first, the timing of the clock recovery unit 27 is advanced by one. When the overflow occurs, there is a possibility that the timing of the clock recovery unit 27 is largely shifted as compared with the case where the adder 23 overflows.

Therefore, in this case, the timing is shifted by two samples. As a result, when the clock timing is greatly shifted for some reason, it is possible to quickly recover.

When the time window is set to 7 samples, the outermost adder is shifted by 3 samples, and the second adder is shifted by 2 samples. Also in the embodiment, the generality is maintained even if the size of the time window is changed.

FIG. 7 is a schematic block diagram showing the configuration of the clock recovery circuit according to the fourth embodiment of the present invention. In the figure, a window control unit 11, a delay unit 12
The adders 22 to 26, the clock recovery circuit 27, and the weighting circuits 56 to 60 are the same as those in the second embodiment, and a detailed description thereof will be omitted.

A correlation signal obtained from a demodulator (not shown) is spread on a time axis by delay units (for example, shift registers) 12 to 16. At this time, it is assumed that sampling is performed with two samples per chip, as in the first embodiment.

On the other hand, the window control unit 11 is controlled by the synchronization pulse, and a correlation signal for several samples before and after the synchronization pulse is used for controlling the clock reproduction. The correlation signal in this window is weighted by weighting circuits 56 to 60 for each sampling, added by adders 22 to 26, and receives the overflow signal. I do.

The clock recovery unit 27 maintains the timing of the clock recovery unit 27 when the adder 24 at the center of the window overflows first, and when the adder 22 or 23 at the earlier timing overflows. , The timing of the clock reproducing unit 27 is delayed by one. Conversely, when the adder 25 or 26 at a later timing overflows, the timing of the clock recovery unit 27 is advanced by one. In this way, a reproduction clock having a correct timing is obtained.

In this embodiment, as in the second embodiment, the clock timing is corrected more quickly as the clock timing is greatly shifted outward, and the performance can be improved.

Here, the weighting circuits 56 to 60
In this example, weighting is performed on the outside of the center of the time window by using the adder 22 and the adder 22 to 26. However, as in the second embodiment, the overflow value is changed only by the adder (for example, the center Value overflows at 32, but overflows at 16 on the outside)
Weighting can also be performed, and the same effect as in the present embodiment can be obtained.

In the case where the adder 24 of the window center timing overflows first in the clock reproducing unit 27, the clock reproducing unit 27 maintains the current timing, while the adders 22 and 23 of the earlier timings maintain the current timing. When the overflow occurs, the timing is delayed by one. When the adders 25 and 26 at the later timing overflow first, the timing of the clock recovery unit 27 is advanced by one. When the overflow occurs, there is a possibility that the timing of the clock recovery unit 27 is largely shifted as compared with the case where the adder 23 overflows.

Therefore, in this case, the timing is shifted by two samples. As a result, when the clock timing is greatly shifted for some reason, it is possible to quickly recover.

If the time window is set to 7 samples, the outermost adder is shifted by 3 samples, and the second adder is shifted by 2 samples. Also in the embodiment, the generality is maintained even if the size of the time window is changed.

[0065]

As described above, according to the first aspect of the present invention, there is provided a clock recovery circuit for generating a clock by dividing a sampling clock used for data demodulation using a spread spectrum synchronization pulse as a start signal. And a plurality of frequency dividers whose frequency division ratio is changed by 1 by means for dividing the sampling clock, and a correlation signal whose correlation timing is earlier or later than that of the synchronization pulse. An early / late control signal forming circuit that determines whether or not to generate an early / late control signal, and a circuit that selects an output of the plurality of frequency dividers based on the early / late control signal and outputs the selected output as a reproduction clock , Early / late control signal
The forming circuit is used for every input of the intermittently input synchronization pulse.
The correlation signal is sampled at multiple sampling points.
Delay circuit, and a common threshold for the output of each sampling point.
A plurality of comparators for comparing the values and outputting a binary signal;
Weighting circuit for weighting the output of each comparator of
Cumulatively add the output of each weighting circuit for each correlation signal
Since it consists of an addition circuit, it can be realized by a digital circuit,
In addition, it can be realized by a relatively simple circuit.

[0066]

According to the second aspect, the spectrum spread is the same.
Using the initial pulse as a start signal for data demodulation
Specified for generating clock by dividing clock for pulling
In clock recovery circuits in vector spread communication,
Divide the sampling clock by means of frequency division
Correlation from correlation signals with multiple frequency dividers with ratio changed by 1
Determine whether the timing is earlier or later than the sync pulse
An early / late control signal forming circuit for generating an early / late control signal;
Output of the plurality of frequency dividers based on the early / late control signal
A circuit for selecting and outputting as a reproduction clock.
The early / late control signal forming circuit is provided with an intermittently input synchronous signal.
The correlation signal at multiple sampling points for each input
The sampling delay circuit and the output of each delay circuit
A weighting circuit for performing weighting;
An adder circuit for accumulating the output for each correlation signal.
Therefore, it can be realized by a digital circuit and can be realized by a relatively simple circuit.

[0068]

[0069]

[0070]

[0071]

[Brief description of the drawings]

FIG. 1 is a first block schematic diagram showing a configuration of a clock recovery circuit according to a first embodiment of the present invention.

FIG. 2 is a second block schematic diagram illustrating a configuration of a clock recovery circuit according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a relationship between a correlation signal and a sampling timing in the embodiment.

FIG. 4 is a timing chart showing an operation of a main part in the embodiment.

FIG. 5 is a schematic block diagram showing a configuration of a clock recovery circuit according to a second embodiment of the present invention.

FIG. 6 is a schematic block diagram showing a configuration of a clock recovery circuit according to a third embodiment of the present invention.

FIG. 7 is a schematic block diagram showing a configuration of a clock recovery circuit according to a fourth embodiment of the present invention.

FIG. 8 is a schematic block diagram showing a configuration of a clock recovery circuit in a conventional example of the present invention.

FIG. 9 is a third block schematic diagram showing a configuration of a clock recovery circuit according to the first embodiment of the present invention.

[Description of Signs] 1 Synchronous pulse generating circuit 2 2 × (k−1) frequency divider 3 2 × k frequency divider 4 2 × (k + 1) frequency divider 5 Early / late control signal forming circuit 6 Selector

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 1/69-1/713 H04J 13/00-13/06 H04L 7/00

Claims (2)

(57) [Claims] 1. A clock recovery circuit in spread spectrum communication for generating a clock by dividing a sampling clock used for data demodulation using a synchronization pulse for spread spectrum as a start signal, wherein a means for dividing the frequency of the sampling clock is provided. A plurality of frequency dividers whose frequency division ratios are changed by one, and an early / late control signal forming circuit for determining whether the correlation timing is earlier or later than the synchronization pulse from the correlation signal and generating an early / late control signal And a circuit for selecting the outputs of the plurality of frequency dividers based on the early / late control signal and outputting the selected clock as a reproduction clock, wherein the early / late control signal circuit receives an intermittently input synchronization pulse. The correlation signal is duplicated for each
Delay circuit that samples at a number of sampling points
And comparing the output for each sampling point with a common threshold
A plurality of comparators that output binary signals; a weighting circuit that weights the output of each comparator; and an accumulative addition of the output of each weighting circuit for each correlation signal
Clock recovery circuit, wherein the adder circuit, in that it consists of that. 2. A synchronization pulse for spread spectrum is started.
Sampling clock used for data demodulation as signal
Spread spectrum communication that divides the clock and generates a clock.
A clock recovery circuit that performs frequency division of the sampling clock.
A plurality of dividers having different dividing ratio by 1, with respect to the sync pulse correlation timing from the correlation signal
Early / late control that determines whether it is early or late and generates an early / late control signal
A signal forming circuit, and outputting the plurality of frequency dividers based on the early / late control signal.
A circuit for selecting and outputting as a reproduction clock , wherein the early / late control signal circuit duplicates a correlation signal for each input of an intermittently input synchronization pulse.
Delay circuit that samples at a number of sampling points
And a weighting circuit for weighting the output of each delay circuit
And cumulatively add the outputs of the weighting circuits for each correlation signal.
Clock recovery circuit, wherein the adder circuit, in that it consists of that.