JPS57141154A - Receiver on spectrum spread communication system - Google Patents

Receiver on spectrum spread communication system

Info

Publication number
JPS57141154A
JPS57141154A JP56026388A JP2638881A JPS57141154A JP S57141154 A JPS57141154 A JP S57141154A JP 56026388 A JP56026388 A JP 56026388A JP 2638881 A JP2638881 A JP 2638881A JP S57141154 A JPS57141154 A JP S57141154A
Authority
JP
Japan
Prior art keywords
code
phase
codes
clock generator
tap selector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56026388A
Other languages
Japanese (ja)
Other versions
JPH0239139B2 (en
Inventor
Akira Iga
Yasuhiro Hideshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP56026388A priority Critical patent/JPS57141154A/en
Publication of JPS57141154A publication Critical patent/JPS57141154A/en
Publication of JPH0239139B2 publication Critical patent/JPH0239139B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7085—Synchronisation aspects using a code tracking loop, e.g. a delay-locked loop

Abstract

PURPOSE:To achieve excellent reception even in the presence of a multipath by performing demodulation by PN codes in phase with ones contained in a radio wave having the highest level among input radio waves. CONSTITUTION:A controller 18 controls a clock generator 17 by its output to generate a PH code KW1 which shifts in phase by phi at every time, and also discriminates the maximum peak value of a detection output Vd in respective phases to control a tap selector 22 according to the discrimination result. The tap selector 22 selects three adjacent bits of the (m)-bit PN code outputted by a PN code generator 11 and applies the center bit as a PN code KW2 to a multiplier 10. The remaining bits are applied as PN codes KW3 and KW4 to the multipliers 24a and 24b of a phase detector 23, and their outputs are detected and then synthesized by a synthesizer 27 to be supplied as a signal for fine adjustment to a clock generator 28.
JP56026388A 1981-02-25 1981-02-25 Receiver on spectrum spread communication system Granted JPS57141154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56026388A JPS57141154A (en) 1981-02-25 1981-02-25 Receiver on spectrum spread communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56026388A JPS57141154A (en) 1981-02-25 1981-02-25 Receiver on spectrum spread communication system

Publications (2)

Publication Number Publication Date
JPS57141154A true JPS57141154A (en) 1982-09-01
JPH0239139B2 JPH0239139B2 (en) 1990-09-04

Family

ID=12192145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56026388A Granted JPS57141154A (en) 1981-02-25 1981-02-25 Receiver on spectrum spread communication system

Country Status (1)

Country Link
JP (1) JPS57141154A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6188679B1 (en) 1996-12-13 2001-02-13 Nec Corporation CDMA chip synchronization circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55130249A (en) * 1979-03-30 1980-10-08 Sansui Electric Co Code synchronous system for reception of spectrum diffusion signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55130249A (en) * 1979-03-30 1980-10-08 Sansui Electric Co Code synchronous system for reception of spectrum diffusion signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6188679B1 (en) 1996-12-13 2001-02-13 Nec Corporation CDMA chip synchronization circuit

Also Published As

Publication number Publication date
JPH0239139B2 (en) 1990-09-04

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