JPH06311025A - Up-down counter circuit - Google Patents

Abstract

PURPOSE:To obtain an up-down counter whose count is unchanged by switching the count operation executed by the up-down counter circuit before a switching signal is inputted even when up-count or down-count is switched on the way of count. CONSTITUTION:The up-counter is provided with a control signal generating circuit 60 generating a 1st control signal A and a 2nd control signal B based on a 2nd clock signal CLK2 and a switching signal U/D. Furthermore, 2nd, 3rd gate circuits 81-84 inverting outputs of delay flip-flop circuits D-FF 51-54 of each stage with the 1st control signal A and plural multiplexers 91-94 selecting an output of the flip-flop circuits D-FF 51-54 of each stage based on the 2nd control signal B are provided, then even when up-count and down- count are selected on the way of the count, the accurate up-down counter circuit in which the count is not deviated is obtained. Thus, a means correcting the count or the like is not required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention comprises an LSI or the like,
The present invention relates to an up / down counter circuit widely used in digital measuring instruments, electronic calculators, and the like.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a configuration example of a conventional up counter. The up counter is a hexadecimal up counter that counts (up counts) the number of pulses of the clock signal CLK.
Input terminal TC for output and an output signal S forming a counter value
It has output terminals T1 to T4 for outputting Q1 to SQ4. The up-counters are four stages of delay type flip-flops (hereinafter referred to as D-FFs) 11 to 14 which are connected in cascade.
The D-FFs 11 to 14 of the respective stages, which are configured by, are output terminals sq1 to sq4 of positive phase which output the output signals sq1 to sq4 and output signals sq1 / to s of a phase opposite to the output signals sq1 to sq4.
It has a reverse-phase output terminal Q / for outputting q4 /, a data input terminal D, and a clock signal input clock terminal C, respectively. The output terminals Q of the D-FFs 11 to 14 in each stage are connected to the output terminals T1 to T4, respectively, and the output terminals Q / of the D-FFs 11 to 14 in each stage are
Are connected to the input terminals D of the respective D-FFs 11-14. The input terminal TC is connected to the clock terminal C of the first-stage D-FF 11, and the output terminal Q of the previous-stage D-FF is connected to each clock terminal C of the D-FFs 12 to 14.

Next, the operation of FIG. 2 will be described. The clock signal CLK is input from the clock terminal C of the first-stage D-FF 11, and at the fall of the clock signal CLK, the D-FF 11 outputs the output signal s from the output terminal Q /.
q1 / is latched at the input terminal D and the output signal sq1 is output from the output terminal Q. Similarly, the D-FFs 12 to 14 of the respective stages similarly output signals sq1 of the D-FFs 11 to 13 of the preceding stage.
~ Sq3 is input from the clock terminal C and the output signal sq2
Output ~ sq4. These output signals sq1
To sq4 are output to output terminals T1 to T4 and become output signals SQ1 to SQ4, respectively. D-FF11 ~ of each stage
14 is two input pulses from the clock terminal C.
Output pulses are generated and shifted. As a whole of the up counter, the output signals SQ1, SQ
2, high and low levels of SQ3 and SQ4 are "1" and "0"
The change in the output signals SQ1 to SQ4 corresponds to the hexadecimal notation in which all the output signals SQ1 to SQ4 return to their original states by 16 pulses of the clock signal CLK by counting up the clock signal CLK in a binary system. It becomes the counter value.

FIG. 3 is a circuit diagram showing a configuration example of a conventional down counter. The down counter is a hexadecimal down counter that subtracts (down counts) the number of pulses of the clock signal CLK and returns to the original state with 16 pulses. The down counter is an input terminal TC for the clock signal CLK and a counter value. And output terminals T1 to T4 for outputting output signals SQ1 to SQ4. Similar to FIG. 2, FIG. 3 is composed of four stages of D-FFs 21 to 24 connected in cascade, and the D-FFs 21 to 24 of each stage output signals sq1 to sq1.
A positive-phase output terminal Q that outputs sq4 and an output signal sq1
It has an output terminal Q / of a reverse phase for outputting output signals sq1 / to sq4 / of a phase opposite to that of sq4, a data input terminal D, and a clock terminal C for clock signal input. The output terminals Q of the D-FFs 21 to 24 of each stage are connected to the output terminals T1 to T4 and the D-FF2 of each stage is connected.
The output terminals Q / of 1 to 24 are connected to the respective input terminals D of the D-FFs 21 to 24. The input terminal TC is connected to the clock terminal C of the first-stage D-FF 21, and unlike FIG. 2, each clock terminal C of the D-FFs 22 to 24 has a reverse-phase output terminal Q / of the preceding D-FF. Are connected.

Next, the operation of FIG. 3 will be described. The clock signal CLK is input from the clock terminal C of the first-stage D-FF 21, and the D-FF 21 outputs the output signal s from its output terminal Q / at the falling edge of the clock signal CLK.
q1 / is latched at the input terminal D and the output signal sq1 is output from the output terminal Q. Different from FIG. 2, each D-FF 22 to 24 inputs the output signal sq1 / to sq3 / from the anti-phase output terminal Q / of the preceding D-FF 21 to 23 from the clock terminal C and outputs the output signal sq1 to sq4. Are output respectively. These output signals sq1 to sq4 are output to the output terminal T
1 to T4 and output signals SQ1 to SQ4, respectively.
Becomes Therefore, the output signals SQ1, SQ2, SQ3,
The change in SQ4 becomes a hexadecimal counter value that down-counts the clock signal CLK by the binary system.

FIG. 4 is a diagram showing a configuration example of a conventional hexadecimal up / down counter circuit. In the up-down counter circuit of FIG. 4, the up-counter and the down-counter of FIGS. 2 and 3 are combined, and up-counting or down-counting can be switched by the switching signal U / D. This up / down counter circuit is shown in FIGS.
Similarly, it has an input terminal TC for the clock signal CLK and output terminals T1 to T4 for outputting the output signals SQ1 to SQ4 constituting the counter value. This counter circuit further has a switching signal U for switching the counting operation. It has an input terminal TS of / D. This counter circuit has four stages of D-
Based on the FFs 31 to 34 and the switching signal U / D, the preceding D
-Select either one of the output signals from the output terminals Q of the FFs 31 to 33 or the output terminal Q / to select the DF of the next stage.
It has multiplexers 35 to 37 for outputting to F32 to 34. Further, this counter circuit has an input terminal TS.
Connected to the switching signal U / D having a phase opposite to that of the switching signal U / D
It has an inverter 38 that outputs / DN. The output signals sq1 to sq of the D-FFs 31 to 34 at the respective stages are output.
Positive-phase output terminal Q for outputting 4 and output signals sq1 to sq1
It has a reverse-phase output terminal Q / for outputting output signals sq1 / -sq4 / having a phase opposite to q4, a data input terminal D, and a clock signal input clock terminal C, respectively.
Each of the multiplexers 35 to 37 is composed of two 2-input AND gates and one 2-input OR gate.
The input terminal TS of the switching signal U / D and the output terminal of the inverter 38 are connected to one input terminal of the D gate, respectively. The output terminals of the two AND gates are connected to the input terminals of the OR gate, and the output terminal of the OR gate is the output terminal of the multiplexer. First stage DF
The clock terminal C of F31 is connected to the input terminal TC, and the positive-phase output terminals Q of the D-FFs 31 to 34 are output terminals T1 to T1.
It is connected to T4 and the negative-phase output terminal Q /
-It is connected to the data input terminal D of FF31-34. Output terminal Q of the first stage D-FF31, and output terminal Q
/ Is connected to the other input terminal of each AND gate of the multiplexer 35, and the output terminal of the multiplexer 35 is connected to the clock terminal of the D-FF 32 at the next stage. Similarly, in the D-FFs 32 and 33, the output terminal Q and the output terminal Q / are connected to the D of the next stage via the multiplexers 36 and 37.
It is connected to each lock terminal C of -FF33 and 34.

Next, the operation of the up / down counter circuit will be described. When the signal level of the switching signal U / D is on the high level side, each of the multiplexers 35 to 37 in FIG.
Are output signals sq1 to sq of the D-FFs 31 to 33 in the previous stage.
3 is output to the D-FFs 32 to 34 in the next stage, the up / down counter circuit operates as the up counter in FIG. When the signal level of the reverse phase switching signal U / DN is on the high level side, each of the multiplexers 35 to 35 shown in FIG.
37 is an output signal sq1 / of the D-FFs 31 to 33 in the preceding stage.
Since up to sq3 / is output to the D-FFs 32 to 34 in the next stage, the up / down counter circuit operates as the down counter in FIG.

[0008]

However, in the conventional up-down counter circuit as shown in FIG. 4, a switching signal is generated during the up-counting operation or the down-counting operation for the pulse of the clock signal CLK. If the operation is switched by U / D, D
-The levels of the signals input to the clock terminals C of the FFs 32 to 34 are inverted, and accordingly, the respective D-FFs 32 to
The output of 34 is also inverted. Therefore, there is a problem that the output signals SQ1 to SQ4 change and the counter value before switching and the counter value after switching differ. In order to solve this problem, the following up-down counter circuit of a method different from that of FIG. 4 can be considered.
That is, the output signals input to the clock terminals C of the D-FFs 32 to 34 are not switched by the switching signal U / D, but the output signals SQ1 to SQ4 are changed from the output signals sq1 to sq4 as shown in FIG. / ~ Sq4 /
To or from the output signal sq1 / to sq4 /
The up / down counter circuit can also be configured by the method of switching to q1 to sq4.

Similar to FIG. 4, this counter circuit has an input terminal TC for the clock signal CLK and output terminals T1 to TQ1 for outputting output signals SQ1 to SQ4 constituting the counter value.
A hexadecimal up / down counter circuit having T4 and an input terminal TS of a switching signal U / D for switching between up-counting and down-counting. The counter has a data input terminal D, a clock signal CLK input clock terminal C, a positive-phase output terminal Q for outputting the output signals sq1 to sq4, and an output signal opposite in phase to the output signals sq1 to sq4. Four stages of delay type D-FFs 41 to 44 having output terminals Q / of opposite phase for outputting sq1 / to sq4 / are provided. Further, an inverter 49 which is connected to the input terminal TS and outputs a switching signal U / DN having a phase opposite to that of the switching signal U / D, and output terminals of the D-FFs 41 to 44 of each stage based on the switching signal U / D Select one of the output signals from Q and the output terminal Q /
Multiplexers 45 to 48 for outputting to T4 are provided. Each of the multiplexers 45 to 48 is composed of two 2-input AND gates and one 2-input OR gate,
A switching signal U / is applied to one input terminal of each AND gate.
The input terminal TS of D or the output terminal of the inverter 49 is
Each is connected. The output terminals of the two AND gates are connected to the input terminals of the OR gates, and the output terminals of the OR gates serve as the output terminals of the multiplexer and are connected to the output terminals T1 to T4, respectively. First stage D
The clock terminal C of the -FF 41 is connected to the input terminal TC, and the output terminal Q and the output terminal Q / of the D-FF 41 are connected to the other input terminals of the two AND gates of the multiplexer 45, respectively. Similarly, each stage D-FF
The output terminals Q and Q / of 43, 44 and 45 are also connected to the input terminals of the multiplexers 46, 47 and 48. Further, each of the D-FFs 42 to 44 has the D-FF 41 of the preceding stage.
Output terminals Q of ~ 43 are connected to respective clock terminals C.

FIG. 6 is a diagram showing the counter value of the up / down counter. A change in the counter value when switching between up-counting and down-counting will be described with reference to FIG. U / D in FIG. 6 is a switching signal U /
D signal levels, SQ1 to SQ4, indicate the signal levels of the output signals SQ1 to SQ4, respectively. Also, H
EX is obtained by reading SQ1 to SQ4 by the binary system and converting them into hexadecimal numbers. When the switching signal U / D is "0",
The up / down counter circuit performs up counting. The switching signal U / D is set to "1" in order to count down when the HEX counts up to 3.
Then, HEX becomes B, and down counting is performed from the state where HEX is B. However, as shown in FIG.
Even if the up-down counter circuit is configured by the method described above, if the count operation is switched by the switching signal U / D during the up-counting operation or the down-counting operation, the counter value before switching is switched. The problem that the later counter values are different cannot be solved. The present invention provides an up-down counter circuit that solves the problem that the counter value changes when switching between up-counting and down-counting, as a problem that the above-mentioned prior art has.

[0011]

In order to solve the above-mentioned problems, the present invention provides a plurality of flip-flops (hereinafter, referred to as a flip-flop for inputting data at a predetermined timing and outputting a positive-phase output signal and a negative-phase output signal thereof). FF) in cascade connection, based on a second clock signal of the first and second clock signals having the same cycle and different phases, and a switching signal for switching up or down counting, A control signal generating circuit for generating a first control signal and a second control signal, and outputs a positive-phase or negative-phase output signal of the front-stage FF to the rear-stage FF in synchronization with the first clock signal. And a plurality of first gate circuits that operate. Further, a second gate circuit for inputting the first clock signal to the first stage FF and forcibly inputting the first control signal to the first stage FF to invert the data held in the FF. A plurality of output signals of the first gate circuit are input to the FF of the next stage, and the first control signal is forcibly input to the FF of the next stage to invert the data held in the FF. A third gate circuit and a plurality of multiplexers for selecting and outputting either the positive-phase output signal of the FF of each stage or its negative-phase output signal based on the second control signal are provided. There is.

[0012]

According to the present invention, since the up-down counter circuit is configured as described above, when the switching signal is input, the first control signal and the second control signal are generated. The first control signal inverts the data held in the FF in each stage, and the inverted data held in the FF is used in the FF in the next stage.
Entered in. Therefore, the counting operation performed by the up / down counter circuit is switched before the switching signal is input. At the same time, by the second control signal,
The output of the multiplexer is switched from the positive phase output signal of each stage FF to the negative phase output signal or from the negative phase output signal to the positive phase output signal. This makes it possible to match the counter values before and after the switching of the count operation. Therefore, the above problem can be solved.

[0013]

1 is a circuit diagram showing an up / down counter according to an embodiment of the present invention. The up / down counter circuit performs up-counting or down-counting with the first clock signal CLK1 generated from the reference clock signal CLK, and also generates the clock signal CLK from the switching signal U / D and the reference clock signal CLK.
A hexadecimal up / down counter circuit that can switch up-counting or down-counting without changing the counter value by a second clock signal CLK2 having the same cycle as that of 1 but a different phase. This counter has an input terminal TC1 for a clock signal CLK1, an input terminal TC2 for a clock signal CLK2, an input terminal TS for a switching signal U / D, and output terminals for outputting output signals SQ1 to SQ4 that form a counter value. It has T1 to T4.

The up / down counter circuit includes four stages of D-FFs 51-54 for up-counting or down-counting the input clock signal CLK1. Each of the D-FFs 51 to 54 has a data input terminal D, a clock signal CLK input clock terminal C, and a positive-phase output terminal Q that outputs the output signals sq1 to sq4.
Output signals sq1 /-having a phase opposite to that of the output signals sq1-sq4
It has an opposite-phase output terminal Q / for outputting sq4 /. Further, a control signal generation circuit 60 for generating the first control signal A and the second control signal B from the switching signal U / D and the clock signal CLK2 is provided. Here, the control signal generation circuit 60 has two D-FFs 61 and 62 and an exclusive OR circuit 63, and the input terminal TC2 is the D-FF6.
The input terminal TS is connected to the clock terminals C of 1, 62 and the data input terminal D of the D-FF 61. The output terminal for the control signal B of the control signal generation circuit 60 is connected to the inverter 64 that outputs the control signal B / having a phase opposite to that of the control signal B, and the control signal B outputs the control signal B and the control signal B / It is designed to branch to. DF
The input terminal TS of the F61 is connected to the input terminal TS, the output terminal Q of the D-FF61 is connected to the data input terminal D of the D-FF62, and the control signal B is output from the output terminal Q of the D-FF62. Is output. The input terminal of the exclusive OR circuit 63 has a D-FF 6
1, 62 output terminals Q are connected, the output terminal of the exclusive OR circuit 63 is connected to each input terminal of the gate circuits 81-84, and the control signal A is output.

Further, the up-down counter circuit includes a D-FF on the preceding stage side in synchronization with the clock signal CLK1.
The first gate circuits 71 to 73 for outputting the outputs of 51 to 53 to the subsequent D-FFs 52 to 54 respectively, and the clock signal CLK1 and the control signal A are input to receive the clock signal CLK.
The second gate circuit 81 which outputs 1 and the control signal A, and the outputs of the gate circuits 71 to 73 and the control signal A are input to output the outputs of the gate circuits 71 to 73 and output the control signal A. Third gate circuits 82 to 8 for outputting
4 and the output signal sq1 from the output terminals Q of the D-FFs 51 to 54 based on the control signal B and the control signal B /.
~ Sq4 and the output signal sq1 / from the negative-phase output terminal Q /
Select any one of sq4 / to output signals SQ1 to SQ1.
Multiplexers 91 to 94 for outputting to Q1 as output terminals T1 to T4 are provided.

Each of the second gate circuits 81 to 84 is composed of one OR gate. Further, the gate circuit 71 is composed of one AND gate, and its AN
The input terminal of the D gate is connected to the input terminal TC1. Each of the gate circuits 72 to 73 is composed of two AND gates, and the input terminal of the AND gate on the output side is connected to the input terminal TC1. Each multiplexer 91
.About.94 each have two AND gates on the input side and one OR gate on the output side. This each A
One input terminal of the ND gate has an output terminal for the control signal B of the control signal generation circuit 60 and the inverter 6
The four output terminals are connected to each other. The output terminal of the gate circuit 81 is connected to the clock terminal C of the first-stage D-FF 51, the output terminal Q of the D-FF 51 is connected to the input terminal of the multiplexer 91, and the gate circuit 71 and the gate circuit 82. Next D-FF52
Is connected to the input terminal C of. Similarly, the output terminals Q of the D-FFs 52 and 53 are connected to the input terminals of the multiplexers 92 and 93, and the D-FFs 53 and 5 of the next stage are connected.
4 input terminals C, respectively. The output terminal of the final stage D-FF 54 is connected to the input terminal of the multiplexer 94.

FIG. 7 is a time chart of the level of each signal according to the embodiment of the present invention. The operation of FIG. 1 will be described with reference to FIG. In FIG. 7, HEX represents the counter value of the up / down counter in hexadecimal notation,
HEX is displayed from 0. Switching signal U /
When D is “0”, the up / down counter circuit
The output signals sq1 to sq4 are input to the clock terminals C of the D-FFs 52 to 54 with the up count specified, and the output signals sq1 to sq4 are selected as the output signals SQ1 to SQ4. When HEX in FIG. 7 is 2 and time ta is,
When the switching signal U / D transitions to "1", the control signal A is generated in synchronization with the rising edge of the clock signal CLK2, and each D-FF is synchronized with the falling edge of the control signal A.
The levels of the output signals sq1 to sq4 of 51 to 54 are inverted. Simultaneously with this operation, the output signals sq1 / to sq4 / are output to the output signals SQ1 to SQ4 based on the control signal B generated in synchronization with the falling edge of the clock signal CLK2.
Is selected. Therefore, there is no change in the levels of SQ1 to SQ4, and HEX remains 2. From the next falling edge of the pulse of the clock signal CLK1, the output signals selected by the multiplexer are output signals sq1 / to sq.
It remains 4 /. As a result, SQ1 to SQ4 count down.

Next, when the level of the switching signal U / D is set to "1" at the time tb in FIG. 7, the clock signal CL is set.
The control signal A is generated in synchronization with the rising edge of K2, and each of the D-FFs 51 to 51 is synchronized with the falling edge of the control signal A.
The levels of the output signals sq1 to sq4 of 54 are inverted.
At the same time as this operation, the control signal B becomes "0" in synchronization with the falling edge of the clock signal CLK2, and the output signal SQ1
Output signals sq1 to sq4 are selected for SQ4.
Therefore, the level of SQ1 to SQ4 does not change and H
EX remains F. From the next falling edge of the pulse of the clock signal CLK1, the output signals selected by the multiplexers 91 to 94 remain the output signals sq1 to sq4. Therefore, SQ1 to SQ4 count up. As described above, in the present embodiment, it is possible to realize an up-down counter circuit that does not change the counter value even if the up-count or the down-count is switched during the counting operation. Further, since the up / down counter circuit synchronized with the clock signal is composed of circuits having substantially the same pattern, it can be incorporated in the same circuit.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications. (1) D- involved in up-counting and down-counting
The FFs 51 to 54 may have any number of stages, and the D
-FF may be replaced with another FF such as a toggle FF. (2) D-FFs 61 and 62 in the control signal generation circuit 60
May be replaced with a toggle FF or the like. (3) AND gates in the multiplexers 91 to 94 are
It may be configured by using a transfer gate or an exclusive OR gate.

[0020]

As described in detail above, according to the present invention, the second clock signal CL in the up counter is used.
A control signal generation circuit 60 for generating the first control signal A and the second control signal B based on K2 and the switching signal U / D is provided. Further, the second and third output signals of the D-FFs 51 to 54 at the respective stages are inverted by the first control signal A.
Since the gate circuits 81 to 84 and the plurality of multiplexers 91 to 94 that select the outputs of the D-FFs 51 to 54 in each stage based on the second control signal B are provided, the up counting is performed in the middle of the counting operation. It is possible to obtain an accurate up / down counter circuit in which the counter value does not deviate even when the and down counts are switched. This eliminates the need for means for correcting the counter value. Further, even when there is no means for correcting the counter value, it is not necessary to switch between up-counting and down-counting after waiting for the end of the counting operation cycle or reset.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an up / down counter circuit showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional up counter.

FIG. 3 is a circuit diagram showing a conventional down counter.

FIG. 4 is a circuit diagram showing a conventional up / down counter circuit.

FIG. 5 is a circuit diagram of an up / down counter circuit for explaining a conventional problem.

6 is a diagram showing the count value of FIG. 5;

FIG. 7 is a time chart of FIG.

[Explanation of symbols]

 51-54 D-FF 60 Control signal generation circuit 71-74 1st gate circuit 81 2nd gate circuit 82-84 3rd gate circuit 91-94 Multiplexer U / D switching signal CLK1 1st clock signal CLK2 1st 2 clock signal A 1st control signal B 2nd control signal

Claims (1)

[Claims] 1. An up-counter circuit in which a plurality of flip-flops for inputting data at a predetermined timing and outputting a positive-phase output signal and a negative-phase output signal thereof are cascade-connected, and first and different phases having the same cycle. A control signal generating circuit for generating a first control signal and a second control signal based on a second clock signal of the second clock signals and a switching signal for switching the addition counting operation or the subtraction counting operation; A plurality of first gate circuits that respectively output the positive-phase or negative-phase output signal of the front-stage flip-flop to the second-stage flip-flop in synchronization with the first clock signal; The first control signal is forcibly input to the flip-flop of the first stage while being input to the flip-flop of the first stage. A second gate circuit that inverts data, and an output signal of the first gate circuit are input to the flip-flop of the next stage, and the first control signal is forcibly input to the flip-flop of the next stage. A plurality of third gate circuits for inverting the data held in the flip-flops, and either one of the positive-phase output signals of the flip-flops of the respective stages or the reverse-phase output signals thereof based on the second control signal. An up-down counter circuit characterized in that a plurality of multiplexers for selecting and outputting are provided.