JP3243801B2 - Digital input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital input circuit.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional digital input circuit, and FIG. 4 is a timing chart for explaining the operation of the digital input circuit shown in FIG. OUT of the output terminal, 6 is a shift register, 7 aND gates, 8 noise elimination circuit, 10 a clock control circuits.

The shift register 6 has a four-stage configuration of D-type flip-flops 6a to 6d, which are cascade-connected in a serial input / parallel output type. The shift register 6 has a Q terminal for each of the flip-flops 6a to 6c and a flip-flop. The Q ′ terminal of the gate 6 d is connected to each input of the AND gate 7 . Noise removal circuit 8
Is composed of AND gates 8a and 8b and an inverter 8c. Each input of the AND gate 8a has a Q terminal of a flip-flop 6b and a flip-flop 6c.
Are connected to the input terminal of the AND gate 8b. The input terminal of the inverter 8c is connected to the output terminal of the AND gate 8a and the output terminal of the inverter 8c. Is the input terminal 2 for the input signal A
It is connected to the.

In such a digital input circuit,
Clock terminal C of each of flip-flops 6a to 6d
A clock CK having a period as shown in FIG. Then, the input terminal D of the flip-flop 6a
At time t0, when a normal input signal A having a signal length of, for example, four times or more the period of the clock CK is input, the Q terminal of each of the flip-flops 6a to 6c connected in cascade and the flip-flop 6d An output FF1 that rises to a high level in response to a rising input from the Q 'terminal at times t1, t2, t3, and t4 of the clock CK.
FF3 and an output FF4 falling to a low level.

[0005] The AND gate 8a operates at time t2-
At t3, the high-level output FF2 from the Q terminal of the flip-flop 6b and the high-level output from the Q 'terminal of the flip-flop 6d (the Q terminal output FF at the time t2 to t3).
3 is at a low level and is at a high level because it is the inverse of the low level. ) Is output. This time t
From 2 to t3, since the normal high-level input signal A is input to the input terminal 2, the output of the inverter 8c, which is the inverted output thereof, is at the low level.

Therefore, the output of the AND gate 8b, which is the logical product G2 of the inverter 8c and the AND gate 8a at the time t2 to t3, remains low.
Since the flip-flops 6a to 6d are not reset by the logical product G2 of the AND gate 8b, at time t3,
Q terminal outputs FF1-F of flip-flops 6a-6c
F3 is at a high level and the flip-flop 6
Since the Q 'terminal output FF4 of d is also at the high level, the AND gate 7 outputs the high-level output signal OU for counting the normal input signal A from time t3 to t4.
T is output from the output terminal 4 as a count output. When the normal input signal A is input from the input terminal 2 as described above, the count output OUT is output from time t3 to t4.

On the other hand, a plurality of synchronous noises synchronized with the cycle of the clock CK may be continuously input to the input terminal 2 as the input signal A as shown after time t5. Such synchronization noise is counted out OUT
In this case, an erroneous count is generated. To prevent this erroneous count, the D of the flip-flop 6a is set at time t5.
When the synchronous noise is input to the input terminal, time t6 , t6
7 and t8, the flip-flops 6a to 6c output the output FF1 to FF3 rising from the respective Q terminal to the high level at the rising edge of the clock CK at time t9.
At the rising edge of the clock CK, the flip-flop 6d outputs an output FF4 that falls to a low level. During the time t7 to t8, the Q terminal output FF2 of the flip-flop 6b and the Q ′ terminal output of the flip-flop 6c are output. Is also at a high level, so that the AND gate 8a
Outputs a high-level AND output G1. Then, from time t7 to time t8, since the input signal A is at the low level, the output of the inverter 8c is at the high level. Therefore, the AND output G2 of the AND gate 8b becomes high level from the high-level AND output G1 from the AND gate 8a and the high-level output of the inverter 8c, and the flip-flops 6a to 6d are reset. As a result, during this time t7 to t8, AN
The count output OUT is not output from the D gate 7, and the input signal A that causes erroneous counting such as synchronization noise is not counted.

Next, the clock control circuit 10 will be described. The clock control circuit 10 comprises a reference clock generation circuit 10a, frequency dividers 10b and 10c, a clock setting switch 10d, and a clock selection circuit 10e. The reference clock generation circuit 10a generates a reference clock, the frequency divider 10b divides the frequency of the reference clock from the reference clock generation circuit 10a, and the frequency divider 10c outputs the frequency of the frequency divider 10b. Is to further divide the frequency-divided clock. Therefore,
The output of the frequency divider 10b has a longer period than the reference clock.
That is, the clock is a high-speed clock, and the output of the frequency divider 10c is a low-speed clock having a longer cycle than the clock.

The clock setting switch 10d is a switch for setting the period of the clock CK for each of the flip-flops 6a to 6d, and is a clock selection circuit 10e.
Selects one of the high-speed clock from the frequency divider 10b and the low-speed clock from the frequency divider 10c in accordance with the cycle set by the clock setting switch 10d, and supplies a shift operation clock to each of the flip-flops 6a to 6d. It is output as CK.

In such a clock control circuit 10, it is necessary that at least four clocks CK exist within the signal width of the input signal A. Therefore, when the signal width of the input signal A is short, the high-speed clock CK on the output side of the frequency divider 10b is used. When the signal width of the input signal is long, the low-speed clock CK on the output side of the frequency divider 10c is used.
It is necessary to select the clock CK by operating the clock setting switch 10d by the operator.
Had to be selectable.

[0011]

However, if the clock setting switch 10d is operated to select the clock CK as described above, an erroneous operation may occur, so that a count for a desired input signal cannot be performed, or Synchronization noise cannot be removed.

Accordingly, an object of the present invention is to automatically select an appropriate clock corresponding to the input signal width from the signal width.

[0013]

To achieve the above object, a digital input circuit according to the present invention includes a shift register (6) and a clock control circuit (10 '). The shift register (6) is formed by cascade-connecting a plurality of flip-flops (6a to 6d). In response to a shift operation clock to each of the flip-flops (6a to 6d), an input signal is transmitted from the first-stage flip-flop. The clock control circuit (10 ') sequentially shifts to a subsequent flip-flop.
Clock generation circuit (10a) and the reference clock generation circuit
To divide these clock signals and output a high-speed clock.
A high-speed clock generating frequency divider (10b);
For low-speed clock generation by dividing the frequency and outputting a low-speed clock
A frequency divider (10c) for dividing the low-speed clock and resetting
Clock divider for outputting reset clock
(10j) and the frequency divider (10
delay processing of the reset clock output from j)
A delay circuit (10 m), a count circuit (10 h),
Switch circuit (10i), clock selection circuit (10e)
The has, the counting circuit (10h) is adapted to count the number of signals of the input signal, before a predetermined period
The reset clock input from the delay circuit (10m) .
When the count is reset by the lock and the count value reaches a predetermined value within the predetermined period, a high-speed clock selection signal for selecting a high- speed clock is output.
When the count value does not reach the predetermined count value, the latch circuit (10i) outputs a low-speed clock selection signal for selecting a low-speed clock.
The clock selection signal output from the circuit (10h) is latched.
And the reset clock generating frequency divider (10j)
Until the reset clock is input.
It is intended to hold the switch state, the clock selecting circuit (10e), the high-speed clock generated when the high-speed clock selection signal from the latch circuit (10i) is given
Use dividers speed clock output from (10b), also the low-speed when the low-speed clock selection signal is given
The low-speed clock output from the clock generating frequency divider (10c) is selected and output to each of the flip-flops (6a to 6d).

[0014]

In the present invention, the count circuit (10h)
Counts input signals and generates reset clock
Input via raw frequency divider (10c) and delay circuit (10m)
When the predetermined count value is reached within the period of the reset clock to be input , the high-speed clock selection signal is output . When the count value does not reach the predetermined count value, the low-speed clock selection signal is output .
Output to the latch circuit (10i), respectively.
(10i) latches the clock selection signal and resets it.
Reset from the frequency divider (10j) for generating a reset clock.
Hold the latched state until the clock for
You . The clock selection circuit (10e) includes a latch circuit (10e).
The high-speed clock is selected when the high-speed clock selection signal is supplied from i), and the low-speed clock that is slower than the high-speed clock when the low-speed clock selection signal is supplied from the latch circuit (10i). The shift register (6) shifts the input signal in response to a high-speed or low-speed clock from the clock control circuit (10 '). In addition, low speed
Reset clock of the count circuit (10h)
Since the lock is generated, the circuit configuration can be simplified.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a digital input circuit provided with a clock control circuit according to an embodiment of the present invention. Parts corresponding to those in FIG. Here, the detailed description of is omitted.

The clock control circuit 10 'of this embodiment comprises a conventional reference clock generation circuit 10a, a frequency divider 10b,
c and a clock selection circuit 10e, which is the same as the conventional example.
Instead of omitting d, an AND gate 10f, an inverter 10g, a count circuit 10h, a latch circuit 10i, a third frequency divider 10j, a differentiating circuit 10k, and a delay circuit 1
0 m.

The clock control circuit 10 'having such a configuration.
2 will be described with reference to the timing chart of FIG. 2. The input signal A is input to the input terminal 2. In this case, the input signal A has a short signal width and a high frequency in the period X, and has a long signal width and a low frequency in the period Y. Frequency divider 10b as frequency divider for high-speed clock generation
From the reference clock B of the reference clock generation circuit 10a.
The high-speed clock C obtained by dividing the frequency
A low-speed clock D obtained by dividing the high-speed clock C is output from a frequency divider 10c as a divider, and both clocks C and D are respectively supplied to a clock selection circuit 10e, and the low-speed clock D is used for generating a reset clock. Minute
It is provided to a frequency divider 10j as a frequency divider. This divider 1
The clock E is output from 0j as a reset clock ( not shown) obtained by further dividing the low-speed clock D. From the differentiating circuit 10k, a reset
A differential clock F is output as a reset clock, and the differential clock F is supplied to the delay circuit 10m and the latch circuit 10i. The differential clock F is a delay circuit 10
After being delayed by m, it is supplied to the count circuit 10h as a reset delay clock G. Counting circuit 10h
Counts the number of the input signals A during the cycle of the delay clock G. When a predetermined count value, for example, counts up within the cycle of the delay clock G, the carry is increased to the most significant bit. Then, a high-level carry signal H is output. Carry signal H is output from inverter 10f
To make it low level, so that even if the input signal A enters the AND gate 10f, it does not enter the count circuit 10h. On the other hand, carry signal H from count circuit 10h is supplied to differential clock F in latch circuit 10i.
At the rising edge of the clock selection signal I, the latched state of the clock selection signal I is held until the next differential clock F rises. Counting circuit 1
0h is reset by the delay clock G and repeats counting from zero.

The clock selection circuit 10e includes a latch circuit 1
0 i in the clock selection signal speed clock by the presence or absence of the latch of the I C or one selects the low-speed clock D, the output fast or slow clock C was selected, the D, as a shift operation clock CK of the shift register 6, I do. In this example, when carry signal H is output from count circuit 10h, high-speed clock C is selected as shift operation clock CK, and when carry signal H is not output, low-speed clock D is used as shift operation clock CK. Select as

Here, the cycle of the clock E is the cycle of the valid signal determined when the shift operation clock CK is the low-speed clock D, and the cycle of n of the value 2 for outputting the carry signal H when the count circuit 10h has n bits. The value is determined by the product of the power of -1. For example, if the period of the valid signal determined at the time of the high-speed clock C is 30 ms, and the count circuit 10h has 3 bits, the period of the clock E is 30 × 2 ² = 120.
ms. Therefore, when a short input signal A (within the period X) having a cycle of 30 ms or less is input, the counting circuit 1
The count value of 0h becomes 2 ² or more, a carry signal H is outputted fast clock C is a clock CK for the shift operation
Is selected as, when the period is long input signal A (the period Y) beyond the 30ms enters, the count value of the count circuit 10h is 2 ² follows it and carry signal H is low-speed clock D shift operation is not output Selected as clock CK.

With this configuration, when the signal width of the input signal A changes, the effective signal width automatically changes, so that proper noise removal can always be performed.

Although this embodiment has been described with reference to switching between two types of clocks, it is possible to switch between three or more types of clocks by increasing the number of outputs of the count circuit 10h and the number of frequency dividers. You may. In this embodiment, a description has been given of a hardware circuit configuration. However, a software circuit configuration using a microcomputer may be used.

[0023]

As is apparent from the above description,
According to the present invention, the count circuit counts an input signal, and generates a reset clock generating frequency divider, a delay
When the predetermined count value is reached within the period of the reset clock input through the path , the high-speed clock selection signal is sent to the latch circuit. When the predetermined count value is not reached, the low-speed clock selection signal is sent to the latch circuit. Output. latch
The circuit latches its clock select signal and resets it.
The reset clock from the lock generation frequency divider is input.
Hold the latched state until the The clock selection circuit, a high-speed clock when given a high-speed clock selection signal from the latch circuit, also a low-speed clock to be slower than the high speed clock when the low-speed clock selection signal from the latch circuit are given, respectively, Since the clock is selected and output, an appropriate clock is automatically selected according to the signal width of the input signal, and the shift register inputs at a shift speed according to the high-speed or low-speed clock from the clock control circuit. The signal can be shifted.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a digital input circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a circuit diagram of a digital input circuit according to a conventional example.

FIG. 4 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 6 shift register 10 'clock control circuit

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 5/1252

Claims (1)

(57) [Claims] 1. A shift register (6) and a clock control circuit (10 '), wherein the shift register (6) is formed by cascade-connecting a plurality of flip-flops (6a to 6d). are those sequentially shifted to the subsequent stage of the flip-flop input signal in response to the shift operation clock to each flip-flop (6 a to 6 d) from the first stage of the flipflop, said clock control circuit (10 ' ) Is the reference clock generation
Circuit (10a) and a clock from the reference clock generation circuit.
High-speed clock that divides clock signal and outputs high-speed clock
Frequency divider (10b) for dividing the high-speed clock
Clock generating frequency divider that outputs low-speed clock
(10c), the low-speed clock is divided and the reset clock is
Frequency divider for reset clock generation (10
j) and the reset clock generating frequency divider (10j)
Circuit that delays the reset clock output from the
Road (10m), count circuit (10h), latch times
(10i) and a clock selection circuit (10e).
And which, the counting circuit (10h) is adapted to count the number of signals of said input signal, said delay circuit at a predetermined cycle (1
0m) , the count is reset by the reset clock , and when the count value reaches a predetermined value within the predetermined period, a high-speed clock selection signal for selecting a high-speed clock is output . When the count value does not reach the predetermined count value, a low-speed clock selection signal for selecting a low- speed clock is output, and the latch circuit (10i) outputs the low-speed clock selection signal.
h) latching the clock selection signal output from
The reset from the reset clock generating frequency divider (10j)
The latch state is maintained until the set clock is input.
Is intended to lifting, the clock selection circuit (10e), said latch circuit
When the high-speed clock selection signal is given from (10i), the output from the high-speed clock generation frequency divider (10b) is output.
The supplied high-speed clock and the low-speed clock selection signal are applied to the low-speed clock generation frequency divider (10
A digital input circuit for selecting and outputting the low-speed clocks output from c) to each of the flip-flops (6a to 6d).