JPH0522087A - Digital input circuit - Google Patents

Abstract

PURPOSE:To automatically select a suitable clock corresponding to the signal width of an input signal according to the signal width and on the other hand, to exactly select the frequency of a filter clock even when there is chattering in the case of switching the signal width of the input signal by a contact, etc. CONSTITUTION:An input signal (in) is ANDed G1 based on the outputs of respective flip-flops FF1-FF4 and an output signal (out) is obtained. The number of input signals (in) is counted by a counter 14-1 for fixed time, and a count signal (g) is outputted. When the input signal (in) inputted parallelly to this signal (g) has the signal width wider than a fixed value, a digital filter part 12 outputs a valid signal (h). According to the count signal (g) and the valid signal (h), a clock selecting circuit 14-2 selects the frequency of a filter clock CK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention inputs an input signal to a plurality of flip-flops having a cascade connection structure and sequentially inverts and shifts the flip-flops in response to a filter clock in the flip-flops. The present invention relates to a digital input circuit that obtains an output signal by logically ANDing the outputs of a group.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional digital input circuit, and FIG. 4 is a timing chart for explaining the operation of the digital input circuit shown in FIG. 3. Reference numeral 2 is an input terminal of an input signal in, and 4 is an output signal. An output terminal of out, 6 is a shift register, is an AND gate, 8 is a noise removing circuit, and 10 is a clock control circuit.

The shift register 6 has a four-stage configuration of D-type flip-flops FF1 to FF4, which are cascade-connected in a serial input / parallel output type. The shift register 6 has respective Q terminals of the flip-flops FF1 to FF4 and a flip-flop. The Q'terminal of the flip-flop FF4 is connected to each input portion of the AND gate G1. The noise removing circuit 8 is composed of AND gates G2 and G3, and an inverter G4. The Q terminal of the flip-flop FF2 and the Q'terminal of the flip-flop FF3 are respectively provided at the respective input parts of the AND gate G2. , The output of the AND gate G2 and the output of the inverter G4 are connected to each input of the AND gate G3, and the input of the inverter G4 is connected to the input signal i.
n input terminals 2 are connected.

In such a digital input circuit,
A filter clock CK having a frequency as shown in FIG. 4 is applied to each clock terminal CK of the flip-flops FF1 to FF4. And the flip-flop F
The filter clock CK is applied to the D terminal of F1 at time t0.
A normal input signal i having a signal length of 4 times the period of
When n is input, the Q terminals of the flip-flops FF1 to FF3 and the Q'terminal of the flip-flop FF4 connected in cascade are responded to the rising input of the filter clock CK at times t1, t2, t3, and t4. Output FF1 to FF3 which rises to a high level and output FF4 which falls to a low level.

Then, the AND gate G2 has the time t2.
At t3, the high-level output FF2 from the Q terminal of the flip-flop FF2 and the high-level output from the Q'terminal of the flip-flop FF3 (the Q terminal output FF3 is at the low level at the times t2 to t3, And becomes a high level). At the times t2 to t3, since the normal high-level input signal in is input to the input terminal 2, the output of the inverter G4, which is the inverted output thereof, is at the low level.

Therefore, the output of the AND gate G2 which is the logical product G2 of the inverter G4 and the AND gate G2 at the times t2 to t3 remains at the low level.
Since the flip-flops FF1 to FF4 are not reset by the logical product G2 of the AND gate G2, at the time t3, the Q terminal outputs F of the flip-flops FF1 to FF4 are output.
Since F1 to FF3 are at a high level and the Q'terminal output FF4 of the flip-flop FF3 is also at a high level, the AND gate G1 is used to count the normal input signal A at times t3 to t4. A high-level output signal out is output from the output terminal 4. When the normal input signal in is input from the input terminal 2 as described above, the output signal out for counting the input signal in is output from the time t3 to t4.

On the other hand, as shown after time t5, a plurality of synchronous noises synchronized with the cycle of the filter clock CK may be continuously input to the input terminal 2 as the input signal in. If such synchronization noise is used as the output signal out, an erroneous count will occur. Therefore, in order to prevent this erroneous count, the flip-flop F at the time t5.
When synchronous noise is input to the D terminal of F1, at time t6,
The flip-flops FF1 to FF3 output from the respective Q terminals to the high level at the rising edges of the filter clocks CK at t7 and t8, and outputs FF1 to FF.
3 is output from the flip-flop FF4 to the low level at the rise of the filter clock CK at time t9, and from this time t7 to t8, the Q terminal output FF2 of the flip-flop FF2 and the Q of the flip-flop FF3 are output. Since the output of the 'terminal is at a high level, the AND gate G2 outputs a high-level AND output G2. Then, from this time t7 to t8
In, since the input signal in is at low level, the output of the inverter G4 is at high level. Therefore, A
From the high level AND output G2 from the ND gate G2 and the high level output from the inverter 8c, the AND gate G3
As a result, the AND output G3 becomes high level and the respective flip-flops FF1 to FF4 are reset. As a result, the count output out is not output from the AND gate G1 at the times t7 to t8, and the synchronous noise of The input signal in which causes such an erroneous count is not counted.

Next, the clock control circuit 10 will be described. The clock control circuit 10 includes a reference clock generation circuit 10-1, frequency dividers 10-2 and 10-3, a clock setting switch 10-4, and a clock selection circuit. It is composed of a circuit 10-5. Reference clock generation circuit 10-1
Is for generating a reference clock, and the frequency divider 10
The reference numeral 2-2 divides the reference clock from the reference clock generation circuit 10-1, and the divider 10-3 further divides the divided clock divided by the divider 10-2. It is a thing. Therefore, the output of the frequency divider 10-2 is a clock having a longer cycle, that is, a higher speed than the reference clock, and the output of the frequency divider 10-3 is a low speed clock having a longer cycle than the clock.

The clock setting switch 10-4 is a switch for setting the frequency of the filter clock CK for each of the flip-flops FF1 to FF4, and the clock selection circuit 10-5 is set by the clock setting switch 10-4. In response to the above, one of the high-speed clock from the frequency divider 10-2 and the low-speed clock from the frequency divider 10-3 is selected and output to each of the flip-flops FF1 to FF4 as the filter clock CK.

In such a clock control circuit 10, the filter clock CK is set within the signal width of the input signal in.
It is necessary that at least 4 exist. Therefore, when the signal width of the input signal in is short, the filter clock CK having a high frequency is output from the output side of the frequency divider 10-2, and when the signal width of the input signal is long, the frequency of the filter clock CK is changed from the output side of the frequency divider 10-3. Each low filter clock CK
It is necessary to select the frequency. Therefore, the operator operates the clock setting switch 10-4 to select the frequency of the filter clock CK.

[0011]

However, if the clock setting switch 10-4 is operated to select the frequency of the filter clock CK as described above, an erroneous operation may occur. It may not be possible, or synchronization noise may not be removed.

Therefore, in the present invention, while the selection of the frequency of the filter clock can be automatically selected based on the signal width of the input signal, the signal width of the input signal is set to, for example, a contact. An object of the present invention is to enable the frequency of the filter clock to be accurately selected without being affected by unnecessary waveforms before and after the input signal due to chattering generated by switching.

[0013]

In order to achieve such an object, in a digital input circuit of the present invention, an input signal is input to a plurality of flip-flops having a cascade connection structure, and in the flip-flops. In response to the filter clock, it is sequentially inverted and shifted, and the output signal is obtained by logically ANDing the outputs of each flip-flop, and the number of input signals is counted for a certain period of time. Counter means for outputting a count signal, digital signal means for inputting an input signal in parallel with the counter means, and for outputting an effective signal corresponding to the input signal when the input signal has a certain signal width or more, The frequency of the filter clock depends on the count signal from the counter means and the valid signal from the digital filter means. It is characterized by comprising a clock selection means for selecting.

[0014]

The input signal is input to a plurality of cascade-connected flip-flops, and the flip-flops are sequentially inverted and shifted in response to the filter clock, and the outputs of the flip-flops are logically ANDed. In obtaining the output signal, the counter means counts the number of input signals for a certain period of time, and outputs a count signal corresponding to this. Further, the digital filter means inputs an input signal in parallel with the counter means, and when the inputted input signal has a certain signal width or more, outputs an effective signal corresponding thereto. The clock selection means selects the frequency of the filter clock based on the count signal from the counter means and the valid signal from the digital filter means.

Therefore, although the signal width of the input signal is switched by a contact or the like, chattering or the like occurs before and after the input signal, but in the counter means,
When counting the number of input signals for a certain period of time, the chattering is included in the number of signals and counting is performed, and the count signal is given to the clock selecting means to select the frequency of the filter clock. In such a case, the valid signal from the digital filter means is given to the clock selecting means. As a result, the clock selection means can select the frequency of the filter clock from the count signal from the counting means based on the valid signal, so that the mistake of the frequency selection of the filter clock due to chattering can be eliminated.

[0016]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of a digital input circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation. In FIG. 1, 2 is an input terminal, 4
Is an output terminal, 6 is a shift register, 8 is a noise removing circuit, and G1 is an AND gate. These are the same as those in FIG.

A digital filter unit 12 has the same circuit configuration as the shift register 6, the noise removing circuit 8 and the AND gate G1.

Reference numeral 14 is a clock control circuit, and as a circuit shown by a block, a counter 14-1, a clock selection circuit 14-2, a reference clock generation circuit 14-3, and frequency dividers 14-4 to 14-6. , Differential circuits 14-7, and delay circuits 14-8, 14-9, and AND gates G5, G7, OR gates G9, G11, inverters G6, G8, G12, and flip-flops as logic circuit elements. FF5, FF6, FF7.

The reference clock a from the reference clock generation circuit 14-1 is sequentially divided by frequency dividers 14-4, 14-5 and 14-6, and frequency dividers 14-4 and 14-5 are respectively provided. The divided clocks b and c of the high-speed clock b and the low-speed clock c are supplied to the clock selection circuit 14-2.
Given as. The divided clock c of the frequency divider 14-5 is also input to each flip-flop of the digital filter unit 12 as a shift operation clock. Frequency divider 14
The divided clock d of −6 is differentiated by a differentiating circuit 14-7 for the purpose of resetting a clock or the like which will be described later, and the differentiated clock e is delayed by the delay circuit 14-8 and the flip-flop FF.
6 and FF7. The differential clock e input to the delay circuit 14-8 is delayed here for reset timing adjustment. This delay clock f is used by the counter 1
4-1 and the flip-flop FF5 are input as reset inputs.

The counter 14-1 counts the number of signal inputs of the input signal in during the period of the delay clock f, and when counting up within the period of the delay clock f, carries to the most significant bit. Then, the high-level count signal g is output, and when it does not count up within the period, it is reset to 0 by the delay clock f.

The count signal g is inverted by the inverter G6 and becomes low level, and the input signal i is input to the AND gate G5.
Even if n is entered, it should not be entered in the counter 14-1. On the other hand, the count signal g from the counter 14-1 is input to one input portion of the AND gate G7.

Here, when the signal width of the input signal in is switched from a short signal to a long signal with a contact or the like, chattering occurs before and after the input signal in at the time of switching, but due to this chattering, the original input is caused. The signal width of the signal in is i in part a in the timing chart of FIG.
As shown by n ', the width becomes a certain width or more. Then, the digital filter unit 12 responds to the input of the input signal in ′ having a certain width or more, which is formed by sandwiching the chattering due to the chattering as shown in FIG. The gate G10 outputs a valid signal h indicating that the input signal has a certain width or more, and the valid signal h is O
The valid signal h is input to the input terminal D of the flip-flop FF5 via the R gate G9, and the flip-flop FF5 latches the valid signal h at the rising edge of the delay clock i delayed by the delay circuit 14-9. The valid signal latch output j from the flip-flop FF5 is the OR gate G9.
Is held by being guided to the flip-flop FF5, and is held until the delay clock f is input.

The high-level valid signal latch output j from the flip-flop FF5 is inverted by the inverter G8 to a low level and then input to the other input section of the AND gate G7.

Therefore, the counter 14-1 counts, including chattering, the input signal at the section a,
The corresponding counter 14-1 to the AND gate G7
Even if the count signal g is output to one input section of the
The D gate G7 is turned off by the valid signal latch output j inverted to the low level, so that the count signal g from the counter 14-1 during chattering is not input to the flip-flop FF7. Then, this flip-flop FF7 falls to the low level at the next differential clock e and is reset. On the other hand, the valid signal latch output j is input to the flip-flop FF6, and the flip-flop FF6 rises to the high level at the next differential clock e and is set to output the high-level output m corresponding to the valid signal.

Therefore, in the clock selection circuit 14-2, the flip-flop F from the flip-flop FF7.
Since the high level output m from F6 is output as the low speed clock selection signal p via the OR gate G11, the clock selection circuit 14-2 selectively outputs the low speed clock c as the filter clock CK. ..
When the chattering continues thereafter, the count signal g is output from the counter 14-1.
Since the D gate G7 is off, the clock selection circuit 14
-It is not given to 2.

In the part B where the chattering is completed, since the count signal g from the counter 14-1 and the latch output j of the flip-flop FF5 are both input signals having a long cycle, the OR gate G1 is used.
1 and the inverter G12 output the low speed clock selection signal p, and the low speed clock c is selected as the filter clock CK.

Further, after the section b, since the valid signal latch output j disappears this time, the output of the inverter G8 becomes high level, and the flip-flop FF6 falls to the low level by the differential clock e and is reset. Therefore, the count signal g from the counter 14-1 is AN
It is applied to the flip-flop FF7 via the D gate G7. As a result, the flip-flop FF7 rises to the high level and is set, and outputs the high-level output n. Since this high-level output n is given to the clock selection circuit 14-2 as a low speed clock selection signal, the clock selection circuit 14-2 selectively outputs the low speed clock c as the filter clock CK.

In this embodiment, selection of two types of filter clocks, high speed and low speed, has been described, but the present invention is not limited to this type, and the number of outputs of the counter 14-1 and the number of frequency dividers are not limited thereto. May be appropriately added so that three or more types of filter clocks can be selected. Although this embodiment has been described with a hardware circuit configuration, it may be configured with a software circuit configuration using a microcomputer.

[0030]

As is clear from the above description,
According to the present invention, an input signal is input to a plurality of cascade-connected flip-flops, and the flip-flops are sequentially inverted and shifted in response to a filter clock, and the output of each flip-flop is logically changed. When the output signal is obtained by multiplying, the counter means counts the number of the input signals for a certain period of time and outputs the count signal, while the digital filter means inputs the input signal in parallel with the input signal. When the input signal has a certain signal width or more, a valid signal corresponding to this is output, and the clock selection means selects the frequency of the filter clock by the count signal from the counter means and the valid signal from the digital filter means. As a result, the filter clock can be automatically switched. To the signal width of the input signal for switching the like reed, even if chattering occurs before and after the input signal, the frequency of the filter clock can be automatically without error accurately selected.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a digital input circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a circuit diagram of a digital input circuit according to a conventional example.

FIG. 4 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 2 input terminal 4 output terminal 6 shift register 12 digital filter section 14 clock control circuit 14-1 counter section 14-2 clock selection circuit

Claims (1)

Claim: What is claimed is: 1. An input signal is input to a plurality of flip-flops having a cascade connection structure, and the flip-flops are sequentially inverted and shifted in response to a filter clock in the flip-flops. In a digital input circuit that obtains an output signal by logically ANDing the outputs of the counters, a counter means that counts the number of signals of the input signal for a certain period of time and outputs a count signal corresponding to the counter means, and an input signal in parallel with the counter means. When inputting and the input signal that is input is a certain signal width or more,
It is characterized by further comprising digital filter means for outputting a valid signal corresponding to this, and clock selecting means for selecting the frequency of the filter clock by the count signal from the counter means and the valid signal from the digital filter means. Digital input circuit.