JPH05291893A - Clock selection circuit - Google Patents

Abstract

PURPOSE:To provide the clock selection circuit in which generation of a spike to an output waveform and disturbance of a width of a clock pulse are effectively prevented at the changeover of a clock signal. CONSTITUTION:The clock selection circuit is provided with 1st and 2nd pulse generating circuits 13-16 generating a pulse synchronously with a trailing of 1st and 2nd clock signals respectively, a 2-input AND circuit 17 receiving an output of the 1st and 2nd pulse generating circuits, a latch circuit 18 using the output of the 2-input AND circuit 17 as a control input, using a clock selection signal as a data input and outputting the data input when the control input is at a high level and latching and outputting the data input hen the control input is at a low level, and selection circuits 11, 12, 19, 20 selecting the 1st and 2nd clock signals based on the output of the latch circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock selection circuit in a logic circuit.

[0002]

2. Description of the Related Art As a conventional clock selection circuit, for example, "Design of digital IC circuit" (Toshio Yuyama, 11th edition,
CQ publishing company) pages 39-40, what is shown in FIG. 3 is described. In the clock selection circuit shown in FIG.
The first 2-input AND circuit 1 receives the first clock signal CK1.
The second clock signal CK2 to the second input terminal
Of each of the first and second 2-input AND circuits 1, 2.
The clock selection signal SEL is supplied to the other input terminal of 2 after being inverted by the inverter circuit 3, and the outputs of the first and second 2-input AND circuits 1 and 2 are supplied to the 2-input OR circuit 4.
The first clock signal CK1 and the second clock signal CK2 are selectively output by the clock selection signal SEL.

[0003]

However, in the conventional clock selection circuit shown in FIG. 3, both the clock signals CK1 and CK2 are high when the first and second clock signals CK1 and CK2 are synchronized. When the clock selection signal SEL is switched from the high level to the low level in the level state, there is a problem that spikes occur in the output.

That is, as shown in the timing chart of FIG. 4, when the clock selection signal SEL changes from high level to low level, the output Z of the second 2-input AND circuit 2 simultaneously changes from high level to low level. Inverter circuit 3
Output X from the low level to the high level is delayed by the delay time in the inverter circuit.
The output Y of the D circuit 1 changes from low level to high level later than the change of the output Z of the second 2-input AND circuit 2. As a result, the input of the 2-input OR circuit 4 becomes low level at the same time, which causes a negative spike in its output OUT.

The first and second clock signals CK1,
When CK2 is asynchronous, it is necessary to perform switching when their phases match, but the conventional clock selection circuit shown in FIG. 3 has a function of detecting the matching of phases and switching the clocks. I don't have it. For this reason,
When the clock selection signal SEL is switched, the clock is switched, and as shown in FIG. 5, the pulse width of the output waveform is changed depending on the timing of change of the first and second clock signals CK1 and CK2. There is also a problem.

The present invention has been made by paying attention to such a conventional problem, and it is necessary to appropriately prevent the generation of spikes in the output waveform and the disturbance of the clock pulse width at the time of switching the clock signal. An object is to provide a configured clock selection circuit.

[0007]

In order to achieve the above object, according to the present invention, a first pulse generating circuit for inputting a first clock signal and generating a pulse synchronized with its falling edge, and a second pulse generating circuit A second pulse generating circuit that inputs a clock signal and generates a pulse synchronized with its falling edge, a two-input AND circuit that receives the outputs of these first and second pulse generating circuits, and this two-input AND circuit The output of the circuit is used as a control input, the clock selection signal for selecting the first and second clock signals is used as a data input, and when the control input is at a high level, the data input is output and at a low level. In this case, a latch circuit that latches and outputs a data input and the first and second clock signals are input, and these clock signals are output from the latch circuit. Constituting the clock selection circuit by a selection circuit for selecting based on.

[0008]

In such a configuration, the output of the 2-input AND circuit that receives the outputs of the first and second pulse generation circuits becomes high level when both the first and second clock signals are low level, The clock selection signal at that time is output from the latch circuit, and the first and second clock signals are selected based on it. Therefore, the switching of the first and second clock signals is performed when the phases of both are the same and both are at a low level, so that no spike occurs in the output waveform at the time of switching and the output pulse is The width does not change.

[0009]

1 shows an embodiment of the present invention. In this embodiment, the first clock signal CK1 is
The second clock signal CK2 is supplied to one input terminal of the 2-input AND circuit 11 of FIG. The first clock signal CK1 is supplied to one input terminal of the first two-input NOR circuit 13 and is supplied to the other input terminal of the NOR circuit 13 via the first inverting delay element 14. .. Similarly, the second clock signal CK2 is the second 2-input NO
It is supplied to one input terminal of the R circuit 15 and is supplied to the other input terminal of the NOR circuit 15 via the second inverting delay element 16.

First and second 2-input NOR circuits 13 and 15
Is supplied to the third 2-input AND circuit 17, and the output of the AND circuit 17 is supplied to the control signal input terminal G of the latch circuit 18. The clock selection signal SEL is supplied to the data input terminal D of the latch circuit 18,
When the control signal supplied to the input terminal G is at a high level, the data supplied to the data input terminal D is passed and output from the output terminal. When the control signal is at a low level, the data is latched and the latched data is stored. Output from the output terminal. The output of the latch circuit 18 is the second 2-input AN.
It is supplied to the other input terminal of the D circuit 12 and is also supplied to the other input terminal of the first two-input AND circuit 11 via the inverter circuit 19, and these first and second two-input AN
The outputs of the D circuits 11 and 12 are supplied to the 2-input OR circuit 20 to obtain the output signals OUT of the first clock signal CK1 and the second clock signal CK2 selected by the clock selection signal SEL.

The operation of this embodiment will be described below with reference to the timing chart shown in FIG. In FIG. 1, when the first and second clock signals CK1 and CK2 fall, the outputs a and b of the first and second two-input NOR circuits 13 and 15 have first and second inversion delays, respectively. Element 1
A positive pulse having a pulse width of a delay of 4, 16 is generated. Therefore, the positive pulse is generated at the output c of the third two-input AND circuit 17 only when the clock signals CK1 and CK2 both fall and the positive pulses are simultaneously generated at the outputs a and b.

On the other hand, the latch circuit 18 becomes through when the control signal is at a high level, and the data input terminal D
The clock selection signal SEL supplied to
Since the previous state is maintained when the level is low, the state of the clock selection signal SEL at the time when the clock signals CK1 and CK2 both fall at the output d of the latch circuit 18 and a positive pulse occurs at the output c. Will be transmitted,
The output c switches the clock signals CK1 and CK2.

According to this embodiment, the clock selection signal S
When EL changes from high level to low level, as shown in FIG. 4, the first and second 2-input AND circuits 1
Both outputs of 1 and 12 are at low level, but in this state, since both clock signals CK1 and CK2 are at low level, there is no influence on the output waveform. Even when the clock signals CK1 and CK2 are asynchronous, switching is performed by the clock selection signal SEL at the time when both of them become low level and the outputs a and b both become high level. The width is not disturbed.

It should be noted that the present invention is not limited to the above-described embodiments, and many variations and modifications are possible. For example, in the above-described embodiment, the inverting delay element and the NOR circuit are used for each clock signal to generate a positive pulse at the falling edge of the clock signal. However, the clock signal is inverted by the inverter circuit, The inverted output is supplied to one input terminal of the two-input AND circuit and is supplied to the other input terminal of the two-input AND circuit via an inverting delay element to generate a positive pulse synchronized with the falling edge of the clock signal. It can also be configured to generate.

[0015]

As described above, according to the present invention, the first
Since the switching of the second clock signal and the second clock signal are performed when the phases of both are the same and both are at a low level, generation of spikes in the output waveform and disturbance of the clock pulse width at the time of switching are effectively prevented. be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is a diagram showing a configuration of a conventional clock selection circuit.

FIG. 4 is a timing chart for explaining the operation of FIG.

FIG. 5 is a timing chart for explaining the operation of FIG.

[Description of Reference Signs] 11 first 2-input AND circuit 12 second 2-input AND circuit 13 first 2-input NOR circuit 14 first inverting delay element 15 second 2-input NOR circuit 16 second inverting delay Element 17 Third 2-input AND circuit 18 Latch circuit 19 Inverter circuit 20 2-input OR circuit

Claims (4)

[Claims] 1. A first pulse generation circuit for inputting a first clock signal and generating a pulse synchronized with its falling edge, and a second clock signal for inputting a second clock signal to generate a pulse synchronized with its falling edge. A second pulse generating circuit, a two-input AND circuit having the outputs of the first and second pulse generating circuits as inputs, and an output of the two-input AND circuit as a control input. A latch circuit that outputs a data input when the control input is at a high level and latches and outputs the data input when the control input is at a high level, using a clock selection signal for selecting a clock signal as a data input; First and second
And a selection circuit for selecting these clock signals based on the output of the latch circuit. 2. Each of the first and second pulse generation circuits has an inverting delay element and a 2-input NOR circuit,
The corresponding clock signal is supplied to one input terminal of the 2-input NOR circuit, and the 2-input N circuit is supplied through the inverting delay element.
The two-input NOR is supplied to the other input terminal of the OR circuit.
2. The clock selection circuit according to claim 1, wherein the circuit is configured to generate a pulse in synchronization with a falling edge of a corresponding clock signal. 3. The first and second pulse generating circuits each include an inverter circuit, an inverting delay element and a 2-input A.
It has an ND circuit, inverts a corresponding clock signal by an inverter circuit, supplies the inverted output to one input terminal of the 2-input AND circuit, and also supplies the other input terminal of the 2-input AND circuit via an inverting delay element. To the two inputs A
The clock selection circuit according to claim 1, wherein the ND circuit is configured to generate a pulse in synchronization with a falling edge of a corresponding clock signal. 4. The selection circuit has first and second 2-input AND circuits, a 2-input OR circuit, and an inverter circuit, and inputs the first clock signal to one input of the first 2-input AND circuit. The second clock signal is applied to the terminal
Of the two-input AND circuit, and the other input terminal of these first and second two-input AND circuits is supplied with the output of the latch circuit, one of which is supplied through an inverter circuit, First and second 2-input AND
The output of the circuit is supplied to the 2-input OR circuit, and the 2-input OR circuit is supplied.
4. The clock selection circuit according to claim 1, wherein the clock selection circuit is configured to obtain a selected clock signal from the circuit.