JPS59144248A - Cmi encoding and decoding circuit - Google Patents

Abstract

PURPOSE:To obtain a small-sized, inexpensive CMI encoding and decoding circuit to be operated at a high speed without any adjustment by composing all circuits of digital logical circuits which is operated by a clock signal in a CMI transmission period. CONSTITUTION:A CMI signal from a terminal 1 is inputted to a differentiation circuit 8, and the clock signal (c) for the CMI transmission period which synchronizes with a CMI input signal from a terminal 7 is inputted to the circuit 8, clock frequency dividing circuit 9, and a delay circuit 10. The circuit 9 inputs a frequency-divided clock signal (c') for an NRZ transmission period whose phase is determined by a signal (g) to the circuit 10. The circuit 10 delays the signal (c') by an integral multiple of the CMI transmission period and inputs the output signal c'' to a decoding circuit 11. The circuit 11 inputs the CMI signal and signals (c) and (c'') to generate the composite timing signal of the CMI signal, and the CMI input signal is converted by the timing signal into an NRZ code, which is outputted.

Description

TECHNICAL FIELD The present invention relates to a circuit for decoding a CMIM code input signal into a normal NRZ code signal.

CM I (Corded Mark Inversi)
on ) code is one of the transmission codes, and is a normal NR
“0” of Z code is converted to 2 bits of 01, and NRZ
The code '1' is a code that is sent alternately with 2 bits of 100'' or 11''. Therefore, the transmission period of 1 bit of the CM code is half the transmission period of 1 bit of the NRZ code. .This code should be a balanced code and timing extraction should be easy.

It is widely used because it can be created and decoded with a relatively simple circuit. In particular, when transmitting electrical or optical signals over long distances, the CMI code is considered advantageous because it is a balanced code and the amplification circuit of the receiving circuit can be simplified.

BACKGROUND OF THE INVENTION FIG. 1 is a block diagram showing an example of a conventional CMI code/decoding circuit. In other words, the CM input to input terminal 1
The received signal of the I code is input to one input of the exclusive NOR circuit 4, and the other input of the exclusive NOR circuit 4 is
A signal obtained by delaying the received signal by the ICMI transmission period by a delay circuit 3 is input. and said exclusive no.
The output of the R circuit 4 is input to the data output of the D type flip-flop 5. A clock signal having a repetition period (NRZ transmission period) equal to twice the CMI transmission period is input from the input terminal 2 to the clock signal C of the D-type flip-flop 5, and the data signal is input at each rising edge of the clock signal. The next state is set and output to the output terminal 6.

In the above decoding circuit, when the input signal is "01", the latter bit of the output (2 bits) of the exclusive NOR circuit 4 is "0", and the input signal is "00" or "11". In this case, the latter bits of the output of the exclusive NOR circuit 4 are all 'l'', so if the latter bits of the output of the exclusive NOR circuit 4 are set in the flip 70 knob 5 by the NRZ cycle clock, , 7 lip flops''
A code obtained by decoding the input CMI code into an NRZ code is output from the block 5. The distinction between the first half and the second half of a CMI input signal is that in the CMI code, a change from '1'' to *On occurs only at the beginning or end of a pair of 2 bits (sometimes it does not occur). This can be easily done by using the property that it does not occur between two bits.

In the conventional circuit described above, especially in the case of high-speed transmission, the delay circuit 3
The disadvantage of p1 is that it requires time adjustment using a delay line, as the precision of the delay time is strictly required.
Not suitable for integrated circuits. If a digital delay device operated by the CMI clock is used without using a delay line, two types of clocks are required for decoding, and the phases of the two types of clocks must be matched.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional drawbacks, and to provide a CMI code/decoder circuit that does not use a delay line, is entirely composed of digital logic circuits, does not require adjustment, and is suitable for integrated circuit implementation. Our goal is to provide the following.

Structure of the Invention The decoding circuit of the present invention is a CMI code decoding circuit that decodes a CMI input signal into an NRZ code.The decoding circuit receives a CMI input signal and detects a change point from 1" to "0" in the CMI input signal. A differentiating circuit that performs
The clock signal of the MI transmission period and the output of the differentiating circuit are input, and the phase is determined by the output of the differentiating circuit.
a clock frequency divider circuit that outputs a divided clock signal with an RZ transmission period; a delay circuit that delays the output of the clock frequency divider circuit by an integral multiple of the CMI transmission period; and a clock signal with the CMI input signal and CIVI I transmission period. and the output signal of the delay circuit, and the output signal of the delay circuit and the CM
The present invention is characterized in that it includes a decoding circuit that creates a timing signal for adjusting the CMI input signal using a clock signal having an I transmission period, and converts and outputs the CMI input signal into an NRZ code using the timing signal.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

That is, a differentiating circuit 8 receives the CMI input signal and detects that the CMI input signal changes from ``1'' to θ''.
The phase is determined by the output of the differentiating circuit 8, and the CMI
A clock frequency divider circuit 9 that frequency divides a clock signal with a CMI transmission cycle synchronized with an input signal, and a delay circuit 10 that delays the output of the clock frequency divider circuit 9 by an integral multiple of the CMI transmission cycle.
The output of the delay circuit 10, the CMI input signal, and the CMI transmission lock clock signal are input, and the clock signal of the CMI transmission period is decoded by passing through a gate that is opened and closed by the output of the delay circuit 10. The decoding circuit 11 generates a timing signal and converts an input CMI code into an NRZ code using the timing signal.

FIG. 3 is a block diagram showing a detailed configuration example of each part in FIG. 2. Differential circuit 8Vi, flip-flop 13.1
4 and a NAND circuit 16 which receives a signal obtained by inverting the output of the flip-flop 14 and the output of the flip-flop 13 by an inverter 5. A clock signal C having a CMI transmission cycle input from the terminal 7 is input to the clock terminal C of the flip-flops 13 and 14. The differentiating circuit 8id is a circuit that detects that the CMI input signal changes from 1'' to 0'' and outputs a low level for one clock period.

In other words, if the input signal becomes 1" then 0",
When the first '1' is set in the flip-flop 14 and the next '0' is set in the 7-lip-flop 13,
If the output of inverter 15 is abnormal, CXNAN
The two inputs of the D circuit 16 are both high level and NA
The output of the ND circuit 16 becomes a low level, and at the next clock, the output of the flip-flop 14 becomes a low level, and the output of the NAND circuit 16 becomes a NO level. The differentiator circuit may be a circuit (for example, a simple capacitor and rectifier) that generates a pulse at the 1" to 0" change point based on only the CMI input signal, without using a clock signal.

The frequency dividing circuit 9 inputs the output of the differentiating circuit 8 to one input of the AND circuit 17, connects the output of the AND circuit 17 to the D input of the flip-flop 18, and connects the output of the AND circuit 17 to the D input of the flip-flop 18.
The inverter 19 inverts the output of the AND circuit 1.
input to the other input of 7. A CMI cycle clock is input from the terminal 7 to the clock terminal C of the flip-flop 18. Therefore, when the output of the differentiating circuit 8 is at the NO level (normally), the frequency dividing circuit 9 operates as a 1/2 frequency dividing circuit of the input clock and outputs a frequency divided clock signal of the NRZ transmission period. Then, when the output of the differentiating circuit 8 becomes low level, the output of the AND circuit 17 becomes low level, the flip-flop 18 is set to θ'', and the inverter 19 outputs "1" for one clock period.
is output.

That is, by setting the flip 70 knob 18 to 0'' each time the CMI input code changes from 1 to 0, the phase of the frequency-divided output signal can be determined.

The delay circuit 10 is configured by, for example, a four-stage connection of flip-flops 20 to 23. This necessity will be discussed later.

The decoding circuit 11 includes a cascade circuit of flip-flops 24 and 25, an exclusive NOR circuit 26 inputting the outputs of the flip-flops 24 and 25, an inverter 29 for inverting the clock signal C, and the output of the inverter 29. An AND circuit 28 inputs the output of the delay circuit 10 to create and output a post-coding timing signal, and inputs the output of the exclusive NOR circuit 26 to a data manual, and outputs a post-coding timing signal from the AND circuit side. The CMI input signal is converted into an NRZ code by the output of the flip-flop 27, and the decoded signal is sent out from the terminal 6.Decoding In the circuit 11, the CM and I input signals are first set in the flip-flop 24, and 'ICMI
It is set in the flip-flop 25 with a delay in the transmission period.

The flip-flop 25 corresponds to the conventional delay circuit 3 shown in FIG. 1, and performs a delay operation with higher precision than a delay line with non-alignment. The clock signal C of the CMI transmission period whose polarity is inverted by the inverter 29 is sent to the delay circuit 10.
Out of the two pulses, 14β] is selected by the output of , and a timing signal C# for decoding is created. The timing signal σ" is supplied to the clock input terminal C of the flip-flop 27. This determines the timing for setting the output of the exclusive NOR circuit 26 to the 7-lip flop 27. The decoded code is output in the same way as in the conventional example explained in FIG.

Next, the operation of this embodiment will be explained. FIG. 4 is a time chart showing signals of various parts when a CMI input signal without code rule error 9 is input.

NRZ code “0” * Zllll” shown in Figure (a)
.

The CMI codes corresponding to ``1'' and ``1'' are shown in the same figure (b
) as shown in ``01'', ``01'', ``oo'', ``''1
1”.

It becomes “00”. The CMI code mentioned above is input from the input terminal 1, and a clock C having a CMI transmission cycle as shown in FIG. 3(c) is input from the input terminal 7. 3(d) shows the output signal of the flip-flop 13 (see FIG. 3);
) indicates the four-output signal of the flip-flop 14. Therefore, the output signal go of the differentiating circuit 8 is normally at a high level, but becomes a low level for one clock period only when the CMI code changes from 1'' to 'θ'' (see (g) in the figure).

During the period when the output current g of the differentiating circuit 8 is at a low level (the third
The output of the AND circuit 17 of the frequency divider circuit 9 (shown in the figure) becomes a low level, and the 7 lip-flop 18 is set to a low level at the rising edge of the next clock C (see Figure 4 (h)).
, the output of the inverter 19 becomes high level (Fig. 4 (
(see i)). Therefore, the rising edge of the inverter 19 is at the center position of the second half of the 2-bit pair of the input CMI code. Then, when the output C' of the inverter 19 becomes high level, one input of the AND circuit 17 becomes high level,
Thereafter, the high level from the differentiating circuit 8 causes AND circuit 1.
7 is at a high level, the output of the AND circuit 17 is set to the 7 rip 70 block 18 every time the clock C rises, and the inverted output of the inverter 19 is fed back to the input of the flip-flop 180 via the AND circuit 17. In particular, a frequency division operation is carried out. Therefore, the frequency divided clock C' output from the frequency dividing circuit 9 is as shown in FIG. 4(i).
This is a frequency-divided clock signal having a period twice that of clock C (NRZ transmission period) and whose phase is determined so that the rising time is at the center position of the second half bit of the 2-bit pair of the CMI input code. From this, the output signal CI of the delay circuit 1o is 4
Although the signals are output with a delay of the CMI transmission period, their phases are the same (see FIG. 4(j)). The inverted signal of the clock C and the above-mentioned frequency-divided clock C' are connected to the AND circuit 28 in FIG.
The output of the AND circuit 28 is the decoding timing signal CI of the NRZ transmission period as shown in FIG.
I&become.

On the other hand, since the CMI input signal is input to the decoding circuit 1 and is successively set to 7 ripples, 70 ripples, and 24.25 every time the clock C rises, the output of the exclusive NOR circuit 26 is as shown in FIG. 4(f). As shown, the latter bit of the 2-bit pair is a signal with the same logic level as the NRZ code, and is processed by the decoding timing signal σ' into 7 rip 70 amplifiers 27.
When set to , a code decoded into an NRZ code as shown in FIG. 4 C1) is output to the output terminal 6.

Next, the NRZ code "0" as shown in FIG. 5(a).

0'', ``0''l'1lZlt1'' is erroneously CMI-encoded, and the operation will be described when a CMI input code other than that shown in FIG. 3(b) is input. The figure shows an example in which the second bit 0' of the NRZ code is incorrectly input as a CMI code "10".

Note that (C) in the same figure shows the clock signal C of the CMI transmission cycle. When the above 0” error occurs, the CMI code becomes 1”
The change point 1. from 0'' to 0'' occurs in the middle of the 2-bit pair.Then, the output of the clip 70 tube 13. As shown in the same figure (g), the output signal g of the flip-flop 18 is an erroneous low-level signal with a phase shift of the ICMI transmission period compared to the normal case, and the output of the flip-flop 18 is As shown in (h), the level becomes low for an extra ICMI transmission period.Therefore, the multiphase, which goes high for an extra ICMI transmission period, is disturbed (the divided clock C'ldlCMI output from the inverter Ig). (see (i)).This erroneous branch clock signal C' is transmitted through the delay circuit 10,
An erroneous frequency-divided clock signal C' is output at a position delayed by 4 CM transmission periods (see FIG. 5(j)).

In other words, it is the CM that causes the error in the clock signal CI.
At the time when there is a delay of 4 CMI transmission cycles from the occurrence of the 'O' error in the I code, one extra pulse e is added to the decoding timing signal C# as shown in the same figure (b). Due to this extra pulse e, the output of the exclusive NOR circuit 26 as shown in FIG.
, and a decoded signal as shown in FIG. 4 (V) is output. The code set at this time is of course an error, but the time when the error occurs is delayed by 40 MI clock cycles from the occurrence of the '0' error in the CMI code, and before that, the CMI code including the '0' error is correctly decoded. be converted into

During this period, the code rule error detection circuit (not shown)
It is possible to discover errors in MI coding rules. Generally, a circuit for detecting an error in the CMI coding rule uses a clock signal with a period twice the CMI transmission period, so a clock signal with an NRZ period of correct phase is required for its operation. In this embodiment, even after an error occurs in the CMI coding rule, a divided clock signal with an NRZ period whose phase is not disturbed for 4 CMI transmission cycles is generated, so it is possible to reliably discover the error in the coding rule. . Various types of circuits can be considered as the CMI code rule error detection circuit, and the period required to detect a code rule error differs. Therefore, the delay time required of the delay circuit 10 differs depending on the period required by the detection circuit.

Effects of the Invention As described above, in the present invention, a clock with a CMI transmission period synchronized with a CMI input code is divided to generate a divided clock signal with an NRZ transmission period, and the phase of the divided clock signal is changed. , is determined by the output of a differentiating circuit that detects the point of change of the CMI input signal from 1'' to '0'', and is further delayed by an integral multiple of the CMI transmission period of the above-mentioned frequency-divided clock signal and a clock of the CMI transmission period. Create a decoding timing signal of the NRZ transmission cycle by the signal,
The CMI input signal is set to NR by the decoding timing signal.
Since the configuration is configured to convert and output to Z code, the entire circuit is C
It is possible to configure it with a digital logic circuit that operates according to a clock signal during MI transmission. As before,
There is no need for time adjustment using a delay line, and it is possible to provide a small, inexpensive decoding circuit that can operate at high speed without adjustment.

Furthermore, the frequency-divided clock signal output from the above-mentioned delay circuit is
Even if a code error occurs in the CMI code, the output phase is not disturbed until a certain delay time from the occurrence of the error, so that CMI code rule error detection can be reliably performed during this time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional CMI code decoding circuit, FIG. 2 is a block diagram showing an embodiment of the present invention,
FIG. 3 is a block diagram showing a detailed configuration example of each part of the above embodiment, FIG. 4 is a time chart explaining the decoding operation when there is no CMI coding rule error, and FIG. 5 is a block diagram showing a detailed configuration example of each part of the above embodiment. 3 is a time chart for explaining a decoding operation when there is a . In the figure, 1, 2.7...input terminal, 4.26...
・Exclusive NOR circuit, 5, 13, 14, 18.20-2
5.27...Flip-flop, 6...Output terminal,
8... Differential circuit, 9... Clock frequency divider circuit, 10.
...Delay circuit, 11...Decoding circuit, 15, 19.2
9... Inverter, 16... NAND circuit, 17.
28...AND circuit, C...CMI transmission cycle clock (No. 8, g...output signal of differential circuit, CI,
C#...divided clock signal, σ...decoding timing signal. Representative Patent Attorney Sumi 1) Toshi Sou Figure 1;; 2 Figure 1 Figure 4 (a) l 0 1 0 1 '1 1 1
1 1 1 mountain o o
11t multi ig 5 diagram

Claims (1)

[Claims] In the CMIM code decoding circuit that decodes the CMIM force signal into an NRZ code, a differentiation circuit that receives the CM input signal and detects the point of change from 11" to 00" in the CMIM power signal is synchronized with the CM input signal. a clock frequency dividing circuit that inputs a clock signal of a CMIM transmission period and an output of the differentiating circuit and outputs a divided clock signal of an NRZ transmission period whose phase is determined by the output of the differentiating circuit; a delay circuit that delays the output by an integral number of times the CMIM transmission period; inputting the CMIM power signal, a clock signal of the CMIM transmission period, and the output signal of the delay circuit; and inputting the output signal of the delay circuit and the clock of the CMIM transmission period; A decoding timing signal of the CMIM force signal is created by the signal, and a CMI input signal tNRZ is generated by the timing signal.
7) A CMIM code decoding circuit, characterized by comprising a decoding circuit that converts and outputs a code.