JP2754577B2 - Clock regeneration circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock reproducing circuit, and is suitably applied to, for example, a satellite broadcast receiving apparatus.

B. Summary of the Invention The present invention provides a clock reproduction circuit that latches input data at clock timing to form data delayed by a half cycle with respect to the input data.
As a whole, a highly accurate clock can be obtained with a simple configuration.

C Conventional Art Conventionally, in a signal processing circuit for satellite broadcasting or the like, a clock is reproduced from input data using a clock reproducing circuit proposed in, for example, Japanese Patent Laid-Open No. 52-38867, and the clock is reproduced. The input data is decoded based on the input data.

That is, in FIG. 5, 1 as a whole shows a clock reproduction circuit provides the input data D _I to the delay circuit 2 and the exclusive-OR circuit 3.

As shown in FIG. 6, the delay circuit 2 delays the input data D _I (FIG. 6 (A)) by a half cycle of the clock, and obtains the resulting delay data D _DI (FIG. 6 (B)). ) Is output to the exclusive OR circuit 3.

Thus, in the exclusive OR circuit 3, at a period of the clock to the input data D _I and the input data D _I
Only half period phase delay and delay data D _DI is input, by outputting the exclusive logical sum with a period of clock adapted to be transmitted is superimposed on the input data D _I, the logic level The edge data D _{E to be} switched (FIG. 6 (C)) is output.

Phase comparison circuit 4, together with the low-pass filter circuit 5 and the voltage-controlled oscillation circuit 6 is adapted to constitute a Hue over Zuro poke loop circuit, to obtain the Etsujideta D _E phase-synchronized with clock CK (FIG. 6 (D)) and Has been made.

That is, the phase comparator circuit 4, for example, exclusive-it consists of Shiv OR circuit, the exclusive OR voltage-controlled oscillator via a low-pass filter circuit 5 to the clock CK and Etsujideta D _E outputted from the voltage controlled oscillator 6 Output to the circuit 6.

Accordingly, when the phase of the clock CK is synchronized with the edge data _DE , an error signal S _ER (FIG. 6 (E)) having a duty ratio of 50% is output from the phase comparison circuit 4 and a low-pass filter is provided. A control signal having a signal level of 0 is output to the voltage-controlled oscillation circuit 6 via the circuit 5.

On the other hand, when the phase of the clock CK is advanced or delayed with respect to the edge data _DE , the error signal S _ER (FIG. 6) whose duty ratio changes according to the advanced phase and the delayed phase, respectively. (F) and (G)) are obtained, and the control signal whose signal level has changed from the 0 level to the negative side and the positive side is output to the voltage-controlled oscillation circuit 6.

Thus, based on the signal level of the control signal is controlled so that the phase of the clock CK is synchronized with the phase of Etsujideta D _E, thereby so as to reproduce the clock which is transmitted by being superimposed on the input data D _I It has been done.

D INVENTION point problem to be solved Meanwhile, in the clock regeneration circuit of this kind, because it is adapted to obtain a clock CK to the phase synchronized with Etsujideta D _E, in order to obtain a high accuracy clock CK is the phase of the input data D _I for Etsujideta D _E, certainly it is necessary to delay by 1/2 the period of the clock.

That is, when the phase relationship deviates from 1/2 cycle, deviation occurs in the phase of the clock with respect to that amount input data D _I.

However, since the delay circuit 2 uses a conventional integration circuit configuration using a capacitor and a resistor, a mono-multi circuit using the time constant of the capacitor, and the like, the capacitance of the capacitor due to a temperature change is used. not unavoidable to change the phase of Etsujideta D _E for this reason the input data D _I there is a problem that accompanied connexion variation to temperature changes.

Further, since a capacitor is used, this type of clock reproduction circuit has a problem that it is difficult to make adjustments and to form an integrated circuit.

The present invention has been made in view of the above points, and is intended to propose a clock reproducing circuit capable of solving these problems at once and obtaining a highly accurate clock with a simple configuration as a whole. is there.

In the present invention for solving means above problems to solve E problems, full of outputting the clock CK _S which delayed sub Lord clock CK _M and the main 90 degrees out of phase with the clock CK _M AES locked loop circuits 5, 14, 15, 16, 17, 18 and a first synchronous circuit
And the second input data D _II , D _QI
First and second latch circuits 11 and 12 latch in CK _S,
First and second output data D _DDI and D _DDQ corresponding to the first and second input data D _II and D _QI output from the first and second latch circuits 11 and 12, respectively, and the first and second input data D _DDI and D _DDQ . Input data D of 2
_II, D _QI third and fourth respectively the exclusive OR of the output data D _EI, first and second logic circuits 3I output as D _EQ, and 3Q, a third output data D _EI first Output data D of 4
_A third logic circuit 13 for outputting OR data with the _EQ as fifth output data _DEADD ; and a phase locked loop circuit 5, 14, 15, 16, 17, 18 for providing the fifth output data.
Based on the phase comparison of the D _EADD and Lord clock CK _M, primary and secondary of the clock CK _M, and outputs the CK _S.

F operation If the first and second input data D _II and D _QI are latched by the sub clock _{C S} with a 90 ° phase delay, the data D shifted in phase by a half cycle of the clock _{C M} with high accuracy. _DDI and D _DDQ can be obtained, thus the overall structure is simple and the first
And second input data D _II, D _QI the phase-synchronized with high precision clock CK _M, can be obtained CK _S.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

(G1) First Embodiment In FIG. 1 where parts corresponding to those in FIG. 5 are assigned the same reference numerals, reference numeral 10 denotes a clock reproduction circuit as a whole, which is composed of a four-phase PSK (phase shift keying) signal. Demodulates satellite broadcast signal and obtains I-phase and Q-phase input data
D _II and D _QI are applied to latch circuits 11 and 12, respectively.

As shown in FIG. 2, the latch circuits 11 and 12, the input data D _II and D _QI (FIG. 2 (A) and (B)) to the phase synchronization Lord clock which is formed by CK _M (FIG. 2 ( C)) for 90
Upon receiving the sub clock C _S (FIG. 2 (D)) having a phase delay phase, the input data D _II and D _QI are latched at the timing of the rise of the sub clock _{C S.}

Therefore, the input data D _II is supplied via the latch circuits 11 and 12.
It can be obtained mainly of clock CK _M cycle at half cycle delayed by the delay data D _DDI and D _DDQ (FIG. 2 (E) and (F)) and relative to D _QI.

In this way, the delay data D without using a capacitor, which is one half cycle delay period of the main of the clock CK _M
DDI and D _DDQ can be obtained with high accuracy.

Accordance connexion, by obtaining the main of clock CK _M on the basis of the input data D _II and D _QI and delay data D _DDI and D _DDQ, it is possible to obtain a high accuracy clock CK _M.

Furthermore, since it is possible to obtain a clock CK _M without using the capacitor, it is possible to obtain a suitable clock recovery circuit to no adjustment and integrated circuit.

That is, the exclusive OR circuits 3I and 3Q respectively include the delay data D _DDI and D _DDQ and the input data D _II and D _QI
And the exclusive-OR is added to the edge data D _EI and D
_It is output to the OR circuit 13 as _EQ (FIGS. 2 (G) and (H)).

Thus, the edge data D _EI and D
The OR data D _EADD (FIG. 2 (I)) of the _EQ is obtained. Even when only one of the input data D _II and D _QI is obtained, the OR data D _EADD is obtained from the remaining data.
_EADD has been made available.

Clock CK _M based on the slave connexion the OR data D _EADD
By obtaining even if only one of the data of the input data D _II or D _QI not being broadcast, reliably clock CK _M
Can be obtained.

When practice thus obtain clock CK _M from two input data D _II and D _QI, when the delay circuit so as to obtain delay data D _DDI and D _DDQ using a conventional capacitor as each input data The delay data D _DDI and D _DDQ for D _II and D _QI
There is a problem that it is difficult to completely match between D _DDI and D _DDQ .

However in this embodiment, high without using a capacitor, since it is possible to obtain a reliable Lord clock CK delay data D _DDI and D _DDQ only half period delayed by the period of _M, a correspondingly accurate clock it is possible to obtain the CK _M.

The buffer circuit 14 is composed of a three-state gate circuit that switches the operation state according to the logical level of the logical sum data _{DEADD. When} the logical level of the logical sum data _DEADD falls to logical "L", While the output terminal is floating, the input main clock CK is input when the logical level of the OR data _DEADD rises to logical "H".
_M is output as it is.

Accordance connexion, if clock CK _M to the logical OR data D _EADD are phase synchronized, and the period in which the logical level rises to a logic "H", a period in which the logic level falls to a logic "L" is equal error The signal S _ER (FIG. 2 (J)) is output from the buffer circuit 14.

On the other _hand , the clock C
When the phase of K _M is advanced and delayed, the period in which the logic level rises to logic “H” according to the advance phase and the delay phase, and the logic level becomes logic “L”, respectively.
An error signal S _ER whose period has changed has been obtained.

Thus, the clock reproducing circuit 10, and outputs the error signal S _ER via a low-pass filter circuit 5 to the voltage controlled oscillator 15, voltage controlled oscillator 15
A frequency dividing circuit 16 and a latch circuit of a predetermined dividing ratio
By feedback to the buffer circuit 14 through a 17, based on the DC level of the error signal S _ER, the input data D _II and
D _QI the clock CK _M is adapted to phase synchronization.

Latch 17 receives a reference signal consisting of four times the frequency of clock CK _M and CK _S is outputted from the frequency divider 16 with latch 18, the two 90 degree phase difference clock CK _M and CK _S
Is output.

Thus, the buffer circuit 14, the low-pass filter circuit 5, the voltage controlled oscillator 15, the frequency divider 16, the latch 17
And 18 constitute the Hue over Zuro poke loop circuit for outputting the primary and secondary of the clock CK _M and CK _S is phase-synchronized to the logical sum data D _EADD as a whole.

In the above configuration, the input data D _II and D _QI (FIGS. 2A and 2B) are supplied to the latch circuits 11 and 12 at the rising timing of the sub clock _{C S} (FIG. 2D). in the latch, the input data D _II and D _QI to the main of the clock CK _M period only half period delayed by the delay data D _DDI and D _DDQ (FIG. 2 (E) and (F)) is obtained Can be

The delay data D _DDI and D _DDQ respectively correspond to the input data D _II
And is input to the exclusive-OR circuits 3I and 3Q with D _QI Etsujideta D _EI and D _EQ (Fig. 2 (G) and (H)) is obtained, the via the OR circuit 13 Etsujideta D _EI and D The OR data D _{EADD of the EQ} (FIG. 2 (I)) is obtained.

OR data D _EADD is output to Hue over Zuro poke loop circuit, thereby the OR data D _EADD with respect to the input data D _II and Lord synchronized in phase D _QI clock CK _M (FIG. 2 ( C)) and vice of clock CK _S are obtained.

According to the above configuration, the input data D _II and D vice of clock CK _S becomes 90 degrees phase delay with respect to the main of the clock CK _M
By latches the _QI, can be obtained input data D _II and Lord clock CK period in half cycle only accurate delay data D _DDI and D _DDQ delayed of _M with respect to D _QI, thereby A highly accurate clock can be obtained with a simple configuration as a whole as compared with the related art.

(G2) Figure 3 a second embodiment, the reference signal S _REFZ made at twice the frequency instead of the reference signal formed at four times the frequency of the primary and secondary of the clock CK _M and CK _S, 90 degree phase Different primary and secondary clock CK _M
And it is obtained to obtain the CK _S.

That is, as shown in FIG. 4, the reference signal S _REFZ (fourth
(A) is applied to a latch circuit 21 via an inverting amplifier circuit 20 and directly to a latch circuit 22 so that the reference signal
Lord clock logic level is inverted at the logical level falling and rising timings of the S _REFZ CK _M and the third
Get the clock CK ₃ .

In this case, according to the initial state of the latch circuits 21 and 22,
Third clock CK ₃ phase with respect to the main of clock CK _M 90
For degree delay phase (FIG. 4 (B1) and (B2)), it may occur only phase difference main and third clock CK _M and CK ₃ are both 180 degrees relative thereto (Figure 4 (C1) and (C2)), when the main of clock CK _M relative to the third clock CK ₃ phases 90 degrees phase lead (Figure 4 (D1) and (D2)), a main and a third contrast If is clock CK _M and CK ₃ only occurs a phase difference both 180 degrees (FIG. 4 (E1) and (E2)) is four states is obtained.

In this embodiment, even from such four either state, in order to obtain the secondary of clock CK _S 90 ° phase delay with respect to the main of the clock CK _M, enter the main of clock CK _M in latch 23 third and latch at the timing when the clock CK ₃ rises, and outputs the output via a third exclusive OR circuit 24 together with the clock CK ₃ of Te.

Thus, it is possible to obtain a clock CK _S sub of the main of the clock CK _M against 90-degree phase delay through the exclusive OR circuit 24.

According to the configuration of FIG. 3, the primary and secondary clock CK _M and C
Even when a reference signal having a frequency twice as high as K _S is used, the main clock CK _M and the sub clock CK ₃ whose phase is delayed by 90 degrees with respect to the main clock CK _M can be obtained. A wide range clock recovery circuit can be obtained.

(G3) Another embodiment In the above embodiment, two input data D _II
And has been described the case of reproducing a clock from the D _QI, the present invention is not limited to this, when reproducing clock from one input data, or when reproducing a clock from three or more input data reversed widely applicable can do.

Further, in the above-described embodiment, the clock CK _{M is provided} by using a buffer circuit composed of a three-state gate circuit.
Although the case where the phase comparison is performed between the delay data and the delay data (D _DDI , D _DDQ ) has been described, the present invention is not limited to this, and various phase comparison means such as an exclusive OR circuit and a multiplication circuit can be widely applied. .

Further, in the above-described embodiment, the case where the present invention is applied to a satellite broadcast receiving apparatus has been described. However, the present invention is not limited to this, and may be widely applied to signal processing circuits of electronic devices such as compact disk players. Can be.

H Effect of the Invention As described above, according to the present invention, the main clock
By latching the first and second input data with the sub clock having a 90-degree delay phase, the delayed data is delayed from the first and second input data by a half cycle of the main clock cycle. Can be obtained with high accuracy, and a highly accurate clock phase-synchronized with the first and second input data can be obtained with a simpler configuration as a whole as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a clock reproducing circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining its operation, FIG. 3 is a block diagram showing a second embodiment, and FIG. FIG. 5 is a signal waveform diagram for explaining the operation, FIG. 5 is a block diagram showing a conventional clock reproducing circuit, and FIG. 6 is a signal waveform diagram for explaining the operation. 1, 10 clock recovery circuit, 2 delay circuit, 3, 3
I, 3Q, 24 ... Exclusive OR circuit, 11, 12, 1
7, 18, 21, 22, 24 ... Latch circuit.

Claims (1)

(57) [Claims] 1. A phase locked loop circuit for outputting a main clock and a sub clock delayed by 90 degrees in phase with respect to the main clock, and first and second input data synchronized with each other are supplied to the sub clock. First and second latch circuits latched by the clock of the first and second latch circuits output from the first and second latch circuits.
First and second output data corresponding to the exclusive OR of the first and second output data corresponding to the first and second input data and the first and second input data as third and fourth output data, respectively. A second logic circuit, and a third logic circuit for outputting a logical sum of the third output data and the fourth output data as fifth output data, wherein the phase locked loop circuit comprises: , The fifth
A clock reproducing circuit for outputting the main and sub clocks based on a comparison between the output data of the main clock and the phase of the main clock.