JPS5897116A - Improvement in floppy disc data separator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates generally to binary data processing, and more particularly to 70-tubi disks.

This relates to modified data and separators for using sources.

In the use of microprocessors and different types of digital processing equipment, clock and data information is typically applied to a controller that provides an interface between the data source and the computer or microprocessor. Operates as n
Ru. The controller also causes binary data from a data source, typically stored in serial format, such as a floppy disk, to be converted into parallel format for use by the computer. The output of a floppy disk is typically data, slot and clock. The slots are alternated to form a combined clock/data waveform containing both data and clock information. The clock signal occurs regularly in spaced intervals or line clocks or slots. A binary data signal is in the form of a logic butterfly 111 and 10'' signal, the former being determined by the presence of a pulse in the slot, which is usually data, and n1 which is usually data,
It is determined by the absence of a pulse signal within the slot. Separation of clock, data, and pulses is performed within the controller.

In one typical arrangement, the floppy disk data is fed directly to the controller and the data separator, and the floppy disk receives data from the disk and provides a derived clock;
;A bit slot for controller) t-determine. The most common analog phase-locked, looped data, separator is 7
The disk is coupled between the drive and the controller. In a different approach, the data separator is a 7-day disk.

The disk and data are received from the drive, and the raw data and reproduction-induced clock are supplied to the controller, and this clock is properly synchronized with the reproduction data. The data separator of this invention is directed toward this array of miscreants.

The controller has data separator from or floppy disk. In order to properly process data received directly from the drive, the data pulses must be identified within the controller as occurring within properly designated bit slots. That is, for data consisting of one logic 111 followed by one logic 111 and n followed by three logics 10@,
The controller calculates the first logic * @ 11 occurs, then data, 3 data without pulses, slot occurs, 1g2 logic 111 data, pulse follows 3 blank bit slots. <Must be able to accurately recognize the identity of the rod bit entering the slot.

Stated another way, the controller must be able to identify each data pulse that it receives as occurring within a proper data slot. Otherwise, the controller will cause incorrect operation based on the clock and data information received from the disk and drive.

For this reason, it is usually desirable to have the logic 111t-specifying data pulses occur as close as possible to the center of the slot in which they occur, so that the slot of the incorrect bit The probability of data associated with is reduced to essentially zero K. However, as a result of magnetic effects on the floppy disk and/or speed fluctuations of the motor driving the floppy disk, the position of the data pulse in the slot may be reduced. The pulse can occur to the extent that it occurs either at the beginning or at the end of the dedicated bit's slot. If this were to occur, the probability of data pulses being associated with incorrect data bit slots at the controller would be significantly increased.

Floppy, disk. Clock selected from source,
Several techniques are known for inferring data from pulses. One common technique is to be careful with your data.

Includes the use of analog phase locking loops using phase detectors and voltage controllers to determine the data and clock slots from the serial data stream selected from the source. ing. requiring externally adjustable components; and
There are several disadvantages to this technique, primarily due to the use of a relatively large number of parts. The former factor makes this circuit difficult to fully integrate and also increases circuit complexity and cost.

Different known techniques for deriving data pulses from a serial stream of data and clock pulses are monostable multivibrators to distinguish clock pulses from data pulses in a serial data/clock pulse stream. is to use. This technology is
For single-density data, modes in which locking pulses are distributed per clock slot, clocks generally yield satisfactory results.

For high-order or dual-density data modes in which pulses are placed only in two logic IQI data, clocks between slots, and within slots, the results are generally satisfactory. There will be no consequences. With this technology,
Also, accurate calibration of the pulse width is required to accurately derive the pulses from the data stream.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved data separator using digital techniques to derive precisely determined slots of bamboo bits.

A different purpose of this invention is data/clock.

The relative phase of the derived clock to the pulses in the stream of data is sensed and corrected so that the pulses are properly centered within the slots of bits. The purpose is to provide separators.

Another object of this invention is to eliminate data loss due to variations in floppy disk drive motor speed. data for use with the floppy, disk, drive, continuously sensing and adjusting for pulse frequency variations;
The purpose is to provide separators.

According to the invention, the guided clock pulses are generated by a phase-locked loop of a platform oscillator that includes an array of logic functions that perform the required algorithm. led n
The relative phase of the detected clock is adjusted or corrected in response to the sensed phase of the input data to position the data toward the center of its A-bit slot. Detection that the input data is far from the center of the dedicated bit slot causes the phase of the synthesis oscillator to be adjusted so that the center of the dedicated bit slot is closer to the input pulse. Become.

In two different aspects of the invention, a predetermined phase adjustment is made relative to the previous input, and the center frequency of the offlator is determined as a function of the severity, and n
n as a function of the rate of occurrence of the preceding phase corrections.

In order to fulfill the above-mentioned objects and objects apparent from the above-mentioned objects and objects, the following details, as substantially defined in the claims, and as discussed in the accompanying drawings are hereby incorporated into the present invention. Data that can be clarified with a detailed explanation. A separator is provided.

Referring to FIG. 1, on line 12 there is schematically shown a disk, a floppy disk, and a drive 10 for generating data. Disk,data typically contains both clock and data,pulses that alternate in μ-bit slots.
is a serial stream of binary data. Data is data, a pulse within a slot is represented by logic 111, and the absence of a pulse within a slot is represented by logic 101.

In Figure 2 4, during bit times b7 to 60, clock 0 and the strong bit of the plow, pulses occur alternately, two times and one time for a given data pattern (hex 17J11). An example waveform is shown. As shown in Fig. 2, in the type 1 waveform, the clock,
A pulse appears every slot of the dedicated bit of the clock, whereas in the dual WjQt waveform there are two pulses, as occurs in the slot of the dedicated bit of the data between bit times b3 and 62. clock only between consecutive logic "01" data slots.

Let n be such that the pulse appears in the slot of the clock, and the clock pulse appears in the slot of the first bit of the clock at bit time 62.

Data on line 12, stream is data.

When applied to the input of separator 14, the combined clock/data waveform of FIG. 2 or the disk derives a clock signal from the data and generates a recovered data signal along with the recovered clock. Synchronized re-clock and data, separator output from controller 1
6, the data is supplied to the nl, the slot is clocked, the slot is separated from the nl, and the data is separated from the computer.

A path 18 provides access to a data processing unit such as an i microprocessor. Since the separation of the clock and data information is accomplished within the controller 16, the term n/1 data applied to the unit 14, separator 1 is incorrect, but this technical term is not commonly used in industry. This term will be used throughout this specification because of the need for this term. This invention, described below, is based on novel data.

It is directed towards the separator.

Some currently used 70-tube disks. The relationship of clock waveforms to bit slots as required by the controller is shown in FIG. In this waveform, the end 9 of a slot for a given bit and the beginning 9 of the next slot are determined by the transition of the clock waveform.
Ru. Both forward and forward transitions are handled in the same way in the controller, and the fact that the clock waveform is high during one dedicated bit slot and low during the next A bit slot means that clock.

When distinguishing slots from all data, slots are not overlapping considerations. Thus, clock waveforms A and B in FIG. 3 are functionally the same.

The position of the data pulse in the data waveform is defined as its leading edge. Thus, as shown in the ideal data waveform of FIG. 3, the leading edge of each data pulse is centered at its dedicated bit slot and midway through the transition of the n1 clock waveform. When a data pulse is spread out and the clock waveform is transitioned between the pulses, the pulse is associated with the W bit slot containing the leading edge of the pulse.

However, in practical systems where data and clock signals are derived from floppy disks, ideal waveforms are not provided to the data separator. Rather, it's 70 tsubii.

As a result of magnetic effects on the disk and speed fluctuations of the disk, the data pulses are such that the pulse positions vary from the desired center of their associated bit slots. The data occurring in slots 2 and 6 of the n dedicated bits shown in the bottom waveform of A, may occur early or late within those A bit slots, as exemplified by the pulses. The derived clock should be such that it describes the A-bit slot as accurately as possible, and the position of the pulses should vary with the maximum margin and still be associated with the correct dedicated bit slot. According to the present invention, as described in more detail below, this is accomplished by aligning the phase of the derived clock to the data.

The average position of the pulse is such that it is in the center of the associated slot of A bits.

At this end, the data of the present invention includes a separator phase lock, a loose oscillator, and one cycle of which corresponds to one dedicated bit slot. As shown in FIG. 4, each oscillator cycle nominally consists of eight phase slices, which are also shown as phase memory values or eight in FIG.
ing. Data of this invention. At the separator, detection of an input pulse outside the center of its bit (i.e., other than phase slice 4t or 5) causes a phase correction to be added to the composite off-lator, redirecting the center of the slot of the dedicated bit to the data. , K to bring it close to the pulse. Fourth (α
) Referring to the figure, the input pulse A at slot IK is centered. That is, since 7n occurs within phase slice 4, no correction is made to this pulse. Input pulse B occurs early in slot 2 of the μ bit. That is, sort occurs within phase slice 2. When a position outside the center of the input pulse is detected, the slot of the first bit is shortened by one, effectively shifting the input pulse toward the center of the slot of the second bit. Slot 3 does not contain an input pulse t1, and no correction is made. The input pulse C in slot 4 is placed within that slot. That is, the nFi phase is caused by a phase squeeze. In this case, the slot is 1 extension 1 nl k nK
Now, try to bring the input pulse towards the center of slot 4 of its associated A bit.

Phase locking of the synthesized oscillator when no input pulse is detected. With the logic of the loop, every 8 phase slices,
Further, at the end of the advertisement slot, a slot end signal (FIG. 4(b)) is periodically generated. This signal determines the induced clock waveform and the duration of each dedicated bit slot. The occurrence of input detection during the bit slot is recalled and one of the slot end signals is used to regenerate the data waveform pulse. The relationship between the detected n1 reproduced pulses A, E and C is shown in Figures 4(a) and 4.
(-) As shown in the figure. The delay waveform at the end of the slot is used to toggle the regenerated clock (FIG. 4(d)) and the regenerated data. The pulses are preferably close to the center with respect to the recovered clock, for greater interchangeability with existing controllers.

The length of the slot is adjusted. That is, the previously sensed data, whether increased or decreased, and modified on the effective frequency of the synthesized oscillator by the detected data, pulses. The adjustments are made to maintain the desired relationship between the data and the output.

and phase locking of the synthesized oscillator to carry out the operations of n et al.
One example of a data separator that includes a loop is wIJ
This is schematically illustrated in FIG. As shown therein, the inverted disk data signal is applied to the input of a rearranger/synchronizer 2o, described in more detail below with respect to FIG. The delay timer/synchronizer 20 also performs phase slicing. The clocks φ and φ are received, and their frequency is, in this embodiment, the same as that of the strong bit slot, since each IA bit slot should nominally contain 8 slices. It is eight times the frequency of .

The D7 Allen 7A/Synchronizer 2o is a phase slice. The disk is synchronized with the clock, and together with the detection of the data signal, it generates a raw detection output of opposite polarity. Be sure to make sure you get inside. i.e. any disk, data. As a friend of the pulses, the raw detection signal produced by the distributor/synchronizer 2o is one that exists within one and only one phase slice.

The opposite polarity raw detection output of the decoder/synchronizer 20 is applied to one input of the detection memory 22, and is also as described later in this specification. The phase slice, clock and end of slot signal from logic function array (LFA) 24 is received. Detection memory 22 prevents one or more detection signals generated by arranger/synchronizer 20 from being recognized during any one slot to generate a detection signal; Applied to the logic function array 24 of the oscillator. The latter constitutes a phase-locked, looped or synthesized oscillator with a phase memory 26 that provides current phase data for LFAK.

As discussed in more detail below with respect to FIGS. 6 and 7, logic function array 24 executes a predetermined algorithm to adjust the phase value of the detected input signal with respect to the end-of-slot signal and to .

The pulses are centered within their associated bit slot. The end-of-cycle signal generated by LFA 24 is applied to an output waveform regenerator 28, which also receives an inverted sensed playback signal from sensed memory 22. Ksanru.

With respect to FIG.
) figure) and playback data waveform or output data pulse,
(FIG. 4(-)), which are temporally synchronized, but the slot end signal is delayed.

As noted, LFA 24 accepts the current phase signal from phase memory 26 and then supplies the next phase signal to the phase memory, according to the algorithm that Lf@LFA is designed to perform. , it is decided in LFA24. A phase memory 26 stores current phase data and divides the current phase signal into phase slices,
It is supplied to the LFAK which is synchronized with the clock.

The LFA 24 is 1 as shown in more detail in FIG.
Phase locking of the n-tension composite offlater shown for illustrative purposes in FIG. The algorithm is run in a loop. In addition to the logic for executing this algorithm illustrated in the LFA embodiment shown in FIG. 14, how many additional logic circuits can be used to execute the algorithm? Those skilled in the art may be aware that they may also be used. Thus, in addition to the n-type logic circuit shown in FIG.
PLA), read-only memory (ROM), look, up, table, or even random logic.

LFA also performs the desired algorithm,
Some logic combined in a known manner. It also consists of a gate.

Observing the truth table of the algorithm in FIG. 7, it can be seen that if there is no detection pulse from the detection memory 22, that is, the detection is 101, then the LFA 24 is executed and the new phase pitches are 0.1 and 2. The nth phase signal produced in the exemplary implementation or embodiment shown in FIG.
4 receives from phase memory 26 current phase value bit o
.

1 and 2 are also one phase higher. Thus, as seen in the truth table, for a phase value 2 where there is no detection, there is a new phase welfare 3. Similarly, for the phase value 4, the new phase for the detected signal is 5, and so on. As shown in FIG. 7, the slot end signal is not generated in the LFA 24 except when there is no detection signal at a phase value of 8. That is, when no detected data signal is present, a slot end signal is generated every %LFAFif3 phase switches when it receives a current phase value signal of phase 8. At the same time, LFA 24 generates a new phase 1, which is added to phase memory 26 to cause the cycle to repeat. On the other hand, when there is no detected data input, the LFA algorithm causes the synthesis oscillator to execute by generating the slot end signal K1 times every slot of dedicated bits.

r, pA2aybsf 7 When the detection data is input to the allen schitter/S/enchronizer 20 and the corresponding detection signal is received, one end is input to the current According to the phase, a different new phase is executed.

Thus, for example, if the detection signal appears in phase 1 and is directed toward the beginning of the slot, the LFA 24 will perform a new phase of phase 4 rather than phase 2, which is normal. This occurs when there is no early detection signal. This can be thought of as a two-slice or two-phase correction or adjustment.

Since the detected signal is no longer present in the subsequent phase slice, the LFA then executes the left-hand side of the algorithm of FIG. 7, causing a new phase 5 to be generated in response to acceptance of the current phase 4. In fact, phases 2 and 3 are removed so that the end-of-slot signal appears two slices earlier than that caused by the absence of the detection input in phase IK. This operation can be done by adjusting the data in the slot by the phase t-2 slices of the induced clock, or by adjusting the data in the slot by the phase t-2 slices of the induced clock, as described elsewhere. , press toward the center. If the detection signal occurs in either phase 2 or phase 3, then the LFA causes a new phase 4 or 5 to be generated, respectively, so that the end of slot signal is generated in the early part of the slot. K is set so that the detection signal occurs one slice earlier than if it were not present.

If the detection signal occurs in phase 4 or 5 corresponding to the center of the A-bit slot, then LFA#-1
New phases 5 and 6 are generated, where n is a phase value similar to the value it would have generated if the detection signal was not present. In this case, the slot end signal would be generated at its normal time, so there would be no corrections or adjustments to the slot end or derived clock.
This is because the data is already properly centered within its appropriate dedicated bit slot.

When the detection signal appears in slot 6 or 7, i.e. toward the end of the slot, the LFA:
new phase equal to the current phase, i.e. phase 6t respectively
7'j generates 7, K delays the slot end signal, n delays the slot end signal by one slice, and as before, n moves from the end of the slot to the center of the slot. If desired, the center of the detection signal is shifted, but this is done by effectively expanding the slot by one slice.

Finally, when the detection signal occurs at phase 8, i.e. at the end of the slot, the algorithm executed in LFA 24 makes the new phase phase 7, where rL is one phase less than the input phase. It is. This 1n causes a delay of two slices in the generation of the slot end signal and the guided clock. The LFA thus makes two slices of correction for the data detected at the end of the slot as it does for the detected signal at the beginning tr of the slot. After a long time,
In summary, if the detected signal occurs in phase slice 2.3.6 or 7, one slice's or one moderate correction is made; if the detected signal occurs in phase slice 1 or phase slice 8, is 1 severe 1t
or two slices of correction nl, and when the detection signal occurs in phase slice 4 or 5, no correction is made.

This algorithm implemented by LFA is represented in the table below.

Current phase [: 1 2 3 4 5 6 7 8
New phase value: 23456781 (no input detection) With input detection: +2+1+1 o o-1-1-
2-Phase Correction The variation in rotational speed in many floppies, disks, and drives is on the order of 2-degrees. If the data is recorded on a drive running 2% slower and played back on a drive running 2-faster, then the data. The data waveform is 4% faster than the nominal one. Similarly, the data waveform is 4% faster than the nominal one. Similarly, the data waveform is 4% faster than the nominal one.
The disc is 4% slower. It is necessary to process the data. In an additional aspect of the invention, center frequency corrections are made to the synthesized oscillator to compensate for these variations in average dedicated bit frequency.

At the end of this period, a simple history is maintained of the input pulse detections that have been phase corrected in the manner described above, centered around the data within the relevant time slot. Its history line, slot length and corresponding periodic adjustments are used to cause a subsequent phase correction to produce an upward or downward increase in the effective center frequency of the synthesized oscillator. .

The phase corrections made by detecting the deviation of the data input tV bits from the center of the slot, as described above, are classified into five types. That is, severe positive direction (+2 slices), moderate positive direction (+1 slice), meaningless (0
), moderate negative direction (-1 slice), and severe negative direction (-2 slice). According to the frequency correction algorithm implemented in LFA'l,4, the detection of three consecutive input pulses resulting in a modest positive phase correction, along with a third such detection, increases the frequency The request is sent to center frequency correction 30, and a single hard positive phase correction is made so that the frequency increase request is made by the LFA. Similarly, for three successive excessive negative phase corrections or one severe negative phase pull, a frequency reduction request is applied to the center frequency correction 30.

Phase correction memory 32 receives and stores phase correction history from LFA 24 in the form of a signal indicating the most recent phase correction made by the LFA. Phase correction memory 32
It also detects the clock.

A detection clock signal from gate 34 is received.

This gate receives the detection signal from the detection memory 22.
The detection signal is gated by a phase clock to generate a detection clock. The phase correction memory 32 provides the current phase correction (p, c, > history signal k, to the LFA 24, which applies the previous phase correction made by the LFAK. Based on these previous phase corrections, An increase/decrease frequency signal is generated by LFA 24 and, as noted, t'L#'i, is applied to center frequency correction 30. The latter also accepts an end of slot signal.

Briefly, as will be discussed in more detail below, the center frequency correction 30 counts the occurrences of the slot end signal received from the LFA 24 and performs a phase correction to cause the latter to generate a frequency increase/decrease signal. is performed in LFA 24, center frequency correction 3 (1), depending on the rate at which center frequency correction 30 is included and the number of frequency varying signals stored in memories 46 and 48. , 4 pieces, 6 pieces or 12 pieces
An adjustment signal for the next slot is generated for each slot of A bits. When the value of rate, memory is zero,
The adjustment signal of the next slot will not be output by the center frequency correction 30. The adjustment signal for the next slot is
In order for the frequency of the synthesized oscillator to correct or compensate for the previously sensed variation in the frequency of the average bit, whenever
1 slot for the beginning of the next slot, depending on whether it should be increased or decreased.
Modify the slot length of the next A bit by adding or removing one slot.

The next slot adjustment signal produced by the center frequency correction is also applied to the adjustment slot, memory 40, which also receives the clock from the termination clock, gate 42. , this is the terminal clock. It is generated in conjunction with the gating of the clock in phase by the slot end signal at gate 42. The adjustment slot memory 40 provides a signal to the LFA 24 that an adjustment slot is in progress each time each slot identifies that an adjustment slot is in progress, and also provides a signal to the LFA that the adjustment slot is in progress. Commands to modify the phase adjustment algorithm corresponding to the slot adjustment.

As described in more detail below, in the embodiment of the invention described herein, the rate of center frequency stopping,
The values in memory are 5 possible absolute values. 4,
3, 2, 1. Or it is 1 out of 00. Depending on the direction of the previous phase correction, i.e. up or down, the rate code memory in the center frequency correction 30 can be either positive or negative rate code for the stored rate, the value of the memory. reveal. Then, the positive rate code #i generates one code that shortens the first-order slot, and the negative rate code #i generates one code that expands the first-order slot. As noted above, when the rate and memory values are zero, the slot 1gj adjustment signal is not output. A signal to adjust the next slot is issued every 12/% slot n
This \Ic% is the rate stored in memory.
Estimate the absolute value. Thus, the 11th-nth order rate, which reflects both the number and severity of previous phase corrections,
Memory value l.

2.3. or for 4 slots) imie (next 7
The wound numbers are respectively 12, 6°4,
or once every three slots, causing a corresponding change in the period of those slots and in the frequency of the composite occlator.

For example, if the center frequency correction 30 shortens the primary slot to 1, the phase memory 26 may be preset to 2 instead of 1 as the slot ends. 1 to extend C1 as the slot ends.
The purpose is to preset the phase memory 26 to zero.

Since each slot of A bits nominally contains 8 phase slices, 12,6.4 . Or the adjustment of one phase slice for n slots generated in this manner every three slots, respectively, is the rate. (1/8)/12. for memory values 1, 2, 3 or 4. (1
/8)/e.

(1/8)/4, or (1/8), /3, or 1.2, 3. or 4%, to make a partial correction to the average dedicated bit slot frequency.

Adjustment slot memory 40 indicates to LFA 24 whether it is in a shortened, nominal, or expanded f'L9 slot row.

The phase correction and frequency correction algorithms are modified accordingly.
Ru. If no input pulse is detected, phase correction is performed.
Instead, the new phase value increases the current phase value by 1, as shown below, except at the end of the slot.

Current phase value: (112345670, 1, t or 28 New phase value: 12345678 The A phase value taken according to the slot end of phase 8, as shown here, is as required by the center frequency correction. 0.1. or 2, depending on the slot adjustment. When an input pulse is detected, one of the following phase corrections will be made if the slot is shortened, nominal, or stretched. It will be performed depending on whether it is in progress or not.

Current phase value: 0 1 2 3 4 5 6 7 8 pheasant compression slots.

Phase correction of +1+1+1 0 -1-1-
Phase correction of 1st nominal slot: +2+1+1 0 0 -1 -
1 -2 Phase correction of expansion slot; +2+1+1 0 0 0 -1 -1
-2 The classification of phase correction as severe, moderate, or insignificant also depends on whether a shortened, nominal, or extended slot is in progress. Sit down at the table below.

+8+1 indicates a severe positive correction, M+°
- indicates a moderate positive ((to that effect), 工 indicates that the meaning is υ57? or no correction, M- indicates a moderate negative, and the meaning is υ57?
indicates a severe negative correction. Phase correction can only occur when an input pulse is detected.

Current phase value: 012345678 Shortening slot correction: M+M+I I
I M-M - Nominal slot correction: S
-4-M+M+I I I M-M-8-I book slot correction: S+M+M+I I I I M-
M-P:-More specifically, in the center frequency correction 30 illustrated in FIG.
A gate 48 is included which outputs the increment, decrement and change signals of the LFA, the rate limit signal from the rate limit logic 50, and the one note code signal from the rate signal memory 48. The slice, along with the clock, gates these signals against a count of values stored in the rate amplitude memory 46 and increases, decreases or clears the rate in the rate sign memory 4.
The value t of the rate code stored in n - presses it to be updated.

rate, memory. The gated frequency increase/decrease signal from the clock gate 44 is applied to the rate amplitude memory 46 as either a right clock (up) or a left clock (down) shift signal. The count stored in 46 is raised and lowered. Rate limit logic 5
0 is rate, memory. clock. The next rate when a signal is provided to gate 44 that reveals that the count in rate amplitude memory 46 is zero.

The control input, whether n is a decreasing or increasing signal, causes an upward shift in memory 46 to cause the count in the rate amplitude memory to change from 0 to 1. The rate code memory 48 is connected to the memory 46
c) Depending on whether the frequency increasing or decreasing signal is received from the LFA, the KSIGN signal or : 5 IGN signal noise clearly increases.

As noted, in the embodiment of the invention described herein, a maximum value of 4 is imposed on the count of rate memory values stored in the rate amplitude memory 46. , n includes three stages of left shift/right shift registers as shown in FIG. The counts stored in the three stages of rate amplitude memory 46 are applied to rate limiting logic 50, which receives a maximum value signal (K) when the count in memory 46 is at its maximum count of 4.
, M A 5 values 0tl
=Sit3t and 4, a signal outside the range (outside K) is generated.

The limiting signal from rate limiting logic 50 is determined when the rate, memory, and clock are determined.

applied to gate 44. Reveals signals outside a certain range
It does not matter whether the frequency increase or decrease signal is clearly K, K clears the rate memory to zero, the zero clock or clear signal to the rate amplitude memory 46, the rate, memory. The clock is generated by the gate 44. K
The presence of the MAX signal prevents the next frequency increase or decrease signal applied to the rate memory clock gate from increasing the count stored in rate amplitude memory 46.

The counts stored in the rate amplitude memory 46 are applied to a four-stage presettable random, walk count memory 52, which receives the load from the counter, clock, gate 54, and clock signal. Acceptance can be made at any time. counter. On a different day, the gate 54 performs a shift with respect to the counting memory 52 for each slot as described below. Supply clock. Kara/ri. Gate 54 also outputs the code rate, KSIGN-* or KSIG from memory 48.
Similar to the rate code for perceiving the N signal, LFA2
4. Accepts the slot end signal and phase slice, clock from n. counter, clock, game) 54ij, ko\
The adjustment signal t-LFAVc for the next slot is provided at a rate determined by the count % stored in the rate amplitude memory 46 in the manner described above.

Please note that 1 is stored in the rate amplitude memory 46.
The out-of-count values are periodically transmitted to the count memo 1J52. Since the counting memory 52 uses a different code than the rate amplitude memory 46 to store specific values, non-counting values are converted upon transmission to the counting memory 52. Note that the count is based on the slot end signal and phase slice.

1 counter, clock, along with the gate action of the clock.
Once per slot from gate 54, the input signal is shifted, clocked, and decremented by the pulse. Counting memory 5
When the 4 bits in 2 are thus reduced to a predetermined value, such as 0001, the counting memory reveals a terminal counting signal to the counter, clock, gate 54;
and n, the latter reveals the load to the counting memory 52, the clock signal, and by n, the rate amplitude measurer 46
rate at. Memory value counting again counting memory 5
2. Once this count has been stored in the count memory 52, the end-of-count signal is no longer apparent and the count, clock, game) 54
Fi, shift at the end of each slot. The clock causes the pulses to be generated again to the counting memory, which causes the counting memory to decrement again through one defined cycle in each slot, so that the count in the counter 52 returns again to the end-of-counting state of 0001. At this time, the counting end signal is again clearly applied to the counter, clock, and gate.

The counting end signal is the counter clock. The latter is applied to gate 54 at a rate of 1 every n. The rate output adjusts or the next slot adjusts the signal at a rate that depends on the value in the memory. The adjustment signal for the next slot is LF once every 112/% slot as noted.
Let K make it clear to A. Here, 舊 is 4
, 3°2, or 1, and once every 3, 4, 6°, or 12 slots.

%1000, the KEQlf signal from rate limit lodge 50 to the counter, clock, gate inhibits the rate adjustment signal t-to clear.

j! 'tc s Depending on the rate code received by the counter, clock, gate from the rate code memory 48, the adjustment signal for the next slot is either to increase the slot length or to decrease the slot length.
There is a command for LFA241C.

Having thus explained the operation of the data, separators, and system of Figure 5, a more detailed description of the various parts of the seven stems shown in block form in Figure 5 is provided in Figures 9-15. , a block diagram of a rearranger/synchronizer 20 is shown, which can be synchronized to a phase clock, and can also accommodate phase slices, input discs that are not synchronized to a clock, and specific ends of a data signal. Generate an output raw detection signal.

The raw detection signal is clearly detected for each selected end of the input signal and lasts for one and only one phase clock.

As shown in FIG.
toggle. The output of the Fritz 1° block 56 is clocked by the phase slice, clock n3
Stage 77 is applied to the input of register 58. The signal is taft. As it propagates through the registers, a memory cycle occurs causing all but the last stage of the shift register to toggle. During this cycle, exclusive NOR gate 60 detects the difference between the final and next next shift register stages and produces an output for output flip flop 621C. This output is the raw detection signal of opposite polarity applied to the input of the detection memory 22, as shown in more detail in FIG.

As shown therein, the raw sense signal of opposite polarity from the differenciator/synchronizer 20 is applied to a NOR gate 64 which accepts a differential input from the output of the Fritz 1.70 tube 66. is applied. The flip, flop 66 is then manually operated by the NOR gate 6
Accepts the output of 8. It accepts at its inputs the slot end signal and the opposite polarity detection recall signal from the output of NOR game 70. The latter receives at its inputs the outputs of the 7-lip, flop 66 and NOR gate 64. The slot end signal, when present,
Discs that have been separated in any way. As for the data signal, flip, 70 knobs. Clear the memory 66. As noted earlier, the detection signal is applied to LFA24.
A detection recall signal of opposite polarity to the output waveform generator 28 is applied to the output waveform regeneration generator 28;
0 is shown in Figure 0.

As shown therein, a slot end signal is applied to the input of a three-stage shift register 72 clocked by a phase clock. Tufting from the input slot end signal by three phase slices. register 72
The output of is applied to an exclusive OR gate 74 whose output is applied to a 1-bit 7-lip, frog, memory 76. The output of the latter is coupled in feedback to the input of exclusive OR gate 74 in both its true and inverted form. The inverted output of the flip flop 76 is applied to the input of the output sofa, inverter 78.
Its output is the discrete clock shown in Figure 4(d).

The output waveform regeneration generator 28 is connected to one of the NOR gates 79.
A detection recall signal of opposite polarity from the human detection memory 22 is accepted as input. Another input to gate 78 is the inverted tLfc cycle end signal, and the output of gate 78 is the 1-bit flip, float 1 . Applying f-, nh, to the memory 80, gates the slot end 1i slice, delays the clock, and outputs its output signal to the second
The output buffer is applied to the inverter 82. The output of inverter 82 is the inverted and separated data signal shown in FIG.

As shown in FIG. 11, the phase memory 26 has seven registers. 70 Tsubu 84, 86, 88. and 90t-4-bit registers, each of which contains an LFA
It accepts one bit of the next phase signal from 24 and also accepts the phase clock from n. As it appears in the register,
The clocked 4-bit phase signal is 1 as described above.
It is applied to LFA 24 as the current phase signal.

The phase correction memory 32 includes a flip signal, as shown in detail in FIG. The first two bits, consisting of flops 92 and 94, shift. Register and flip. The second two bits consist of flops 96 and 98. 77th,
It contains registers. The two shift registers also have a detection clock, also shown in FIG.
A detection clock signal from gate 34 is received. 1st slot of phase correction memory 32, register f-4, LFA
24, when the negative correction signal of opposite polarity is received by the two disks ahead, the negative correction value associated with the data detection is recalled and the sexual storage is increased. In a similar manner, the second foot register stores n positive correction values associated with the detection of the previous two disc data, 1+. The outputs of flip-flops 92 and 94 are NOR gate 100 to LFA 24.
is applied to the input of NOR gate 100 along with the output of n. Similarly, the outputs of flips 96 and 98 are applied to the input of 1NOR gate 102 with the output of gate 102 being applied to LFA 24. The outputs of gates 100 and 1'02 and 7-lip, flops 92-98 constitute the current phase correction information provided to LFA 2 (by 1 phase correction signal 32 as described above). do.

As shown in the 18th vAK example, the adjustment slot.

The memory 40 receives the edge clock, also shown in FIG. Acceptance.

The opposite slot shortening and slot expanding signals are clearly K
1, which also accepts the end clock when n
1-bit flip, flop.

applied to memories 104 and 106.

7 rips, the true and inverted outputs of flops 104 and 106 (i.e., the expansion and contraction slots) are:
It is applied to the LFA 24 as an ongoing slot adjustment signal.

LF that performs the phase adjustment algorithm as described above.
The input and output NOR of A24 is LFAtlC
It is shown schematically in FIG. 14, along with all inputs and outputs for. 1- shown at the top of Figure 14
The resistor numbered 32 fits the load device of the input NOR gate; . The upper and lower parts of the LFA, input and output parts t, are separated by lsK.

In the upper or input part of the LFA, each circle appearing at the intersection of a vertical line and a horizontal line is roughly directed by a resistor flft, NOR in the upper part of the vertical line.
It represents the input of the gate. Thus, for example, an input phase signal represented by resistor 1 is received from phase memory 26 and applied to LFA 24. Similarly, the input NOR gate identified by resistor 26 has an inverted detect signal, an inverted bit 3
and accepts the current phase signal of inverted bit 0, the current phase signal of bit 2 and bit 1, and the inverted shortened slot signal.

All outputs of the 32 input NOR gates are connected to the 10 output NOR gates which are generally narrowed in the lower part of FIG.
Applied as input to R gate. The output NOR fitted by the 10 horizontal lines in the lower part of Figure 14
The input to the gate is also represented by a circle drawn at the intersection of the vertical line and the lower horizontal line. Thus, for example, the NOR gate represented by the second resistor from the top of the output NOR gate and producing the next phase signal of bit 3 has as input a 1.6-9.11
, 19, 20. and the output of the input NOR gate represented schematically by the resistors numbered 22-31 and the rate of 1 center frequency correction 30 as shown in FIG. 44 accepts the inverted increasing/decreasing frequency signal together with the inverted changing frequency signal.
However, this will become apparent when either the increasing or decreasing frequency signal is revealed. The rate memory rip gate also receives the rate code KSI from the root code memory 48 along with the KEQZ (count equal to zero) signal from the rate limit logic 50.
Accept GN (counts less than or equal to zero) and KSIGN (counts greater than or equal to zero). The rate code signal is applied to the inputs of NOR 110 and 112 through a series of switching FEs 1108 which, along with NOR gate 114, also accept the phase clock. NOR gate 110,
112 and 114 run the rate limiting logic 5
Accepts true and inverted signals for out-of-range counts from 0%, NO
R-gate 110 also accepts a KMAX (counting maximum) signal from rate limiter chic 50.

The signals generated by the rate, memory, clock, gate, i.e., right clock (rising), left clock (falling), or zero, clock (or clear) signals are applied to the rate amplitude memory 46. nru. This is similar stage 11
The circuit configuration includes a three-stage left shift/right shift/up/down counter consisting of stages 6, 118, and 120.
It is shown in n. The inverted output of stage 116 is the inverted output of stage 120.
and the inverted output of stage 120 is applied back to the inputs of stages 1-16.

The first bit of the count stored in stage 116 of rate amplitude memory 46 is applied to the inputs of NOR gates 25, 126 and 128 of rate limiting logic 50.

The second bit of the count in stage 118 of rate amplitude memory 46 is applied to the inputs of NOR gates 130 and 128 and the second bit is applied to the inputs of NOR gates 126 and 125. Rate width memory 46
At the rate n stored in stage 120, the third bit of the memory count is applied to the inputs of NOR gates 125 and 128, and its inverted form is applied to the inputs of NOR gates 130 and 126. Gates 130 and 1
The output of 25 is applied to the input of NOR gate 134, whose output is the inverse of the out-of-range count signal. NO
The output of R gate 126 is the KMAX signal. and,
This is the output FiKEQZ signal of NOR gate 128.

These signals include rate, memory,
A clock is applied to gate 44.

The KEQZ signal from gate 128 is also a rate, memory, clock, NOR signal contained within gate 44.
These gates are applied to the inputs of gates 36 and 138, each containing one stage of 7 circuits contained in root code memory 48, KSI from Flora 1140.
GN and 5: Accepts IGN signal. The latter is LF
A 24 receives the inverted down frequency signal and the right clock (rising) signal from the output of the clock (contained within gate 44) 110. The outputs of NOR gates 136 and 138 are KGTZ (count greater than zero) and KLTZ, respectively.
(count less than zero) signal, which is applied along with the KEQZ signal to the control input of switching FE 1108.

Stages 144-150 of counting memory 52 also contain a group of N
Contains OR gamers 56, 158, 160 and 162, the first two of which accept phase clocks.
counter, clock.

It receives gated pulses, slices, and clocks, including shift, clock, and load clock signals from gate 54. Gate 156 also receives the inverted slot end signal from LFA 24 and the count end 3 signal from count memory 52 and generates at its output a clock signal for the count memory. Gate 158 also receives an inverted slot end signal similar to the KEQZ signal and an inverted count end signal in inverter 164 to produce at its output a square clock signal for the counting memory. gate 16
0 is inverted by the inverter 142 from the rate sign memory 48 with the inverted r+-+ count end signal similar to the KEQZ signal, and the output Kf of the flop 140 is 7 rips;
Accepts IGN signal. Gate 162 is inverted f'L
, nine counting end I-go, KEQZ signal, and flip,
Accepts the KgIGN signal from the true output of flop 140.

The output of the NOR gate 15e is a shift clock signal which, when applied to the count memory IJ52, shifts the stage of the count memory by one count. gate 1
The output of 58 is a loading clock signal which, when present, causes the 3 bits from rate amplitude memory 46 to be loaded into the counting memory in conjunction with constant logic 111.

The outputs of NOR gates 160 and 162 are the primary slot shortening and stretching signals, respectively, and are inverted in inverters 166 and 168, respectively. These are the following slots) C! Il! The true and inverted versions of the adjustment signal are applied to LFA 24 and adjustment slot memory 40, as previously described.

The derived data and clock signals are provided for use by the controller in a manner that ensures a desired well-defined relationship between the data and the associated clock signal. It is clear from the foregoing description of the preferred embodiment of the invention. Data of this invention. The separator also monitors the most recent phase corrections made to the induced clock and makes corrections corresponding to the slot length and thus the data.

Means are included for making corrections to the effective wavenumber of the combined oscillator portion of the SEHA L/-.

It is understood that the invention has been described above in terms of a single embodiment thereof. However, it should be further understood that modifications to the disclosed embodiments may be made without departing from the spirit and scope of the invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram illustrating a typical application of the data separator of the present invention. Figure 2 shows floppy, disk, source power C:. FIG. 4 is a diagram of typical data, clock, and pulse waveforms. FIG. 3 is data and clock waveforms illustrating the relationship of clock waveforms to the A-bit slot required by a typical floppy, disk, and controller. FIG. 4 illustrates waveforms of signals used in data and separator operation of the present invention. FIG. 5 is a schematic block diagram of the data separator of the present invention. Figure 6 shows the data. FIG. 3 is a more detailed block diagram of the separator synthesis oscillator phase lock, loop. FIG. 7 is a representative internal algorithm implemented in phase locking loop 1 of the synthesized oscillator of FIG. FIG. 8 is a schematic diagram of the data of FIG. 5, a separator differential/synchronizer. FIG. 9 is a schematic diagram of the data of FIG. 5 and a separator detection memory. FIG. 10 is a schematic block diagram of the data separator output waveform generator of FIG. FIG. 11 is a schematic diagram of the data of FIG. 5 and the phase memory of the separator. FIG. 12 is a schematic diagram of the data, separator phase correction memory, detection clock, and gate of FIG. 5. FIG. 13 is a schematic diagram of the data, separator slot, memory and termination clock, and gate of FIG. 5; Figures 141 and 14B are the data from Figure 5. 1 is a schematic diagram of a logical functional array of separator tubes. FIG. 15 is a schematic diagram of the data in FIG. 5 and correction of the center frequency of the separator. 10+ floppies, disks, drives 14+ data,
Separator 161 Controller No. 20 Differentiator/Synchronizer 24 + Logic Function Array 30; Center Frequency Correction 22! Detection memory 261 phase memory

Claims (1)

[Claims] 1. Input data. a data separator for deriving data and clock signals from a source, said data separator including means for detecting an input data signal, and detecting the phase of the detected input signal with respect to the derived clock signal; means operatively coupled to said detection means for sensing, and said derived rt with sensing of a data signal displaced from the center of said slot relative to said derived clock signal; + logic means responsive to said sensing means to adjust the position of the clock signal so that the sensed data is closer to the center with respect to the slots; The above data is separated by a separator. The phase adjustment means is provided with a guided clock. 2. The data of claim 1, further comprising a synthesis oscillator that generates at a predetermined rate a slot end signal that determines the duration of the slot. Separator. 3. The data of claim 2, wherein said phase adjustment means includes an array of logic functions for executing a predetermined phase adjustment algorithm. Separator. Each clock slot is divided into a predetermined number of phase slices for each purpose n1 and the phase adjustment means has its associated n
clock. Means for adjusting the length of the clock slot by adding or subtracting a predetermined number of phase slices to the clock slot according to the sensed -rL displacement of the detected n-h data from the center of the slot. The data separator according to claim 3, comprising n. a means for sensing a predetermined magnitude of advance phase adjustment made by said phase adjustment means, and modifying the effective clock, slot frequency of said synthesized oscillator in response to said sensed count of advance phase adjustments; The data separator of claim 4, further comprising means for. 6. The data separator of claim 5, wherein said phase adjustment sensing means includes means responsive to both the number and magnitude of prior phase adjustments. 7. The phase adjustment means includes a relatively moderate positive or negative phase adjustment and a relatively severe positive or negative phase adjustment.
A strict phase adjustment means I! 1 with a predetermined number of occurrences of l or with a second larger predetermined number of occurrences of a moderate phase adjustment. Data in section 6. Separator. a The synthesis oscillator further stores current phase information, and converts the phase information into a phase slice. clock,
supplying the logic function array once per cycle;
5. The data of claim 4, wherein the data includes a phase memory for the data. means for separating and operatively coupled to said logic function array and said data detection means for generating all derived data and derived clocks with a predetermined phase with respect to an end of slot signal; 5. The data separator of claim 4 further comprising an output waveform regeneration generator. IQ The frequency correction means includes sensing:rL7' at a rate corresponding to the phase meter positive, means for storing a value in the memory, and means for storing the rate at which it is stored, a predetermined relationship to the value in the memory. 6. The data separator of claim 5, including means for adjusting to the frequency of the composite off-lator at a rate with n. IL The frequency modification means includes a first memory for storing the rate, a memory value, a second memory, the rate from the first memory. means for periodically loading values of a memory into said second memory, said counts in said second memory being periodically modified thereafter until the occurrence of a predetermined end-of-count signal; a second memory for generating a counting end signal in response to said correction means; It includes effective measures, etc.! Data for the 10th term in the desired range, separator. 12, a conditioning slot operatively coupled to the logic function play and frequency modifying means for providing a signal indicating that a conditioning slot to the logic function array is in progress; Furthermore, it includes
A data servitor according to claim 11. 1a further comprising a phase correction memory operatively coupled to the logic function array for providing a signal to the logic function array indicative of current phase correction history information. data, separator. 14. means for sensing a predetermined magnitude of the next phase vI4 adjustment made by said associated phase adjustment means;
2. The data of claim 1, further comprising means for modifying the effective locking, slot frequency of the composite off-lator in response to the sensed count of pre-phase adjustments. Separator. 1a Said phase 11! ll! 15. The data separation of claim 14, wherein the sensing means includes means responsive to both the number and magnitude of prior phase adjustments. 1G the phase adjustment means distinguish between a relatively moderate positive or negative phase adjustment and a relatively severe positive or negative phase adjustment, and with the occurrence of a first predetermined number of severe phase adjustment means; or means for causing a modification of the frequency of the sweet-acid offrator with a second, larger predetermined number of occurrences of moderate phase adjustment;
f Data and separator according to claim 15.