JP2002368611A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that eliminates changes in current, at a frequency lock due to the effect of phase comparison, to decrease the frequency lock time. SOLUTION: A phase comparator 1 compares the phase difference between an input signal and an oscillation clock from a voltage-controlled oscillator 6, provides an output of a phase comparison signal to drive a 1st constant current source 2, a frequency comparator 3 outputs a frequency comparison signal, depending on the frequency difference between the input signal and the oscillated clock signal, and the frequency comparison signal drives a 2nd constant current source 4. A filter 5 converts a current, outputted from the 1st and 2nd constant current sources 2, 4, into a voltage, which is fed to the voltage-controlled oscillator 6 as its input voltage. A frequency difference detection circuit 8 detects a frequency difference between the oscillated clock and the input signal and a drive control circuit 7 increases the ratio of an output of the 2nd constant current source 4 with respect to an output of the 1st constant current source 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CD player, C
D-ROM drive, DVD player, DVD-R
The present invention relates to a PLL circuit used in an optical disk reproducing device such as an OM drive device.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a configuration of a conventional PLL circuit. In FIG. 9, the phase comparator 1 has a function of comparing the phase of an input signal with the phase of an oscillation clock of a voltage-controlled oscillator (hereinafter, referred to as a VCO) 6. The first constant current source 2 is driven by outputs S1 and S2 of the phase comparator 1. The frequency comparator 3 has a function of comparing the frequency of the input signal with the frequency of the oscillation clock of the VCO 6. Second constant current source 4
Is driven by the outputs S3 and S4 of the frequency comparator 3.
The filter 5 has a function of integrating output currents of the first and second constant current sources 2 and 4 and performing current-voltage conversion. VCO
Reference numeral 6 has a function of generating a clock corresponding to the voltage VF of the filter 5.

The first current source 2 outputs a constant current to the outside in response to the output S1 of the phase comparator 1 and outputs the output S1.
In response to step 2, a constant current is allowed to flow from outside. Similarly, the second current source 4 causes a constant current to flow out in response to the output S3 of the frequency comparator 3, and causes a constant current to flow in from the outside in response to the output S4. The above operation of the current source is expressed as driving.

The PLL circuit composed of the above-described components operates as follows.

An input signal is a signal obtained by digitizing an analog signal read from an optical disk, and a PLL circuit generates a clock synchronized with the input signal. This clock is used to extract information recorded on the optical disk.

The phase comparator 1 compares the phase of the input signal with the phase of the oscillating clock of the VCO 6 and alternately generates outputs S1 and S2 as shown in FIG.
The constant current source 2 is intermittently driven, and the current IA shown in FIG.

[0007] In the frequency comparator 3, a specific pattern of an input signal (for T as a basic unit in a CD, 11
(A specific pattern of T + 11T exists)
The oscillation clock of CO6 is counted, and the input signal and VCO
6, the outputs S3 and S4 are generated as shown in FIG. 10 in accordance with the frequency difference of the oscillation clock, the second constant current source 4 is intermittently driven, and the current IB shown in FIG. Then, the capacitor in the filter 5 is charged or discharged.

The current IF obtained by combining the currents IA and IB of the first and second current sources 2 and 4 flows through the filter 5.

In FIG. 10, the vertical axis of the uppermost graph indicates the electric charge accumulated in the capacitor in the filter 5, that is, the voltage of the capacitor. The same applies to FIGS. 2 and 4 described below.

Therefore, when the frequency difference between the input signal and the oscillation clock of the VCO 6 is large, the frequency comparator 3 performs a frequency pull-in operation so that the oscillation clock has a target frequency. The phase comparator 1 performs a phase pull-in operation so that the input signal is synchronized with the input signal.

The first and the second driven in this manner.
Are integrated by the filter 5 and converted into a voltage VF. And VCO6
Generates a clock having a frequency corresponding to the voltage VF of the filter 5, and is used as a clock for extracting the recording information of the optical disk in a later stage (not shown).

[0012]

However, when the conventional PLL circuit is used, a difference occurs between the target frequency and the oscillation clock of the VCO 6, and when the frequency comparator 3 performs the frequency pull-in operation, There is a problem that it takes time for the PLL to pull in to the target frequency.

This is due to the influence of the phase pull-in operation during the frequency pull-in operation.

As shown in FIG. 10, the current IF charged / discharged to / from the filter 5 is a current obtained by adding the current IA due to the phase pulling to the current IB due to the frequency pulling. When the frequency difference between the input signal and the oscillation clock of the VCO 6 is large, the frequency pull-in is required more than the phase pull-in due to the phase difference.

However, the phase pull-in by the phase comparator 1 is performed irrespective of the frequency pull-in state. Therefore, the current IF charged / discharged to / from the filter 5 is obtained by superimposing the unnecessary current IA for phase pull on the current IB for frequency pull. as a result,
Depending on the output state of the current IA, the balance of the charge / discharge current of the current IF may be lost, and normal frequency pull-in may not be performed.

For example, in the example of FIG. 10, since the current IA due to the phase pull-in is partially weakened in the charging direction, when added to the current IB due to the frequency pull-in, the frequency of the oscillation clock of the VCO 6 is lower than the frequency of the input signal. In this case, although it is necessary to increase the voltage VF to increase the frequency of the oscillation clock, a normal charging charge current cannot be obtained as the current IF, and it takes time to obtain the frequency.

Accordingly, it is an object of the present invention to provide a PLL circuit which can eliminate a change in the amount of frequency pull-in current due to the influence of the phase comparison and can shorten the pull-in time.

[0018]

In order to solve this problem, a PLL circuit according to a first aspect of the present invention comprises a voltage-controlled oscillator for generating an oscillation clock corresponding to an input voltage, and a phase shifter between an input signal and the oscillation clock. A phase comparator for comparing phase differences and outputting a phase comparison signal; a first constant current source driven by the phase comparison signal; and a frequency comparison unit for outputting a frequency comparison signal according to a frequency difference between an input signal and an oscillation clock. A filter, a second constant current source driven by the frequency comparison signal, and a filter that converts currents output from the first and second constant current sources into a voltage and supplies the voltage as an input voltage of the voltage controlled oscillator, A frequency difference detection circuit for detecting a frequency difference between the frequency of the oscillation clock and the frequency of the input signal; and a first constant current source when the frequency difference detected by the frequency difference detection circuit is larger than a predetermined value. And a drive control circuit to increase the ratio of the output of the second constant current source to the output.

The above-mentioned drive control circuit stops the first constant current source, changes at least one of the first and second constant current sources, or changes the number of times of outputting the phase comparison signal. Alternatively, by changing at least one of the output width and the number of outputs of the frequency comparison signal, the first
It is preferable to control the output ratio between the constant current source and the second constant current source.

According to this configuration, when the frequency difference is larger than the predetermined value, the ratio of the output of the second constant current source to the output of the first constant current source is increased, so that the influence of the phase pull-in operation is small. , And the change in the amount of frequency pull-in current due to the influence of the phase comparison can be eliminated, and the pull-in time can be shortened.

Further, a PLL circuit according to a second aspect of the present invention includes a voltage controlled oscillator for generating an oscillation clock corresponding to an input voltage, and a phase for outputting a phase comparison signal by comparing a phase difference between the input signal and the oscillation clock. A comparator, a first constant current source driven by the phase comparison signal, a frequency comparator that outputs a frequency comparison signal in accordance with a frequency difference between the input signal and the oscillation clock, and a second comparator driven by the frequency comparison signal. Constant current source, a filter that converts currents output from the first and second constant current sources into a voltage and supplies the voltage as an input voltage of a voltage-controlled oscillator, and a phase comparator that counts the number of phase comparisons of a phase comparator When the number of phase comparisons counted by the number counting circuit and the number of phase comparison times counting circuit is larger than a predetermined value, the ratio of the output of the second constant current source to the output of the first constant current source is increased. That and a drive control circuit.

The above drive control circuit stops the first constant current source, changes at least one of the first and second constant current sources, or changes the number of times the phase comparison signal is output. Alternatively, by changing at least one of the output width and the number of outputs of the frequency comparison signal, the first
It is preferable to control the output ratio between the constant current source and the second constant current source.

According to this configuration, when the number of phase comparisons is larger than the predetermined value, the ratio of the output of the second constant current source to the output of the first constant current source is increased, so that the influence of the phase pull-in operation is small. The frequency pull-in can be performed in the state, the change in the frequency pull-in current amount due to the influence of the phase comparison can be eliminated, and the pull-in time can be shortened.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram showing a P according to a first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an LL circuit. In FIG. 1, a phase comparator 1 has a function of comparing the phase of an input signal with the phase of an oscillation clock of a VCO 6. The first constant current source 2 is driven by outputs S1 and S2 of the phase comparator 1. The frequency comparator 3 has a function of comparing the frequency of the input signal with the frequency of the oscillation clock of the VCO 6. The second constant current source 4 is driven by outputs S3 and S4 of the frequency comparator 3. Filter 5
Has a function of integrating the output currents of the first and second constant current sources 2 and 4 to perform current-voltage conversion. The VCO 6 has a function of generating a clock according to the voltage VF of the filter 5. The frequency difference detection circuit 8 has a function of detecting a frequency difference between the input signal and the oscillation clock of the VCO 6. When the frequency difference detected by the frequency difference detection circuit 8 is larger than a predetermined value, the drive control circuit 7
Has a function of controlling the drive timing of the outputs S1 and S2 of the phase comparator 1 so as to increase the ratio of the output of the second constant current source 4 to the output of the phase comparator 1.

The first current source 2 outputs a constant current to the outside in response to the output S1 of the phase comparator 1,
In response to step 2, a constant current is allowed to flow from outside. Similarly, the second current source 4 causes a constant current to flow out in response to the output S3 of the frequency comparator 3, and causes a constant current to flow in from the outside in response to the output S4. The above operation of the current source is expressed as driving.

The PLL circuit composed of the above-described components operates as follows.

The input signal is a signal obtained by converting an analog signal read from the optical disk into a digital (binary) signal by a data slice circuit (not shown) at a preceding stage. The present PLL circuit generates a clock synchronized with the input signal. This clock is used to extract information recorded on the optical disc at a later stage (not shown).

The phase comparator 1 compares the phase of the input signal with the phase of the oscillation clock of the VCO 6, and outputs the outputs S1 and S2 alternately as shown in FIG. The source 2 is intermittently driven and the current IA shown in FIG.

When the phase difference between the input signal and the oscillation clock is a desired value, the first constant current source 2 is driven so that the charging period by the current IA becomes equal to the discharging period, and the charge / discharge amount of the filter 5 is increased. Are equal, the voltage V of the filter 5
F does not change, and the frequency of the oscillation clock of the VCO 6 is kept constant. On the other hand, when the phase difference is not the desired phase difference, the first constant current source 2 is driven so that the ratio between the charging period and the discharging period by the current IA changes according to the phase difference, and the voltage VF of the filter 5 changes. As a result, the frequency of the oscillation clock of the VCO 6 rises or falls.

In the frequency comparator 3, when a specific pattern of an input signal (CD is T as a basic unit, 11
(A specific pattern of T + 11T exists)
The oscillation clock of CO6 is counted, and the input signal and VCO
6, the outputs S3 and S4 are output as shown in FIG. 2 according to the frequency difference of the oscillation clock, the second constant current source 4 is intermittently driven, and the current IB shown in FIG. Then, the capacitor in the filter 5 is charged or discharged.

When the number of oscillation clocks of the VCO 6 included in the specific pattern of 11T + 11T of the input signal is smaller than 22T, the second constant current source 4 is driven in the charging direction, and the voltage VF of the filter 5 increases. The frequency of the oscillation clock of the VCO 6 increases. On the other hand, the input signal 11T +
When the number of oscillation clocks of the VCO 6 included in the specific pattern of 11T is larger than 22T, the second constant current source 4
Is driven in the discharging direction, the voltage VF of the filter 5 decreases, and the frequency of the oscillation clock of the VCO 6 decreases.

Therefore, when starting or accessing, the PL
When L is out of synchronization and the frequency difference between the input signal and the oscillation clock of the VCO 6 does not match, the frequency comparator 3 performs a frequency pull-in operation so that the oscillation clock of the VCO 6 has a target frequency.

At this time, as shown in FIG. 2, the frequency comparator 3 sets the oscillation clock of the VCO 6 to a target frequency.
Drive outputs S3 and S4 are generated, and the second constant current source 4 is driven.

When the frequency difference between the frequency of the oscillation clock of the VCO 6 and the frequency of the input signal is larger than a predetermined value, it is necessary to mainly perform the frequency pull-in operation. The number of the driving outputs S1 and S2 generated from the phase comparator 1 by the thinning operation by the drive control circuit 7 operating in a reduced manner decreases, and the output of the first constant current source 2 decreases.

Thus, the charging / discharging current I to the filter 5
As F, the current IB for frequency pull-in becomes dominant and the influence of the current IA for phase pull-in decreases, so that the influence of the phase pull-in operation on the frequency pull-in operation can be reduced, and the frequency pull-in time can be shortened. .

When the frequency difference between the frequency of the oscillation clock of the VCO 6 and the frequency of the input signal is smaller than a predetermined value, the oscillation clock of the VCO 6 is set to the target frequency, and at the same time, the oscillation clock of the VCO 6 is The number of driving outputs S1 and S2 output from the phase comparator 1 for synchronizing the phases of the signals is reduced without decreasing the first number.
Is driven, thereby completing a series of pull-in operations.

As described above, in this embodiment, the frequency difference detection circuit 8 and the drive control circuit 7 which operates in accordance with the detection value of the frequency difference detection circuit 8 are added, and the frequency of the oscillation clock of the VCO 6 is reduced. During a period in which the frequency difference from the frequency of the input signal is larger than a predetermined value, the output S of the phase comparator 1
Since the number of outputs of S1 and S2 is reduced to reduce the current IA of phase pull-in, the influence of the amount of charge / discharge current due to the phase pull-in operation during frequency pull-in can be reduced, and the pull-in time can be reduced. it can.

In the first embodiment, the output S of the phase comparator 1 is changed according to the detection value of the frequency difference detection circuit 8.
1, the output ratio of the phase comparator 1 and the output ratio of the frequency comparator 3 are controlled by changing the number of outputs of S2.
Not limited to this. For example, the output ratio of the phase comparator 1 and the output ratio of the frequency comparator 3 are controlled by changing the output number or the output width of the outputs S3 and S4 of the frequency comparator 3 according to the detection value of the frequency difference detection circuit 8. There is no problem as a method to do it.

Further, in the first embodiment, the output S of the phase comparator 1 is changed according to the detection value of the frequency difference detection circuit 8.
1, the output ratio of the phase comparator 1 and the output ratio of the frequency comparator 3 are controlled by changing the number of outputs of S2.
Not limited to this. For example, by stopping the output of the phase comparator 1 according to the detection value of the frequency difference detection circuit 8,
A method of controlling the output ratio of the phase comparator 1 and the output of the frequency comparator 3 may be used.

In the first embodiment, the VCO
6, the difference between the frequency of the oscillation clock and the frequency of the input signal is compared with a predetermined value to control the number of outputs of the phase comparator 1 or the number of outputs of the frequency comparator 3 or the output width. However, it is not limited to this. For example, VCO
6, the frequency difference between the frequency of the oscillation clock and the frequency of the input signal is sequentially compared with a plurality of different values to control the number of outputs of the phase comparator 1 or the number of outputs of the frequency comparator 3 or the output width stepwise. There is no problem as a method to do it.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS.

FIG. 3 is a graph showing a P value according to the second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an LL circuit. In FIG. 3, 1 is a phase comparator, 3 is a frequency comparator, 4 is a second constant current source, 5 is a filter, 6 is a VCO, and 8 is a frequency difference detection circuit. It is the same as the form.

The difference from the first embodiment is that the first constant current source 2 is divided into two constant current sources 2A and 2B.
The drive control circuit 7 controls the magnitude of the current IA of the first constant current source 2 instead of controlling the number of outputs S1 and S2 of the phase comparator 1. The sum of the output currents IA1 and IA2 of the two constant current sources 2A and 2B is equal to the output current IA of the first constant current source 2 in the first embodiment.

The operation will be described below. The drive control circuit 7 changes the magnitude of the current IA of the first constant current source 2 according to the output of the frequency difference detection circuit 8. For example, FIG.
As shown in (1), when the frequency difference between the input signal and the oscillation clock of the VCO 6 is larger than a predetermined value, the current IA is changed from IA1 + IA2 to IA1 by stopping one constant current source 2B of the first constant current source 2. To decrease. Others are the same as FIG.

When the frequency difference between the frequency of the oscillation clock of the VCO 6 and the frequency of the input signal is larger than a predetermined value, it is necessary to mainly perform the frequency pull-in operation. By stopping one constant current source 2B of the first constant current source 2 by the drive control circuit 7, the current IA of the first constant current source 2 decreases. As a result, the charge / discharge current IF to / from the filter 5 is dominated by the current IB for frequency pull-in, and the influence of the current IA for phase pull-in is reduced. Therefore, the influence of the phase pull-in operation on the frequency pull-in operation can be reduced, and the frequency pull-in time can be shortened.

On the other hand, when the frequency difference between the frequency of the oscillation clock of the VCO 6 and the frequency of the input signal is smaller than a predetermined value, the oscillation clock of the VCO 6 is set to the target frequency, and In order to synchronize the phases of the signals, the first constant current source 2 is driven without decreasing the current amount IA of the first constant current source 2, thereby completing a series of pull-in operations.

As described above, in this embodiment, the first constant current source 2 including the two constant current sources 2A and 2B, the frequency difference detection circuit 8, and the operation according to the detection values of the frequency difference detection circuit 8 And the magnitude of the current IA of the first constant current source 2 is reduced during a period in which the frequency difference between the frequency of the oscillation clock of the VCO 6 and the frequency of the input signal is larger than a predetermined value. As a result, the influence of the amount of charge / discharge current due to the phase pull-in operation during frequency pull-in can be reduced, and the pull-in time can be shortened.

In the second embodiment, the second constant current source 2 is controlled according to the detection value of the frequency difference detection circuit 8.
Although one of the two constant current sources 2A and 2B is stopped to reduce the amount of current IA of the first constant current source 2, the method of reducing the amount of current of the constant current source 2 itself may be used. Absent.

In the second embodiment, the current of the first constant current source 2 is stopped by stopping one of the constant current sources 2A and 2B of the two constant current sources 2A and 2B. Although the method of reducing the IA is used, a method of reducing the amount of current of the first constant current source 2 by stopping an arbitrary constant current source of a plurality of constant current sources may be used.

In the second embodiment, the output of the phase comparator 1 and the output of the frequency comparator are reduced by reducing the current IA of the first constant current source 2 in accordance with the value detected by the frequency difference detection circuit 8. Although the method of controlling the output ratio is adopted, a method of controlling the output ratio of the phase comparator 1 and the output of the frequency comparator 3 by increasing the amount of current of the second constant current source 4 may be used.

In the second embodiment, the VCO
6 is a method of controlling the first constant current source 2 or the second constant current source 4 by comparing a frequency difference between the frequency of the oscillation clock and the frequency of the input signal with a predetermined value. Is compared with a plurality of values to determine whether the first constant current source 2 or the second constant current source 2
The constant current source 4 may be controlled stepwise.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS.

FIG. 5 is a diagram showing a P according to a third embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an LL circuit. In FIG. 5, 1 is a phase comparator, 2 is a first constant current source, 3 is a frequency comparator, 4 is a second constant current source, 5 is a filter, 6 is VC
O and 7 are drive control circuits, and the above configuration is the same as that of the first embodiment.

What is different from the first embodiment is not a frequency difference detection circuit, but a phase comparison frequency counting circuit 9 for counting the number of outputs S1 and S2 of the phase comparator 1 (phase comparison frequency). In the control circuit 7, when the number of phase comparisons counted by the phase comparison number counting circuit 9 is larger than a predetermined value, the ratio of the output of the second constant current source 4 to the output of the first constant current source 2 is increased. In this manner, the drive timing of the outputs S1 and S2 of the phase comparator 1 is controlled.

In this embodiment, the frequency ratio operation is mainly performed by switching the output ratio of the current source based on the number of phase comparisons.
The main operation of the frequency pull-in operation will be described below. That is, since the current is output by the phase comparator 1 every time the phase comparison is performed, if the number of phase comparisons is large, the influence of the output of the phase comparator 1 becomes larger than the output of the frequency comparator 3. It is. Therefore, when the number of phase comparisons is large, it is necessary to mainly perform the frequency pull-in operation.

The operation will be described below. In the phase comparison count circuit 9, the phase comparison output S of the phase comparator 1 is output.
1 and S2, that is, the number of phase comparisons is counted.
As shown in FIG. 6, when the number of phase comparisons is large, a signal is output to the drive control circuit 7 to reduce the number of outputs S1 and S2 of the phase comparator 1 by thinning. When the number of phase comparisons is small, the outputs S1 and S2 of the phase comparator 1 are output as they are. Regarding the outputs S3 and S4 of the frequency comparator 3, a normal frequency pull-in operation is performed regardless of the number of phase comparisons.

When the PLL is out of synchronization at the time of start-up or access, and the frequency difference between the input signal and the oscillation clock of the VCO 6 does not match, the frequency comparator 3 operates so that the oscillation clock has the desired frequency. Perform the pull-in operation. At this time, as shown in FIG. 6, drive signals S3 and S4 are output from the frequency comparator 3 so that the oscillation clock of the VCO 6 has a target frequency, and the second constant current source 4 is driven.

At this time, if the output of the phase comparison number counting circuit 9 for counting the number of phase comparison outputs (number of phase comparisons) from the phase comparator 1, that is, if the number of phase comparisons is larger than a predetermined value, the phase comparison number is counted. The drive signals S1 and S2 output from the phase comparator 1 are thinned out by the drive control circuit 7 operating in accordance with the circuit 9 to reduce the number of outputs, and the current IA of the first constant current source 2 decreases.

Thus, the charge / discharge current I to the filter 5
As F, the current IB for frequency pulling becomes dominant, and the influence of the current IA for phase pulling decreases. Therefore, the influence of the phase pull-in operation on the frequency pull-in operation can be reduced, and the frequency pull-in time can be shortened.

When the output of the phase comparison number counting circuit 9, that is, the number of phase comparisons is smaller than a predetermined value,
At the same time that the oscillation clock of the VCO 6 has the target frequency, the number of output of the drive signals S1 and S2 output from the phase comparator 1 for synchronizing the phase of the oscillation clock of the VCO 6 and the input signal is not changed. The first constant current source 2 is driven, thereby completing a series of pull-in operations.

As described above, according to the PLL circuit of this embodiment, the phase comparison number counting circuit 9 and the drive control circuit 7 operating according to the detection value of the phase comparison number counting circuit 9 are added. During a period in which the number of phase comparisons by the phase comparator 1 is larger than a predetermined value, the drive control circuit 7 reduces the number of outputs of the phase comparator 1 to reduce the current I
By reducing the output of A, the influence of the charge / discharge current amount due to the phase pull-in output at the time of frequency pull-in can be reduced, and the pull-in time can be shortened.

Even when the number of phase comparisons is large, it takes time to pull in the frequency because the phase pull-in influences the frequency pull-in. However, the third embodiment can reduce the frequency pull-in time.

In the third embodiment, the number of outputs S1 and S2 of the phase comparator 1 is changed according to the detection value of the phase comparison number counting circuit 9 to change the phase comparator 1
The output ratio of the frequency comparator 3 and the output ratio of the frequency comparator 3 are controlled, but the present invention is not limited to this. For example, the outputs S3 and S3 of the frequency comparator 3 according to the detection value of the phase comparison number counting circuit 9
By changing the number of outputs or the output width of the output 4, the output ratio of the phase comparator 1 to the output of the frequency comparator 3 may be controlled.

Also, in the third embodiment, the number of outputs S1 and S2 of the phase comparator 1 is changed according to the detection value of the phase comparison number counting circuit 9 so that the phase comparator 1
The output ratio of the frequency comparator 3 and the output ratio of the frequency comparator 3 are controlled, but the present invention is not limited to this. For example, a method of controlling the output ratio of the phase comparator 1 to the output of the frequency comparator 3 by stopping the output of the phase comparator 1 according to the detection value of the phase comparison number counting circuit 9 may be used.

Further, in the third embodiment, the number of outputs of the phase comparator 1 is compared with a predetermined value to compare the number of outputs of the outputs S1 and S2 with the number of outputs of the phase comparator 1 or the number of outputs of the frequency comparator 3. Alternatively, the output width is controlled, but the present invention is not limited to this. For example, the number of outputs of the outputs S1 and S2 of the phase comparator 1 is sequentially compared with a plurality of different values, and the phase comparator 1
The number of outputs or the number of outputs of the frequency comparator 3 or the output width may be controlled stepwise.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIGS.

FIG. 7 is a circuit diagram showing P according to the fourth embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an LL circuit. In FIG. 7, 1 is a phase comparator, 3 is a frequency comparator, 4 is a second constant current source, 5 is a filter, 6 is a VCO, 9 is a frequency comparison number counting circuit 9, and the above configuration is the third configuration. This is the same as the embodiment.

The difference from the third embodiment is that the first constant current source 2 is divided into two constant current sources 2A and 2B.
The drive control circuit 7 controls the magnitude of the current IA of the first constant current source 2 instead of controlling the number of outputs S1 and S2 of the phase comparator 1. The sum of the output currents IA1 and IA2 of the two constant current sources 2A and 2B is equal to the output current IA of the first constant current source 2 in the third embodiment.

The operation will be described below. The phase comparison counting circuit 9 counts the number of outputs S1 and S2 of the phase comparator 1. In addition, the drive control circuit 7 changes the magnitude of the current IA of the first constant current source 2 according to the output of the phase comparison count circuit 9. For example, as shown in FIG.
When the output of the phase comparison count circuit 9 is larger than the predetermined value, the current IA is reduced from IA1 + IA2 to IA1 by stopping one of the first constant current sources 2B. Others are the same as FIG.

When the PLL is out of synchronization at the time of startup or access, and the frequency difference between the input signal and the oscillation clock of the VCO 6 does not match, the frequency comparator 3 pulls in the frequency so that the oscillation clock has the desired frequency. Perform the operation. At this time, as shown in FIG. 8, driving outputs S3 and S4 are generated from the frequency comparator 3 so that the oscillation clock of the VCO 6 has a target frequency, and the second constant current source 4 is driven.

Here, if the output of the phase comparison number counting circuit 9 for counting the number of phase comparison outputs from the phase comparator 1 is larger than a predetermined value, the phase comparison number counting circuit 9
By stopping one constant current source 2B of the first constant current source 2 by the drive control circuit 7 operating according to the output of the first constant current source 2, the current IA of the first constant current source 2 decreases. As a result, the current IB for drawing the frequency becomes dominant in the charge / discharge current IF to the filter 5, and the influence of the current IA for drawing the phase is reduced.

On the other hand, when the output of the phase comparison number counting circuit 9 is smaller than the predetermined value, the oscillation clock of the VCO 6 is set to a target frequency and at the same time, the phase of the oscillation clock of the VCO 6 is synchronized with the phase of the input signal. First
The first constant current source 2 is driven without decreasing the current IA of the constant current source 2 to complete a series of pull-in operations.

As described above, according to the PLL circuit of this embodiment, the first constant current source 2 composed of the two constant current sources 2A and 2B, the phase comparison number counting circuit 9, and the phase comparison number counting circuit 9 And a drive control circuit 7 that operates in accordance with the detected value of, to reduce the amount of current of the first constant current source 2 during a period in which the number of phase comparisons by the phase comparator 1 is larger than a predetermined value. The influence of the amount of charge / discharge current due to the phase pull-in operation during frequency pull-in can be reduced, and the pull-in time can be shortened.

In the fourth embodiment, one of the two constant current sources 2A and 2B of the first constant current source 2 is stopped in accordance with the detection value of the phase comparison number counting circuit 9 to obtain the first constant current. Although the method of reducing the amount of current of the constant current source 2 is used, the method of reducing the amount of current of the constant current source 2 itself may be used.

In the fourth embodiment, the current IA of the first constant current source 2 is reduced by stopping one constant current source 2B of the constant current source 2 including the two constant current sources 2A and 2B. Although the method of reducing the current is used, a method of reducing the amount of current of the first constant current source 2 by stopping an arbitrary constant current source of a plurality of constant current sources may be used.

In the fourth embodiment, the output of the phase comparator 1 and the frequency comparator are reduced by reducing the amount of current of the first constant current source 2 in accordance with the detection value of the phase comparison number counting circuit 9. Although the method of controlling the output ratio of No. 3 was adopted,
A method of controlling the output ratio of the phase comparator 1 to the output of the frequency comparator 3 by increasing the current amount of the constant current source 4 may be used.

In the fourth embodiment, the number of outputs of the outputs S1 and S2 of the phase comparator 1 is compared with a predetermined value to control the first constant current source 2 or the second constant current source 4. However, the number of outputs of the outputs S1 and S2 of the phase comparator 1 is sequentially compared with a plurality of different values, and the first constant current source 2
Alternatively, the second constant current source 4 may be controlled stepwise.

In the first, second, third, and fourth embodiments, the second constant current source 4 is driven according to the frequency difference between the input signal and the oscillation clock of the VCO 6. The frequency comparator 3 uses 2T and 12T as input signals of a length that does not exist as information recorded on the optical disc.
The second constant current source 4 may be driven when T is detected.

[0080]

As described above, according to the PLL circuit of the first invention, the ratio of the output of the second constant current source to the output of the first constant current source when the frequency difference is larger than the predetermined value. Since it is made large, the frequency pull-in can be performed in a state where the influence of the phase pull-in operation is small, and the change in the frequency pull-in current amount due to the influence of the phase comparison can be eliminated, and the pull-in time can be shortened.

According to the PLL circuit of the second invention,
When the number of phase comparisons is larger than a predetermined value, the ratio of the output of the second constant current source to the output of the first constant current source is increased, so that the frequency pull-in can be performed with little influence of the phase pull-in operation. In addition, it is possible to eliminate a change in the amount of frequency pull-in current due to the influence of the phase comparison, thereby shortening the pull-in time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is an output timing diagram of a filter charging / discharging current according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a PLL circuit according to a second embodiment of the present invention.

FIG. 4 is an output timing diagram of a filter charging / discharging current according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a PLL circuit according to a third embodiment of the present invention.

FIG. 6 is an output timing diagram of a filter charging / discharging current according to a third embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a PLL circuit according to a fourth embodiment of the present invention.

FIG. 8 is an output timing diagram of a filter charging / discharging current according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 10 is an output timing diagram of a conventional filter charging / discharging current.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 phase comparator 2 first constant current source 3 frequency comparator 4 second constant current source 5 filter 6 VCO 7 drive control circuit 8 frequency difference detection circuit 9 phase comparison count circuit

Continuation of the front page F term (reference) 5D044 BC03 CC06 GM02 GM14 GM19 5J106 AA04 BB03 CC01 CC24 CC31 CC41 DD32 EE08 GG15 HH04 KK03

Claims (6)

[Claims] A voltage-controlled oscillator that generates an oscillation clock corresponding to an input voltage; a phase comparator that compares a phase difference between an input signal and the oscillation clock to output a phase comparison signal; A constant current source driven by a frequency comparator, a frequency comparator that outputs a frequency comparison signal in accordance with a frequency difference between the input signal and the oscillation clock, and a second constant current source that is driven by the frequency comparison signal A filter that converts currents output from the first and second constant current sources into a voltage and supplies the voltage as an input voltage of the voltage-controlled oscillator; and a frequency between the frequency of the oscillation clock and the frequency of the input signal. A frequency difference detection circuit for detecting a difference, and when the frequency difference detected by the frequency difference detection circuit is larger than a predetermined value, the frequency difference with respect to the output of the first constant current source And a drive control circuit for increasing the ratio of the outputs of the constant current sources. 2. A voltage-controlled oscillator for generating an oscillation clock corresponding to an input voltage, a phase comparator for comparing a phase difference between an input signal and the oscillation clock and outputting a phase comparison signal, and the phase comparison signal. A constant current source driven by a frequency comparator, a frequency comparator that outputs a frequency comparison signal in accordance with a frequency difference between the input signal and the oscillation clock, and a second constant current source that is driven by the frequency comparison signal A filter for converting a current output from the first and second constant current sources into a voltage and supplying the voltage as an input voltage of the voltage-controlled oscillator, and a phase comparison number for counting the number of phase comparisons of the phase comparator A counting circuit, wherein when the number of phase comparisons counted by the phase comparison number counting circuit is greater than a predetermined value, the output of the second constant current source with respect to the output of the first constant current source is output. A PLL circuit comprising a drive control circuit for increasing a ratio of force. 3. The drive control circuit controls the output ratio of the first constant current source and the second constant current source by stopping the first constant current source. 2. The PLL circuit according to 2. 4. The drive control circuit changes the amount of current of at least one of the first and second constant current sources,
3. The PLL according to claim 1, wherein an output ratio between the first constant current source and the second constant current source is controlled.
circuit. 5. The drive control circuit according to claim 1, wherein the drive control circuit controls the output ratio of the first constant current source and the second constant current source by changing the number of times of outputting the phase comparison signal. The PLL circuit as described in the above. 6. The drive control circuit controls at least one of an output width and an output frequency of the frequency comparison signal to control an output ratio between the first constant current source and the second constant current source. 3. The PLL circuit according to claim 1, wherein: