JPS60256988A - Digital type data separate circuit - Google Patents

Abstract

PURPOSE:To reduce the adjusting man-hour and to make the adjustment stable by providing a clock control circuit, clock generating circuit and a data detecting circuit and digitizing the said circuits. CONSTITUTION:The clock control circuit 1 starts the control of a state generating a clock in following to a read gate signal RG representing the state of data read. On the other hand, a detection signal DD1 for phase synchronism representing the detection of logical 1 in a read signal RD is transmitted to the circuit 1 from a data detection circuit 3, the circuit 1 compares the phase between a clock signal SEED and the signal DD1 transmitted from the clock generating circuit and generates a signal changing the clock frequency or following to the signal RD. A detection signal DET0 for frequency locking representing the detection of the synchronizing signal in the signal RD is transmitted to the circuit 1 from the circuit 3. After the frequency locking is taken by the signal DET0, the frequency synchronizing is locked once. On the other hand, the phase lock is conducted by using the detection signal DD1 representing the lead/lag correction of the phase. Thus, the adjustment using an externally mounted circuit is not required.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data separation circuit provided in a floppy disk controller (FDC) connected between a disk drive (FDD) and a computer (CPU). In particular, the present invention relates to digital data separation circuits. The read data read from the head of the FDD includes data bits, black bits, and qubits. The circuit that separates this signal and supplies it to the FDC is a data separation circuit, which generates a passive window and separates the data and clock. On the other hand, FM (frequency
cymodulatlon) method, MFM (mod
ff t@dfrequency rnodulato
n) method, etc., but in the case of the currently standard MFM method, an analog VFO data separator using a PLL circuit is often used as the data separation circuit. Analog type VFO data separator) circuit bar typically includes a phase detector, filter and a/f1 voltage controlled oscillator (
VCO) and an r-taseno frector. Read data (RD) from the FDD is input to the phase detector, passes through a filter and an amplifier, and is fed back from the vCO to the phase detector at the first stage, and at the same time is input to the data separator as a data window. RD is also input to the data separator and is separated into r-tough 4 pulses and clock/4' pulses by the data separator. According to this method, the phase difference between RD and the clock pulse generated by itself is compared, a voltage proportional to the deviation from RD is detected, and the delay or lead of the clock is adjusted by an oscillator that is controlled by this detected voltage. are doing. As described above, an analog type VFO data separation circuit uses a method in which the VCO of the iPLL circuit that generates black and white signals as a data window is controlled by an analog signal based on a detected voltage. [Problems to be Solved by the Invention] In the above-mentioned analog VFO circuit, the oscillator that generates the clock is largely controlled by the detection voltage, so it is necessary to fine-tune the model using external resistors and capacitors. This increases the number of parts, leading to an increase in parts costs, manufacturing costs, etc. Furthermore, when incorporating it into an FDC, there are many unstable factors such as power supply noise and crosstalk, which are difficult to overcome. [Means for Solving the Problems] The present invention provides a digital data separation circuit that solves the above problems. Detects frequency shift and phase difference based on
A clock control means that generates a signal indicating a delay or a lead in response to a frequency shift, and generates a plurality of count signals for performing a predetermined count in response to a phase difference; A clock that starts a binary counter to generate a read clock based on the output of a predetermined counter that is activated and the output of a master counter that is activated based on the signal indicating the delay or advance, and generates the seed clock and the second clock;
detects a frequency synchronization signal in the read data, detects the frequency synchronization signal that instructs correction of frequency deviation, detects rlJ in the read data, detects the phase difference with the read clock, This is achieved by a digital data separation circuit characterized in that it comprises a data detection means for generating the phase synchronization signal instructing correction. With this configuration, at the time of synchronization, the phase of the output clock is corrected by the input phase/4' pulse and the clock pulse, and the frequency of the output clock is changed, thereby quickly achieving synchronization. be able to. After synchronization, 1) predict the direction in which the peak foot of the next data will move based on the previous data, and correct the black and red phases accordingly. By using the above-mentioned digital method, there is no need for fine adjustment using external resistors and capacitors, thus reducing the number of adjustment steps, and eliminating the need for countermeasures against problems such as power supply noise and crosstalk, which eliminates the cine stability factor. . [Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows a digital data senor f rate circuit according to one embodiment of the present invention. 1 is a clock control circuit, 2
3 is a clock generation circuit, and 3 is a data detection circuit. In addition, RG is a read f-) signal, CK is a basic clock signal, RD is a fixed data signal, 5EED is a seed clock signal, UP is a countdown signal, DOWN is a countdown signal, and 11CNT. 21CNT and 16CNT are respectively 11 counts. 21 counts, 16 count signals, RCLK is a read clock signal, D O + DDt T I) IETo is a detect signal in each state. RG is clocked from the FDC, indicating that the FDC has entered the data read state. , is input to the control circuit 1. At this time, it is assumed that there is no frequency fluctuation and the frequency is fixed, and the clock control circuit 1 starts controlling the state of generating a clock in accordance with the RD. "1" inside
DD for phase synchronization, which indicates that `` has been detected, is sent to the control circuit 1, and the control circuit l compares the phase of the 5EED and DD sent from the black and white generation circuit 2 to the control circuit 1. A signal for changing the clock frequency or following RD is generated. The detection circuit 3 further sends DET o for frequency synchronization to the control circuit 1, which indicates that a sync byte signal, which is a synchronization signal in the RD, has been detected.
ETo stops the above-mentioned frequency fixing and starts frequency variation. CK is a basic clock signal supplied from a separately provided oscillator, and in this embodiment, it is 16M.
Hz, and is normally input at a cycle of about 1/32 of RCLK, that is, divided into 32 parts, and the delay and lead are adjusted in accordance with RD. The detection circuit 3 detects the RD input from the FDD, since the window is determined by the CK and the extent of the shear is determined, and sends it to the control circuit 1. As mentioned above
DDl sends the moment when RD is detected as "1" to the control circuit l, compares this moment with RCLK, and if the phase is earlier, it returns to the original state and changes the clock frequency to match RD. Instruct circuit l. As described above, the basic operation of the detection circuit 30 is to achieve frequency synchronization and phase synchronization with respect to the RD), and frequency synchronization is performed using the sync byte signal, which is a signal for frequency synchronization provided in the RD. DET indicates that a sync byte has been detected as described above.
This is done using o. After frequency synchronization is achieved by DET, frequency synchronization is temporarily performed using a lock signal (LOCK).
) to be shrunk. On the other hand, phase synchronization is RD's "l"
This is done using DDI which detects the deviation between the position of the rising edge 9 of RCLK and the center of RCLK and instructs to correct the delay or advance of the phase. The clock generation circuit 2 basically consists of a plurality of counters and generates ARCLK and S@ED. This is a basic clock, and when CK is input, it is determined that the counter has reached 0 and the clock is inverted. In other words, the pulse width is determined by the number of counts that the counter has, and when the 90K is operating at 16 MHz, 32 counts is 2 μtxec.In order to obtain multi-period wave number synchronization, synchronization is performed by changing to 31 or 33 counts. Take. Therefore, the control signals are UP and DO.
Frequency synchronization is obtained by this signal in the WN. On the other hand, phase synchronization is IICNT. This is done using 21 CNT and 16 CNT, and detects "1" in the RD input at the time of 16 counts, determines whether there is a delay or advance, temporarily stops a predetermined counter, and then starts a separate counter, such as a 16 counter. After starting the Yoshikant and counting out at 16 counts, the first 32
Initializing to the count state is well phase-locked. The above-mentioned operation will be explained in more detail with reference to FIG. 2 and the subsequent drawings. FIG. 2 is a detailed block diagram of the clock control circuit shown in FIG. 1. In FIG. 2, 11 is a phase difference detection force Kunta;
12 indicates a phase adjustment circuit. The phase difference detection counter 11 is for detecting the phase difference with RCLK. For example, in an ideal RCLK, R
The rising edge of D is located, but in reality, this rising edge does not coincide with the center position and lags or advances. That is, a phase difference is generated, detected, and output as an IMF or DOWN signal. Next, the phase adjustment circuit 12 is a circuit for returning the generated phase difference by 11 steps/t according to the delay or advance. Outputs 21 counts. As mentioned above, the frequency is determined by the count number, but the count number can be changed by UP or DOWN, and therefore the frequency can be changed. To change the phase, when you know how many counts the actual RCLK deviates from the ideal RCLK from the rising edge of RD's "1", subtract that number of counts and lower "1". It is controlled by DOWN as shown below. I CNT, 21CNT, 16CNT are a counter that counts 11 from the rising edge of "1", a counter that counts 21, and a counter that counts 16 (the third
(see figure) and the signal to start the signal, ideally 1
6 Synchronization is achieved by forcibly lowering rlJ using CNT, but in reality, the rise point of rlJ is not necessarily located at the ideal gateway or center of the gate, but may be at the front depending on the pattern. After a certain period of time, a so-called peak shift occurs. Therefore, 16CNT alone is not enough, and IIC
NT and 21CNT, but this is done by detecting peak shifts. Peak shift is RD
For example, if the data string is 10100, it is assumed to be shifted to the right by 1 at the beginning, and if the data string is 0 at the beginning, such as 00101, it is assumed to be shifted to the left.
1 CNT or 21 CNT is used. 16O mentioned above
NT is used when there is no peak shift and is used when applying sync synchronization, so the frequency and position,
Used to perform phase synchronization first. Further, Do indicates input data and is sequentially shifted from Do to D7, but only D. is actually used. Furthermore, LOCK is for fixing the frequency after frequency synchronization is completed.
and DOWN are stopped, and phase synchronization is then started. FIG. 3 is a detailed block diagram of the black and white generation circuit shown in FIG. 1. 21 is 11 counter, 22 is 21 counter,
23 is the 16 counter, 24 is the master counter, and 2
5 indicates a binary counter. RCLK is generated by the mask counter, but when data is input, one of them is activated by clock control, so the mask counter stops counting at that point, and one of the counters 21 to 23 is activated instead. Counting is started, and when, for example, 16 counts are completed, the data is lowered and 5EED is sent out. 5rED is fed to the control circuit 1, and at the same time it is input to the binary counter 2.
5 and performs the rising and falling of RCLK. FIG. 4 is a detailed block diagram of the data detection circuit shown in FIG. 1. 31 and 32 are Furi, Pflo, Zo circuit, 33
and 34 are shift registers, and 35 and 36 are one-piece multipisolators. Assume that RD is low active, that is, the low part is data, and it is inverted at the falling edge, and when RD is input, it is inverted. is entered into zo. This is detected by 5EED, and 5EED and 81 are input to CK in the shift register 33.
The correct data is input into the count register 34 by comparing the data input to the count register 34, and if the data is input, it is the same as the IED, and if the data is not input, it should be different. Therefore, “
1" is input, Do becomes 1, and this is further 5E.
Count by ED to obtain Do~D7. In this case, for example, if it is 01010101 or 10101010, this is a sink byte, so it is a 7'/yoto multi 35°36
DET o is output as a sync byte detection signal. Furthermore, by making the 8EEDQ period of the one-shot multi sufficiently large, the key JDET in which the sync byte continues due to the sync detection at the time of sync is not generated. 5 and 6 are timing charts showing the timing of phase synchronization and frequency synchronization. FIG. 5 is a timing chart of phase synchronization. As mentioned above, phase synchronization can be achieved by correcting the deviation of the actual cross-section from the ideal cross-section.
In the case of ONT, 11 counts start from count 5 in synchronization with the rising edge of RD, and when 16 counts are completed, IICNTO' indicating count out is generated, which causes 9
5EED occurs, 7'L11 count is reset,
This allows the falling edge of RCLK to be synchronized with the ideal clock.
In other words, it is synchronized with the start-up of RD. Thereafter, 21CNT and 16CNT are performed in the same manner, but as is clear, the count is 16. As the count reaches 21, the fall of RCLK becomes slower. FIG. 6 is a timing chart of frequency synchronization. In this case, as mentioned above, RD's NoJ? Turn is 10101
It is 010. On the other hand, if a deviation occurs between the ideal clock and the actual clock, for example, if it deviates forward, the actual clock will fall earlier than it should at 16 counts from the rising edge of R1). Therefore, the count is increased to 32.33 by the UP signal, and in the opposite case, the count is decreased to 31.30 by the DOWN signal. In this way, control is performed so that the count from the rising edge of RD (9) to the actual falling edge (black) of RD is always 16 counts. [Effects of the Invention] As explained above, according to the present invention, by digitizing it, it becomes possible to integrate it into an integrated circuit, and therefore it becomes possible to incorporate it into an FDC, thereby creating a small and low-cost FDC system. I can do it. Furthermore, it is also possible to increase the readability of FDD.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a digital data separation circuit as an embodiment of the present invention, Fig. 2 is a detailed diagram of the clock control circuit shown in Fig. 1, and Fig. 3 is the same as Fig. 1. 4 is a detailed block diagram of the data detection circuit shown in FIG. 1, FIG. 5 is a timing chart explaining phase synchronization, and FIG. 6 is a frequency diagram. It is a timing chart explaining synchronization. (Explanation of symbols) 1... Clock control circuit, 2... Clock generation circuit, 3... Data detection circuit, 11... Phase difference horizontal counter, 12... Phase difference adjustment circuit, 21... ...11 counter, 22...21 counter, 23...16 counter, 24...master counter, 25...binary counter, 31°32...flip flow, 76 circuit, 33.
34...Shift register, 35.36...One-shot multivibrator. Patent Applicant: Fujitsu Limited Patent Attorney: Akira Aoki, Patent Attorney: Kazuyuki Nishidate, Patent Attorney: 1) Yukio, Patent Attorney: Akiyuki Yamaguchi, Figure 1, Figure 5, Figure 16, Counter? 〉g 优〕〈) 口）gknee 〉3 possible〕く]F〉(!Fig. 6 5EED p--1-=--CNT2DZσf2overT DD, -11111 Choichi---1-up =--

Claims (1)

[Claims] 1. Detects frequency deviation and phase difference based on frequency synchronization signal, phase synchronization signal, basic clock, and seed clock, generates a signal indicating delay or lead in response to frequency deviation, and detects the phase difference. For this purpose, there is provided a clock control means for generating a plurality of count signals for carrying out predetermined counting, an output of a predetermined counter that is activated by the plurality of count signals, and a signal indicating the delay or advance. Based on the output of the activated master counter, a binary counter t-S is operated to generate a read clock, and a clock generation means for generating a clock signal and a frequency synchronization signal in the read data is detected and a frequency synchronization signal is detected. Data detection that detects "1" in the read data, detects the phase difference with the read clock, and generates the phase synchronization signal that instructs to correct the phase difference. A digital data seno 4 rate circuit comprising means.