JP3143913B2 - Data separator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data separator for generating a window signal for separating an external read data signal into a data pulse and a clock pulse.

[Prior art] Generally, in a FDC (floppy disk controller), a window signal that follows a frequency change of a read data signal in order to separate a read data signal of the MFM recording system sent from the FDD into a clock pulse and a data pulse. Requires a data separator for FDD that generates

This data separator generally generates a window signal using an analog VFO (variable frequency generator).
This analog VFO data separator is easily affected by the external environment such as the filter characteristics changing with temperature.
There are drawbacks such as the need for external components (resistors, capacitors).

Therefore, in recent years, digital VFOs composed only of logic circuits
Data separators are known.

As shown in FIG. 8, this type of data separator includes a phase comparison circuit 1, a bias generation circuit 2, a digital VFO 3, and a data separation circuit 4, and is used to generate a window signal that follows a frequency change of a read data signal. The phase comparison circuit 1 detects the phase difference between the center of the half cycle of the window signal and the read data signal as shown in FIG. 9, and changes the bias value of the bias generation circuit 2 with this phase difference.
The bias value controls the oscillation frequency of the digital VFO 3, and the output of the digital VFO 3 is fed back to the phase comparison circuit 1 as a window signal.

In the data separator configured as described above,
By controlling the oscillation frequency of the digital VFO3, an accurate window signal locked (synchronized) with the read data signal can be obtained.

By the way, in the format of the shift sector system generally used in FDD, as shown in FIG. 10, a sync (SYNC) is provided at the beginning of each of the ID field and the data field.
Since the sync field is composed of "00" data, the sync field is a pulse train of equal intervals (3.5 inch 2DD, 4 us in the MFM recording method). For this reason, the interference from the preceding and succeeding pulses becomes equal, and no "shift" called a peak shift occurs in the peak portion of the composite waveform. Therefore, if the pulse train of this sync field is clocked, lock-in is quickly performed, and an accurate window signal can be obtained.

[Problems to be Solved by the Invention] As described above, by locking the window signal to the pulse train of the sync field, the window signal can quickly follow the read data signal. Even high-speed follow-up was not expected.

It is considered that this is because the oscillation frequency of the digital VFO is controlled only by the phase difference between the read data signal and the window signal.

Therefore, if the oscillation frequency of the digital VFO can be controlled in consideration of the cycle of the read data signal in addition to the phase difference between the read data signal and the window signal in the period of the sync field of the read data signal, Obviously, high-speed tracking of the window signal is enabled.

An object of the present invention is to control the oscillation frequency of a digital VFO in consideration of the period of a read data signal in addition to the phase difference between the read data signal and the window signal during a sync field period of the read data signal. Is to do so.

[Means for Solving the Problems] The means of the present invention are as follows.

A data separator for generating a window signal for separating an external read data signal into a data pulse and a clock pulse, a cycle measuring circuit for measuring a cycle of the read data signal, and the read data signal for the window signal A phase detection circuit that detects whether the phase is the same phase, a leading phase, or a lagging phase; and if the leading phase or the lagging phase is detected by the phase detecting circuit, the leading or lagging amount of the phase A correction instruction circuit for instructing to correct the period of the found signal by a predetermined length without depending on the period of the read data signal measured by the period measurement circuit based on the correction instruction by the correction instruction circuit Signal generating circuit for generating a window signal having a cycle corrected by the predetermined length And characterized in that:

Embodiment An embodiment will be described below with reference to FIGS. 1 to 7.

FIG. 1 is a block diagram of an FDD data separator.

The FDD data separator has an oscillator 11, a synchronization circuit 12, a high-speed tracking circuit 13, and a data separation circuit 14,
The high-speed tracking circuit 13 includes a phase comparison circuit 13-1, a period measurement circuit 13
-2, bias value generation circuit 13-3, digital VFO 13-4
Is provided.

The oscillator 11 oscillates and outputs a 16 MHz basic clock signal CLK, and outputs a synchronization circuit 12, a phase comparison circuit 13-1, a period measurement circuit 13
-2, digital VFO 13-4, and data separation circuit 14.

A read data signal RD sent from the FDD is input to the synchronizing circuit 12, and the read data signal RD is synchronized with the basic clock signal CLK and one cycle of the basic clock (62.
Phase comparison circuit 1 as a pulse signal DATA with a width of 5 ns)
3-1, period measurement circuit 13-2, data separation circuit 14
Given to.

The phase comparison circuit 13-1 uses the pulse signal DATA and the digital signal
Compares the phase of the signal Q ₄ of the half cycle of the window signal WD output from VFO13-4, As a result, the pulse signal DAT
A, that is, when the read data signal RD has a lagging phase, outputs a low-level +/- signal, and when the read data signal RD has a leading phase, outputs a high-level +/- signal and outputs a bias value generating circuit.
13-3, and outputs an operation control signal ADCK to the bias value generation circuit 13-3.

The cycle measuring circuit 13-2 measures the cycle every time the pulse signal DATA is input, and determines a predetermined reference cycle (4u
s) is output as 5-bit data F0 to F4 with one cycle of the basic clock (62.5 ns) as a weight, and is supplied to the bias value generation circuit 13-3.

When the operation control signal ADKE is input from the phase comparison circuit 13-1, the bias value generation circuit 13-3 performs the phase comparison circuit 13-1.
The output data F0 to F4 of the period measurement circuit 13-2 are corrected according to the +/- signal from the controller and output as bias values D0 to D4,
Give to digital VFO13-4. In this case, when the +/- signal from the phase comparison circuit 13-1 is at a low level, the bias value generation circuit 13-3 outputs data F0 to F0 of the period measurement circuit 13-2.
"1" is added to F4, and when the +/- signal is at a high level, "1" is output from the output data F0 to F4 of the cycle measuring circuit 13-2.
Is subtracted to correct the data F0 to F4.

Digital VFO13-4 in the structure having a load with binary counter, etc., bit output of the 6-bit Q ₀ to Q ₅
Q ₅ is bias value D ₀ to D ₄ from the bias value generating circuit 13-3
Output as the frequency the window signal in response to, and the bit outputs Q ₄ are outputted as the signal half cycle of the Window signal (Window half cycle signal). Here, the window signal is applied to the data separation circuit 14 and the like, also the window half-period signal Q ₄ are synchronous circuit as a feedback signal
Sent to 12.

The data separation circuit 14 separates the pulse signal DATA from the synchronization circuit 12 into a data pulse DP and a clock pulse CP based on a window signal from the digital VFO 13-4.

Next, the operation of the present embodiment will be described with reference to FIGS.

Now, it is assumed that, of the read data signal RD sent from the FDD, a pulse train at an equal interval is sent within the period of the sync field.

In this case, the read data signal RD is synchronized with the basic clock signal CLK by the synchronization circuit 12, and as a pulse signal DATA having a width of one cycle of the basic clock, in addition to the data separation circuit 14, the phase comparison circuit 13-1, the cycle measurement circuit It is also sent to 13-2.

Then, the phase comparison circuit 13-1 operates as shown in the time chart of FIG.

Comparing the rise of the phase comparator 13-1 in the window half-period signal Q ₄ output from the rising and digital VFO13-4 of the pulse signal DATA, perform their phase comparison. As a result, as shown in FIG. 2A, the pulse signal DA
TA if (read data signal RD) is delayed phase with respect to the window half cycle signal Q _4, the phase comparator circuit 13 is synchronized to +/- signals on the detection to a low level, also the window half-period signal Q Outputs the one-shot pulse operation control signal ADCK in synchronization with the fall of ₄ .

Further, as shown in FIG. 2 B, and the pulse signal DATA is a phase lead with respect to the window half cycle signal Q _4, the phase comparator circuit 13 is synchronized to +/- signals on the detection and a high level, the outputs an operation control signal ADCK one-shot pulse in synchronism with the trailing edge of the window half cycle signal Q _4.

It is not obtained output of the operation control signal ADCK in the case where the phase of the pulse signal DATA and the window half-period signal Q ₄ are synchronized (see Fig. 2 C).

On the other hand, the cycle measuring circuit 13-2 operates as shown in the time chart of FIG.

Period measuring circuit 13-2 measures the period for each pulse signal DATA comes, outputs the data F ₀ to F ₄ to weight the basic clock one cycle the difference between the reference period. For example, when the measurement cycle is equal to the reference synchronization (reference cycle = 4 us), the cycle measurement circuit 13-2 sets “00H (hexadecimal notation,
Hereinafter the same). Also, as shown in FIG. 3B,
If the measurement cycle is larger than the basic cycle by one basic clock cycle (temperature cycle + 1 = 4us + 62.5ns), data F0 to F0
"01H" is output as 4. Conversely, as shown in FIG. 3C, when the measurement period is smaller than the reference period by one period of the basic clock (reference period -1 = 4 us-62.5 ns), "1FH" is output as data F0 to F4. I do.

FIG. 4 shows the relationship between the difference value with respect to the reference cycle and the data F0 to F4 output corresponding thereto, and the difference value "± 0"
The output states of the data F0 to F4 in the range from the difference value “−15” to “+15” are shown.

Thus, the bias value generation circuit 13-3 is a phase comparison circuit.
The output data F0 to F4 of the period measurement circuit 13-2 are corrected in accordance with the +/- signal from 13-1 and the operation control signal ADCK, and the values are used as bias values D0 to D4 for the digital VFO 13-.
Give to 4.

FIG. 5 is a time chart showing the operation of the bias value generating circuit 13-3.
Is output as an example. The data of "00H" is output from the cycle measuring circuit 13-2 when the measurement cycle is equal to the reference cycle, as described above.

First, the pulse signal DA with respect to the window half cycle signal Q ₄
When TA is a lag phase, +/- from the phase comparison circuit 13-1
Since the signal becomes low level and the operation control signal ADCK is output from the phase comparison circuit 13-1, the bias value generation circuit
13-3, as shown in FIG. 5A, the output value "00H" of the period measuring circuit 13-2 is increased by "+1" in response to the output timing of the operation control signal ADCK, and the value "01H" is set to the bias value D0. ~ D4
To the digital VFO 13-4.

The pulse signal DA with respect to the window half cycle signal Q ₄
When TA is the leading phase, +/- from the phase comparator 13-1
Since the signal becomes high level and the operation control signal ADCK is output from the phase comparison circuit 13-1, the bias value generation circuit
13-3, as shown in FIG. 5B, the output value "00H" of the cycle measuring circuit 13-2 is "-1" in response to the output timing of the operation control signal ADCK, and the value "FFH" is a bias value. D0-D4
To the digital VFO 13-4.

The pulse signal DA with respect to the window half cycle signal Q ₄
When the phases of TAs are synchronized, the output of the operation control signal ADCK cannot be obtained from the phase comparison circuit 13-1, so that the bias value generation circuit 13-3 is connected to the period measurement circuit 13 as shown in FIG.
The output value “00H” of −2 is directly applied to the digital VFO 13-4 as the bias values D0 to D4.

Thus, the digital VFO13-4 is generated a Window half-period signal Q ₄ together give generates a frequency Window signal corresponding to the data D0~D4 from the bias value generating circuit 13-3 to the data separation circuit 14, etc. Phase comparison circuit
13-1 as a feedback signal.

FIGS. 6 and 7 show "0000" as the bias values D0 to D4.
If 0 "as a reference value, indicates the output state of the window signal and the window half-period signal Q ₄ which changes according to which the amount of change, plus" 1 relative to Figure 6 the reference value is the amount of change in the bias value FIG. 7 shows a case where the amount of change in the bias value decreases by minus “1” with respect to the reference value.

Here, the reference period (4 us) of the window signal is equivalent to 64 clocks in terms of the basic clock signal CLK of 16 MHz.
Thus one cycle is 32 clock Window half cycle signal Q _4, 1/2 cycle thereof is corresponds to 16 clocks, the clock number of the window signal one cycle in accordance with a change amount with respect to the reference value of the bias value shown Increase or decrease as shown. On this occasion,
Digital VFO13-4 without substantially collapsing it a duty ratio of 50% of the window signal and the window half-period signal Q _4, the basic clock 1 with respect to the change amount of the bias value D0~D4
In the period of accuracy increasing or decreasing the period of the window signal and the window half-period signal Q ₄ (number of clocks).

As described above, the high-speed following circuit 13 repeats the above-described operation every cycle during the period of the sync field in the read data signal.

According to the present invention, when the cycle of the read data signal fluctuates, the cycle of the window signal can be adjusted to be close to the cycle of the read data signal immediately after the measurement of the read data signal. If the phase of the read data signal and that of the window signal are shifted, the window signal cycle is finely adjusted according to the specified length, and the window signal and the read signal are gradually read while keeping the frequency shift within a certain range. The phase with the data signal can be adjusted, and both high-speed followability and stability of the window signal can be achieved.

[Brief description of the drawings]

1 to 7 show an embodiment, FIG. 1 is a block diagram of an FDD data separator, and FIG.
FIG. 3 is a time chart for explaining the operation of the cycle measuring circuit 13-2, and FIG. 4 is a time chart for explaining the difference value with respect to the reference cycle and the output in the cycle measuring circuit 13-2. The figure which showed the relationship of data F0-F4, 5th
FIG. 6 is a time chart for explaining the operation of the bias value generating circuit 13-3. FIG. 6 is a diagram showing output states of a window signal and the like which change as the bias value increases with respect to the reference value. FIG. 7 is a diagram showing the output state of a window signal or the like which changes as the bias value decreases with respect to the reference value, and FIGS. 8 to 10 are diagrams for explaining the conventional example. FIG. 8 is a block diagram of a conventional FDD data separator, FIG. 9 is a diagram for explaining a phase difference between a read data signal and a window signal, and FIG.
The figure is a diagram for explaining a sync field. 11 ... oscillator, 12 ... synchronous circuit, 13 ... high-speed tracking circuit,
13-1: Phase comparison circuit, 13-2: Period measurement circuit, 13
-3: Bias value generation circuit, 13-4: Digital VF
O, 14 ... Data separation circuit.

Claims (1)

(57) [Claims] 1. A data separator for generating a window signal for separating an external read data signal into a data pulse and a clock pulse, comprising: a period measuring circuit for measuring a period of the read data signal; A phase detection circuit for detecting whether the phase of the read data signal is the same phase, a leading phase, or a lagging phase, and when the leading phase or the lagging phase is detected by the phase detecting circuit, A correction instruction circuit that issues an instruction to correct the period of the window signal by a predetermined length without depending on the advance amount or the delay amount; and a measurement performed by the period measurement circuit based on a correction instruction by the correction instruction circuit. A window for generating a window signal having a cycle obtained by correcting the cycle of the read data signal by the predetermined length A data separator, comprising: a signal generation circuit;