JP3194388B2 - Data separator for FDD - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FDD data separator for generating a window signal for separating a read data signal from an FDD (floppy disk device) into a data pulse and a clock pulse.

[0002]

2. Description of the Related Art Generally, in an FDC (Floppy Disk Controller), a window for following a frequency change of a read data signal in order to correctly separate a read data signal of the MFM recording system sent from the FDD into a clock pulse and a data pulse. It requires a data separator for FDD that generates a signal. This data separator generally generates a window signal using an analog VFO (variable frequency generator). However, the analog VFO data separator is easily affected by an external environment such as a change in filter characteristics depending on temperature. Resistance and capacitor). Therefore, in recent years, a digital VFO data separator composed of only a logic circuit has been known. As shown in FIG. 9, this type of data separator includes a phase comparison circuit 1, a bias generation circuit 2, a digital VFO 3, and a data separation circuit 4, and generates a window signal that follows a change in the frequency of a read data signal. As shown in FIG. 10, the phase comparison circuit 1 detects the center of the half cycle of the window signal and the phase of the read data signal, and changes the bias value of the bias generation circuit 2 based on the comparison result.
It has a PLL configuration that controls the oscillation frequency of O3 and feeds back the output of this digital VFO3 as a window signal to the phase comparison circuit 1. In the data separator configured as described above, by controlling the oscillation frequency of the digital VFO 3, an accurate window signal locked (synchronized) with the read data signal can be obtained. By the way, in the format of the shift selector system generally used in FDD, as shown in FIG. 11, a sync (SY) is placed at the head of the ID field and the data field, respectively.
NC) field, and the sync field is “0”.
Since it is composed of 0 "data, it is equally spaced (3.5 inch 2DD, 4u in the MFM recording method)
s). For this reason, the interference from the preceding and succeeding pulses becomes equal, and no "shift" called a peak shift occurs in the peak portion of the composite waveform. Therefore, by locking to the pulse train of the sync field, lock-in can be performed quickly, and an accurate window signal can be obtained.

[0003]

As described above, if the window signal is locked to the pulse train of the sync field,
Although it is possible to cause the window signal to quickly follow the read data signal, it has not been possible to expect even higher speed follow-up in the related art. Therefore,
The present applicant previously disclosed in Japanese Patent Application No. 2-246206 (Title of Invention: FDD data separator) a phase difference between a read data signal and a window signal during a sync field period of a read data signal. A technique for controlling the oscillation frequency of the digital VFO in consideration of the period of the read data signal and enabling high-speed tracking of the window signal was proposed. In this type, after quickly locking in to the sync pattern and obtaining an accurate window signal, the window signal for the read data signal is controlled so that only the periodic fluctuation due to the redundant rotation fluctuation element of the disk is followed. It is necessary to switch the tracking method.
An object of the present invention is to quickly lock in a sync pattern of a read data signal by switching a method of following a window signal with respect to a read data signal between a sync field detection of a read data signal and a data field detection of the read data signal. After obtaining the window signal, it is necessary to be able to follow only the redundant rotation fluctuation of the disk.

[0004]

The means of the present invention are as follows. (1) The digital VFO generates a window signal for separating the read data signal from the FDD into a data pulse and a clock pulse. (2) In the read data signal sent from the FDD, the phase comparison circuit
The phases of the read data signal and the window signal are compared. (3) In the period measurement circuit, in the period of the sync field of the read data signal sent from the FDD,
Measure the period of the read data signal. (4) The bias value generation circuit generates a bias value to be input to the digital VFO from output results of the phase comparison circuit and the cycle measurement circuit. In this case, the digital VF
The oscillation frequency of the window signal output from the digital VFO is controlled by changing the bias value input to O. Here, the bias value generation circuit corrects the output value of the period measurement circuit based on the comparison result of the phase comparison circuit, and the bias value generation circuit corrects the output value when the sync field of the read data signal is detected. A switching circuit for directly outputting the value as a bias value input to the digital VFO, and switching and outputting a value obtained by correcting a bias value at the time of sync field detection as a reference value at the time of data field detection, and a bias output from this switching circuit. A holding circuit that temporarily holds the value, and a second arithmetic circuit that corrects the bias value in the holding circuit based on the comparison result of the phase comparison circuit and uses the correction value as an input value of the switching circuit. Become.

[0005]

The operation of the means of the present invention is as follows. Now, during the sync field period of the read data signal of the MFM recording system sent from the FDD, the phase comparison circuit compares the phase of the read data from the FDD with the window signal, and the period measurement circuit reads the read data signal. Measure the period of the signal. In this case, the phase comparison and the cycle measurement are performed for each cycle of the window signal. Here, in the bias value generation circuit, the first arithmetic circuit corrects the output value of the cycle measurement circuit based on the comparison result of the phase comparison circuit. Then, the switching circuit outputs the value corrected by the first correction circuit. This output is temporarily held in the holding circuit and then input to the digital VFO. This controls the oscillation frequency of the window signal,
The window signal follows the read data signal at a high speed. On the other hand, in the bias value generation circuit,
When the data field is detected, the second arithmetic circuit corrects the bias value at the time of sync field detection held in the holding circuit based on the comparison result of the phase comparison circuit using the bias value as a reference value. The correction value output from the switching circuit is temporarily stored in the holding circuit and then input to the digital VFO. Thus, the oscillation frequency of the window signal is controlled, so that the window signal follows the read data signal at a low speed. Therefore, by switching the method of following the window signal to the read data signal between when the sync field of the read data signal is detected and when the data field is detected, the lock signal is quickly locked into the sync pattern of the read data signal, and an accurate window signal is obtained. After that, it can follow only the redundant rotation fluctuation of the disk.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below with reference to FIGS. FIG. 1 is a block diagram showing the entire configuration of the FDD data separator. The FDD data separator includes an oscillator 11, a synchronization circuit 12, a tracking control circuit 13, and a data separation circuit 14, and the tracking control circuit 13 includes a phase comparison circuit 13-1, a period measurement circuit 13-2, and a bias value generation circuit. 13-3 and a digital VFO 13-4. The bias value generation circuit 13-3
Denotes a phase correction circuit 13-11 and a frequency correction circuit 13-1
2, a selector 13-13, and a register 13-14. The oscillator 11 oscillates and outputs a 16 MHz basic clock signal CK, and outputs a synchronization circuit 12, a phase comparison circuit 13-1, a period measurement circuit 13-2, and a digital VFO1.
3-4.

[0007] A read data signal RD sent from the FDD is input to the synchronizing circuit 12, and the read data signal RD is synchronized with the basic clock signal CK and has a width corresponding to one period (62.5 ns) of the basic clock. Is given to the phase comparison circuit 13-1, the period measurement circuit 13-2, and the data separation circuit 14 as a read pulse DATA having

The phase comparison circuit 13-1 compares the phase of this read pulse DATA with the signal Q4 of a half cycle of the window signal WD output from the digital VFO 13-4, and as a result, the read pulse DATA, that is, the read data If the signal RD has a lagging phase or coincides in phase, a low-level sign signal +/- is output,
In the case of the advanced phase, a high-level sign signal +/- is output and supplied to the bias value generation circuit 13-3, and the arithmetic control signal ADCK is output to output the bias value generation circuit 13-.
Give to 3.

The period measuring circuit 13-2 has a read pulse DA
Each time a TA is input, its period is measured, and a difference value from a predetermined reference period (4 μs) is calculated as the basic clock 1.
5-bit data F0 having a period (62.5 ns) as a weight
To F4, and is supplied to the bias value generation circuit 13-3.

Next, in the bias value generation circuit 13-3, the code signal + /
− Indicates the phase correction circuit 13-11 and the frequency correction circuit 13-1
2 given. Here, the phase correction circuit 13-11 corrects the output data F0 to F4 of the period measurement circuit 13-2 according to the code signal +/− from the phase comparison circuit 13-1, and
The bit data Q0 to Q4 are provided to the selector 13-13. In this case, the phase correction circuit 13-11 adds "1" to the output data F0 to F4 of the period measurement circuit 13-2 when the code signal +/- from the phase comparison circuit 13-1 is at a low level, and When the sign signal +/- is at the high level, the data F0 to F4 are corrected by subtracting "1" from the output data F0 to F4 of the cycle measuring circuit 13-2. Further, the frequency correction circuit 13-12 includes a phase comparison circuit 13-1.
The input data D0 to D7 from the registers 13-14 are corrected in accordance with the sign signal +/- from the
To S4 are given to the selector 13-13. In this case, like the phase correction circuit 13-11, the frequency correction circuit 13-12 adds "1" to the input data D0 to D7 when the code signal +/- from the phase comparison circuit 13-1 is at a low level. And
When the sign signal +/- is at a high level, the input data D0
By subtracting "1" from ~ D7, the data D0 ~
D7 is corrected.

The selector 13-13 includes a frequency correction circuit 13
-12 and the phase correction circuit 13
-11 to selectively output the input data B0 to B7 from the floppy disk controller (FD).
C) is input as a select signal, and when the external control signal C is at a high level, the input data A0 to A7 from the frequency correction circuit 13-12 are output, and the external control signal C is When the signal is at the low level, the input data B0 to B7 from the phase correction circuit 13-11 are output. The external control signal C is a signal that goes low when a sync field of the read data signal is detected and goes high when a data field is detected.

The register 13-14 has a selector 13-13.
The output data X0 to X7 from the selector 13-13 are temporarily stored in accordance with the operation control signal ADCK from the phase comparison circuit 13-1.
7, that is, input data D0 to C to the registers 13 to 14
Hold 7. The data Q0 to Q7 held in the registers 13-14 are input to the frequency correction circuit 13-12, corrected, and given to the registers 13-14.

The digital VFO 13-4 has a configuration including a binary counter with a load, etc.
Bit output Q5 among 0 to Q7 is a bias value generation circuit 1
The signal is output as a window signal of a frequency corresponding to the bias value from 3-3, and the bit output Q4 is output as a signal of a half cycle of the window signal (window half cycle signal). Here, the window signal is a data separation circuit 1
4 and the like, and the window half-period signal Q4 is sent to the phase comparison circuit 13-1 as a feedback signal.

The data separating circuit 14 converts the read pulse DATA from the synchronizing circuit 12 into a digital VFO1.
Data pulse D based on the window signal from 3-4
P and a clock pulse CP.

Next, the operation of this embodiment will be described with reference to FIGS. First, the read data signal RD is synchronized with the basic clock signal CK by the synchronizing circuit 12, and as a pulse signal DATA having a width of one cycle of the basic clock, in addition to the data separating circuit 14, the phase comparing circuit 13-1,
It is sent to the period measurement circuit 13-2. Then, the phase comparison circuit 13-1 operates as shown in the time chart of FIG.

The phase comparator 13-1 compares the rising of the pulse signal DATA with the rising of the window half-period signal Q4 output from the digital VFO 13-4, and compares their phases. As a result, as shown in FIG. 2A, the pulse signal DATA (read data signal RD)
Is delayed with respect to the window half-period signal Q4,
The phase comparison circuit 13-1 synchronizes with the detection and outputs the code signal +
/-Is set to low level, and the window half-period signal Q4
Outputs a one-shot pulse operation control signal ADCK in synchronization with the falling edge of the signal. Further, as shown in FIG. 2B, when the pulse signal DATA has a leading phase with respect to the window half cycle signal Q4, the phase comparison circuit 13-1 sets the code signal +/- to a high level in synchronization with the detection, and A one-shot pulse operation control signal ADCK is output in synchronization with the fall of the half cycle signal Q4. If the phase of the pulse signal DATA and the phase of the window half-period signal Q4 are synchronized, the output of the arithmetic control signal ADCK cannot be obtained (see FIG. 2C).

On the other hand, the cycle measuring circuit 13-2 operates as shown in the time chart of FIG. Period measurement circuit 13-2
Measures the cycle every time the pulse signal DATA arrives, and outputs data F0 to F4 with the difference from the reference cycle as one cycle of the basic clock. For example, the cycle measuring circuit 13-2
Indicates that the measurement cycle is equal to the reference cycle (reference cycle = 4u)
As “s),“ 00H (hexadecimal expression, the same applies hereinafter) ”is output as data F0 to F4 (see FIG. 3A). Further, as shown in FIG. 3B, when the measurement period is larger than the basic period by one period of the basic clock (basic period + 1 = 4 us + 6).
In “2.5 ns”, “01H” is output as data F0 to F4. Conversely, as shown in FIG. 3C, when the measurement period is smaller than the reference period by one period of the basic clock (basic period−1 = 4 us−62.5 ns), the data F0 to F
As “4”, “1FH” is output.

FIG. 4 shows the relationship between the difference value with respect to the reference cycle and the data F0 to F4 output corresponding to the difference. The difference value is "-15" to "+15" with the difference value "± 0" being the center.
The output states of the data F0 to F4 in the range up to are shown. Thus, the bias value generation circuit 13-3 sets the value based on the output data F0 to F4 of the period measurement circuit 13-2 in accordance with the sign signal +/- from the phase comparison circuit 13-1 and the operation control signal ADCK. Correction is applied and given to the digital VFO 13-4 as a bias value.

FIG. 5 is a time chart showing the operation of the bias value generation circuit 13-3, particularly, the operation at the time of detecting the sync field of the read data signal (hereinafter, referred to as a high-speed tracking mode). Data F0 to F4
Is output as an example.
The data of “00H” is output from the cycle measurement circuit 13-2 when the measurement cycle is equal to the reference cycle, as described above. Here, in the high-speed following mode, the FD
The external control signal C output from C is at a low level, and the selector 13-13 outputs the input data B0 to B7 from the phase correction circuit 13-11 according to the external control signal C.
Is output to the registers 13-14. First, FIG. 5A
When the pulse signal DATA has a lagging phase with respect to the window half-period signal Q4 as shown in (1), the sign signal +/- from the phase comparator 13-1 goes low, and the one-shot pulse Is output. Then, the phase correction circuit 13-1
1 is "1" for the output value "00H" of the cycle measuring circuit 13-2.
, And the value “01H” is output to the selector 13−
13 and is held in the register 13-14 in response to the operation control signal ADCK from the phase comparison circuit 13-1, so that the outputs Q0 to Q7 of the register 13-14 are set to "01H". And is given to the digital VFO 13-4. In this case, in the selector 13-13, the lower three bits B0, B
1 and B2 are fixed to "0" (low level). As a result, the lower three bits BLD0, BLD1, BLD21 and BLD3 of the input value of the digital VFO 13-4 are also fixed to "0". Therefore, in the high-speed tracking mode, the bias value input to the digital VFO 13-4 is BD
0, BD1,..., BD4 are 5-bit data.

When the pulse signal DATA is advanced in phase with respect to the window half-period signal Q4 as shown in FIG. 5B, the sign signal +/- from the phase comparator 13-1 becomes high level, and the phase comparator 13 The operation control signal ADCK is output from -1. Then, the phase correction circuit 1
3-11 subtracts "1" from the output value "00H" of the cycle measuring circuit 13-2 and outputs the result. The value "FFH" is given to the register 13-14 via the selector 13-13.
The data is held in the register 13-14 in response to the operation control signal ADCK from the phase comparison circuit 13-1. Therefore,
The outputs Q0 to Q7 of the registers 13-14 become "FFH" and are given to the digital VFO 13-4.

When the phase of the pulse signal DATA is synchronized with the window half-period signal Q4 as shown in FIG. 5C, the code signal +/- from the phase comparison circuit 13-1.
Becomes low level as in the case of the delay phase, but the output of the operation control signal ADCK is not obtained from the phase comparison circuit 13-1. As a result, the content held in the register 13-14 does not change, and the register 13- 14 outputs the data “00H” as it is.

As a result, the digital VFO 13-4 generates a window signal having a frequency corresponding to the data from the bias value generating circuit 13-3, and
4 and the like, and a window half-period signal Q4 is generated and supplied to the phase comparator 13-1 as a feedback signal.

FIGS. 6 and 7 show output states of the window signal and the window half-period signal Q4 which change in accordance with the amount of change when the bias value is "00000" as a reference value in the high-speed tracking mode. 6 shows a case where the amount of change in the bias value increases by plus “1” with respect to the reference value, and FIG. 7 shows a case where the amount of change in the bias value decreases by minus “1” with respect to the reference value. ing. Here, the reference period (4 us) of the window signal is 1
When converted to a 6 MHz basic clock signal CK, it corresponds to 64 clocks. Therefore, one cycle of the window half-period signal Q4 corresponds to 32 clocks, and a half cycle thereof corresponds to 16 clocks. The number of clocks in one cycle of the window signal increases or decreases as shown in FIG. At this time, the digital VFO 13-4 almost does not destroy the duty ratio of 50% of the window signal and the window half-period signal Q4, and the window signal and the window half-period signal Q4 with an accuracy of one cycle of the basic clock with respect to the change amount of the bias value. Cycle (number of clocks) is increased or decreased.

As described above, in the high-speed following mode, the above operation is repeated for each cycle of the window signal to correct the bias value and control the oscillation frequency of the window signal.

Next, the operation when the data field of the read data signal is detected (hereinafter referred to as the low-speed following mode) is shown in FIG.
This will be described with reference to FIG. When entering the low-speed following mode, FDC
Is high, the period measurement circuit 1
3-2. The frequency correction circuit 13-12 is effective instead of the phase correction circuit 13-11. That is, the selector 13
-13 outputs the input value from the phase correction circuit 13-11 instead of the phase correction circuit 13-11 when the control signal C switches from the low level to the high level. Here, at the moment when the mode is switched, the bias value in the high-speed following mode is held in the register 13-14 as it is, and the bias value is corrected using the bias value as a reference value. The lower 3 bits of the bias value in the high-speed tracking mode are fixed to "0" and are treated as a 5-bit bias value. However, in the low-speed tracking mode, the bias value is released and the bias value is treated as 8-bit data. It is.

FIG. 8 is a time chart showing the operation of the frequency correction circuit 13-12, in which the input values D0 to D7 of the frequency correction circuit 13-12 are "00H". First, as shown in FIG. 8A, the window half-period signal Q4
In contrast, when the pulse signal DATA has a delayed phase, the sign signal +/- from the phase comparison circuit 13-1 becomes low level, and the operation control signal ADCK is output from the phase comparison circuit 13-1. Then, the frequency correction circuit 13-
Numeral 12 adds "1" to the input value "00H" and outputs the added value. The value "01H" is given to the register 13-14 via the selector 13-13, and the arithmetic operation control is performed from the phase comparison circuit 13-1. The register 13-1 responds to the signal ADCK.
4 is held. Therefore, the outputs Q0 to Q7 of the registers 13-14 become "01H", and the frequency correction circuit 13
The signal is returned to -12 and is input to the digital VFO 13-4.

When the pulse signal DATA is advanced in phase with respect to the window half-period signal Q4 as shown in FIG. 8B, the sign signal +/- from the phase comparison circuit 13-1 goes high, and the phase comparison circuit 13-1 outputs an operation control signal ADCK. Then, the frequency correction circuit 13-12 subtracts “1” from the input value “00H” and outputs the result. The value “FFH” is provided to the register 13-14 via the selector 13-13, and the phase comparison circuit 1
The signal is held in the register 13-14 in response to the operation control signal ADCK from 3-1. Therefore, register 13-
The outputs Q0 to Q7 are "01H" and are fed back to the frequency correction circuit 13-12.
Input to 3-4.

As shown in FIG. 8C, when the phase of the pulse signal DATA is synchronized with the window half-period signal Q4, the code signal + /
-Indicates a low level as in the case of the lag phase, but the output of the operation control signal ADCK is not obtained from the phase comparison circuit 13-1. As a result, the content held in the register 13-14 does not change, and From -14, the data of "00H" is output as it is. As described above, in the low-speed following mode, the above operation is repeated for each cycle of the window signal to correct the bias value and control the oscillation frequency of the window signal.

The above-described embodiment is a digital VFO 13-
Although the bias value input to 4 is 8 bits, the number of bits is arbitrary, and the phase correction circuit 13-11 and the frequency correction circuit 13-12 perform "± 1" correction. ± n (n: an integer greater than or equal to 1) ”may be used, and the correction value is arbitrary. By changing each value, the tracking state of the window signal also changes.

[0030]

According to the present invention, the method of following the window signal with respect to the read data signal is switched between when the sync field of the read data signal is detected and when the data field is detected, whereby the lock pattern can be quickly locked to the sync pattern of the read data signal. After an accurate window signal is obtained, it is possible to follow only the redundant rotation fluctuation of the disk.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data separator for FDD.

FIG. 2 is a time chart for explaining an operation of the phase comparison circuit 13-1 shown in FIG.

FIG. 3 is a time chart for explaining the operation of the cycle measuring circuit 13-2 shown in FIG. 1;

4 is a diagram showing a relationship between a difference value with respect to a reference cycle and output data F0 to F4 in the cycle measuring circuit 13-2 shown in FIG.

5 is a time chart for explaining the operation of the phase correction circuit 13-11 shown in FIG.

FIG. 6 is a diagram illustrating an operation of the digital VFO 13-4 illustrated in FIG. 1, and illustrating an output state of a window signal or the like that changes when a bias value increases with respect to a reference value.

FIG. 7 is a diagram showing an operation of the digital VFO 13-4 shown in FIG. 1 and showing output states of a window signal and the like which change as a bias value decreases with respect to a reference value.

8 is a time chart for explaining the operation of the frequency correction circuit 13-12 shown in FIG.

FIG. 9 is a block diagram of a conventional FDD data separator.

FIG. 10 is a diagram for explaining a phase comparison between a read data signal and a window signal in the conventional example.

FIG. 11 is a view for explaining an FDD format in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Oscillator 12 Synchronization circuit 13 Tracking control circuit 13-1 Phase comparison circuit 13-2 Period measurement circuit 13-3 Bias value generation circuit 13-4 Digital VFO 13-11 Phase correction circuit 13-12 Frequency correction circuit 13-13 Selector 13 -14 register 14 data separate circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-83971 (JP, A) JP-A-2-76171 (JP, A) JP-A-62-48809 (JP, A) JP-A-1- 293718 (JP, A) JP-A-64-23466 (JP, A) JP-A-2-8234 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/14 H03L 7 / 00-7/14

Claims (1)

(57) [Claims] A digital VFO for generating a window signal for separating a read data signal from an FDD into a data pulse and a clock pulse; a phase comparison circuit for comparing the phases of the read data signal and the window signal; A period measuring circuit for measuring a period of the read data signal; and a bias value generating circuit for generating a bias value to be inputted to the digital VFO from an output result of the phase comparing circuit and the period measuring circuit. Digital VFO by changing the bias value
A bias value generation circuit that corrects an output value of the period measurement circuit based on a comparison result of the phase comparison circuit, wherein the bias value generation circuit corrects an output value of the cycle measurement circuit based on a comparison result of the phase comparison circuit. An arithmetic circuit, and when the sync field is detected in the read data signal, the value corrected by the first arithmetic circuit is used as the digital VF value.
A switching circuit that directly outputs a bias value input to O, and switches and outputs a value in which a bias value at the time of sync field detection is corrected as a reference value at the time of data field detection, and temporarily stores a bias value output from this switching circuit. A holding circuit for holding, and correcting a bias value in the holding circuit based on a comparison result of the phase comparison circuit,
A second arithmetic circuit that uses the correction value as an input value of the switching circuit.