JPH04310675A - Data separator for fdd - Google Patents

Abstract

PURPOSE:To control the oscillation frequency of a window signal and to quickly re-synchronize by considering even the period of a reading data signal besides the phase difference between the reading data signal and the window signal during the period of a sink field. CONSTITUTION:A phase comparing circuit 13-1 compares the phase difference between a reading data signal and a window signal. A period measuring circuit 13-2 measures the period of the reading data signal. A bias value generating circuit 13-3 corrects the input value inputted to a digital VFO 13-4 from the output result of the phase comparing circuit 13-1 and the period measuring circuit 13-2 and controls the oscillation frequency of the digital VFO 13-4. A window value comparing circuit 15-2 compares the level value of the window signal when the reading data signal is sent at this time and the previous level value held at a window value storing circuit 15-1. The digital VFO 13-4 makes the standard value into the input value based on the compared result.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data separator for an FDD (floppy disk drive) that generates a window signal that separates a read data signal from a floppy disk drive into a data pulse and a clock pulse.

0002

2. Description of the Related Art Generally, in an FDC (floppy disk controller), a window signal that follows the frequency change of the read data signal is used to separate the MFM recording read data signal sent from the FDD into a clock pulse and a data pulse. A data separator for FDD that generates is required. This data separator generally uses an analog VFO (variable frequency generator) to generate a window signal, but this analog VFO data separator is easily affected by the external environment, such as filter characteristics changing depending on temperature, and external components ( It had drawbacks such as requiring resistors and capacitors. Therefore, in recent years, digital VFO data separators made up of only logic circuits have become known. As shown in FIG. 7, this type of data separator consists of a phase comparison circuit 1, a bias generation circuit 2, a digital VF
O3, a data separation circuit 4, and in order to generate a window signal that follows the frequency change of the read data signal, the phase comparator circuit 1 separates the center of the half cycle of the window signal and the read data signal as shown in FIG. The phase of the digital VFO 3 is detected, the bias value of the bias generation circuit 2 is changed based on this phase difference, the oscillation frequency of the digital VFO 3 is controlled using this bias value, and the output of this digital VFO 3 is fed back to the phase comparison circuit 1 as a window signal. P
It has a LL configuration. In the data separator configured in this way, by controlling the oscillation frequency of the digital VFO 3, an accurate window signal locked (synchronized) to the read data signal can be obtained. By the way, F
In the shift selector format commonly used in DDs, as shown in Figure 9, there is a SYNC field at the beginning of the ID field and the data field, and this SYNC field is composed of "00" data. , evenly spaced with only clock pulses (3.
In a 5-inch 2DD, MFM recording system, the pulse train is 4 us). Therefore, the interference from the front and rear pulses becomes equal, and no "shift" called peak shift occurs in the peak portion of their combined waveform. Therefore, by locking to the pulse train of this sync field, you can quickly lock in and obtain an accurate window signal.

0003

[Problem to be solved by the invention] If the window signal is locked to the pulse train of the sink field in this way,
Although it is possible to cause the window signal to quickly follow the read data signal, conventionally even faster tracking could not be expected. The reason for this is thought to be that the oscillation frequency of the digital VFO is controlled only by the phase difference between the read data signal and the window signal. Therefore, in Japanese Patent Application No. 2-246206 (title of invention: FDD data separator), the present applicant previously proposed that the position of the read data signal and the window signal within the sink field period of the read data signal. We have proposed a technique that controls the oscillation frequency of a digital VFO by taking into account not only the phase difference but also the period of the read data signal. This type of device measures the cycle of the read data signal, compares the measured cycle with the reference cycle, and controls the oscillation frequency of the window signal at once within the range of the maximum and minimum difference values. , high-speed tracking of window signals becomes possible. Here, in the case of a data structure according to a shift selector format as shown in FIG. 9, the data separator normally performs high-speed tracking using a SYNC signal output from a floppy disk controller (FDC). At that time, ideally the SYNC signal should be output only during the sync field period, as shown in Figure 10, but it is not possible to set the timing at which the SYNC signal is output, and There is a gap before entering the sync field, and this data should be represented by, for example, "4E", but due to a data shift between formatting and data writing, other data that does not constitute "4E" may exist in the gap. Data (discontinuities) may also be present. In such a case, when entering the sink field, the oscillation frequency of the window signal may be controlled all at once to the maximum or minimum value. FIG. 11(A) shows the state in this case. From this state, the oscillation frequency of the window signal is controlled as shown in FIG. 11(B), and the window signal is converted into a read data signal as shown in FIG. 11(C). It takes a considerable amount of time to resynchronize. The problem of this invention is
Within the period of the sink field of the read data signal, in addition to the phase difference between the read data signal and the window signal, the digital V
It is possible to control the oscillation frequency of the FO and also to be able to quickly resynchronize even if the sync field is entered from a gap in the format.

0004

[Means for Solving the Problems] The means of the present invention are as follows. (1) The digital VFO generates a window signal for separating the read data signal from the FDD into data pulses and clock pulses. (2) The phase comparator circuit detects the read data signal sent from the FDD within the sink field period.
Compare the phase difference between the read data signal and the window signal. (3) The period measurement circuit calculates the period of the read data signal sent from the FDD within the sink field period.
Measure the period of the read data signal. (4) The control circuit controls the oscillation frequency of the window signal output from the digital VFO by correcting the input value input to the digital VFO based on the output results of the phase comparison circuit and the period measurement circuit. (5) The holding circuit holds the level value of the window signal when the read data signal came last time. (6) The level value comparison circuit compares the level value of the window signal when the read data signal arrives this time with the level value held in the holding circuit.

[0005]

[Operation] The operation of the means of the present invention is as follows. Now, the phase comparator circuit compares the phase difference between the read data from the FDD and the window signal within the synch field period of the MFM recording read data signal sent from the FDD, and the period measurement circuit compares the phase difference between the read data from the FDD and the window signal. Measure the period of the data signal. In this case, phase comparison and period measurement are performed for each period of the window signal. Thus, the control circuit controls the oscillation frequency of the window signal output from the digital VFO by correcting the input value input to the digital VFO based on the output results of the phase comparison circuit and the period measurement circuit. On the other hand, the holding circuit stores and holds the level value of the window signal when the read data signal came last time, and the level value comparison circuit stores the level value of the window signal when the read data signal was sent this time. The value is compared with the level value held in the holding circuit. As a result, for example, if the level value of the window signal when the read data signal was sent last time was high level and the level value of the window signal when it was sent this time is low level, or vice versa. If the level value of the window signal when the read data signal was sent last time was low level and the level value of the window signal when it was sent this time is high level, that is, the level value between the previous time and this time is If there is a difference, a predetermined standard value is input to the digital VFO by switching the input value input to the digital VFO. Therefore, within the sync field period of the read data signal, the oscillation frequency of the digital VFO can be controlled by taking into consideration the period of the read data signal as well as the phase difference between the read data signal and the window signal. Even if it enters the sync field from a gap, etc., it can be quickly resynchronized.

[0006]

[Embodiment] An embodiment will be described below with reference to FIGS. 1 to 6. FIG. 1 is a block diagram of a data separator for FDD. The FDD data separator includes an oscillator 11, a synchronization circuit 12, a follow-up control circuit 13, a data separation circuit 14, and a resynchronization circuit 15.
has a configuration including a phase comparison circuit 13-1, a period measurement circuit 13-2, a bias value generation circuit 13-3, and a digital VFO 13-4. The resynchronization circuit 15 also includes a window value storage circuit 15-1, a window value comparison circuit 15-1, and a window value comparison circuit 15-1.
2.

The oscillator 11 oscillates and outputs a 16 MHz basic clock signal CLK, and the synchronous circuit 12 and the phase comparator circuit 1
3-1, period measurement circuit 13-2, digital VFO 13-
4. Provide data to the data separation circuit 14.

A read data signal RD sent from the FDD is input to the synchronization circuit 12, and this read data signal RD is synchronized with the basic clock signal CLK and has a width of one basic clock cycle (62.5 ns). The pulse signal DATA having the same value is applied to the phase comparison circuit 13-1, the period measurement circuit 13-2, and the data separation circuit 14.

The phase comparison circuit 13-1 receives this pulse signal D.
A phase comparison is made between the half-cycle signal Q4 of the window signal WD output from the ATA and the digital VFO 13-4,
As a result, when the pulse signal DATA, that is, the read data signal RD has a delayed phase, a low level +/- signal is output, and when it has an advanced phase, a high level +/- signal is output and the bias value is At the same time, the arithmetic control signal ADCK is output and applied to the bias value generation circuit 13-3.

The period measuring circuit 13-2 receives a pulse signal DAT.
Each time A is input, its period is measured, and the difference value from a predetermined reference period (4 us) is calculated as 5-bit data F0~ with one basic clock period (62.5 ns) as a weight.
It is output as F4 and applied to the bias value generation circuit 13-3.

When the bias value generation circuit 13-3 receives the arithmetic control signal ADCK from the phase comparison circuit 13-1,
The output data F0 to F4 of the period measurement circuit 13-2 is corrected according to the +/- signal from the phase comparison circuit 13-1 and outputted as bias values D0 to D4, and the digital VFO 13-
Give to 4. In this case, when the +/- signal from the phase comparator circuit 13-1 is at a low level, the bias value generation circuit 13-3 outputs the output data F0 to F4 of the period measurement circuit 13-2.
The data F0 to F4 are corrected by adding "1" and subtracting "1" from the output data F0 to F4 of the period measurement circuit 13-2 when the +/- signal is at a high level. Further, the frequency correction circuit 13-12 is configured as a phase comparator circuit 13-12.
Correct the input data D0 to D7 from the registers 13-14 according to the +/- signals from 8-bit data S0 to
S4 is given to the selector 13-13. In this case, like the phase correction circuit 13-11, the frequency correction circuit 13-12 uses the output data F0 to F4 of the period measurement circuit 13-2 when the +/- signal from the phase comparison circuit 13-1 is at a low level. When "1" is added to and the +/- signal is at high level, "1" is added from the output data F0 to F4 of the period measurement circuit 13-2.
The data F0 to F4 are corrected by subtracting .

The digital VFO 13-4 has a binary counter with load, etc., and its 6 bits Q0 to Q
5 out of 5 bits output Q5 is bias value generation circuit 13-
The bit output Q4 is output as a window signal with a frequency corresponding to the bias values Q0 to Q4 from 3, and the bit output Q4 is output as a half-cycle signal of the window signal (window half-cycle signal). Here, the window signal is given to the data separate circuit 14 etc., and the window half period signal Q4
is sent to the synchronization circuit 12 as a feedback signal.

Note that the data separation circuit 14 transfers the pulse signal DATA from the synchronization circuit 12 to the digital VFO 13.
- data pulse DP based on the window signal from
and clock pulse CP.

The window value storage circuit 15-1 constituting the resynchronization circuit 15 receives the read data signal RD (pulse signal D).
ATA) is used to memorize and hold the level value of the window signal sent last time.It has a configuration including flip-flops connected in two stages in cascade, etc., and the pulse signal DATA is input from the synchronization circuit 12, and the digital VFO1
Q5 output (window signal) is input from 3-4. Then, the window value storage circuit 15-1 sends the previous level signal CMP indicating whether the level value of the window signal when the pulse signal DATA was last sent is high level or low level to the window value comparison circuit 15-2. give.

Here, the window value comparison circuit 15-2 compares the level value of the window signal when the pulse signal DATA is sent this time and the level value of the window signal held in the window value storage circuit 15-1. For comparison, the previous level signal CMP is input from the window value storage circuit 15-1, the pulse signal DATA is input from the synchronization circuit 12, and the digital VFO 13-
4, the Q5 output (window signal) is input. When the previous level value and the current level value of the window signal are different, the window value comparison circuit 15-2 sends a one-shot pulse comparison result signal to the bias value generation circuit 13-3 as a reset signal RESET. It is output as a data load signal LOAD to the digital VFO 13-4. Here, when the reset signal RESET is input from the window value comparison circuit 15-2 to the bias value generation circuit 13-3, its contents are reset, and the digital VFO 13-4 receives the data from the window value comparison circuit 15-2. When the load signal LOAD is input, a predetermined standard value is used as the input value instead of the bias value from the bias value generation circuit 13-3. In this case, in this embodiment, a standard value such that the read data signal is synchronized with the center of the half cycle of the window signal is set as the load data value in advance for the digital VFO 13-
It is set to 4.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 to 6. Now, it is assumed that a pulse train at equal intervals is sent within the period of the sync field of the read data signal RD sent from the FDD. In this case, the read data signal RD is synchronized with the basic clock signal CLK by the synchronization circuit 12, and is output as a pulse signal DATA having a width of one period of the basic clock in addition to the data separation circuit 14, the phase comparison circuit 13-1, and the period measurement circuit. Sent to 13-2.

Then, the phase comparison circuit 13-1 operates as shown in the time chart of FIG. Phase comparison circuit 13-
1, the rise of this pulse signal DATA and the window half-cycle signal Q output from the digital VFO 13-4
4 and perform phase comparison. As a result, as shown in FIG. 2(A), the pulse signal DATA
(Read data signal RD) is the window half-cycle signal Q4
In the case of a delayed phase, the phase comparison circuit 13-1 sets the +/- signal to a low level in synchronization with the detection, and also outputs the one-shot pulse calculation control signal in synchronization with the fall of the window half-cycle signal Q4. Outputs ADCK. Also,
As shown in FIG. 2(B), when the pulse signal DATA has a leading phase with respect to the window half-cycle signal Q4, the phase comparator circuit 13-1 sets the +/- signal to high level in synchronization with the detection, and also A one-shot pulse arithmetic control signal ADCK is output in synchronization with the falling edge of the half-cycle signal Q4. Note that when the phases of the pulse signal DATA and the window half-cycle signal Q4 are synchronized, the output of the arithmetic control signal ADCK cannot be obtained (see FIG. 2(C)).

On the other hand, the period measuring circuit 13-2 operates as shown in the time chart of FIG. Period measurement circuit 13-2
measures the period of the pulse signal DATA every time it arrives, and outputs data F0 to F4 in which the difference from the reference period is weighted by one period of the basic clock. For example, the period measurement circuit 13-2
is when the measurement period is equal to the reference period (reference period = 4 us
), "00H (hexadecimal representation, the same applies hereinafter)" is output as data F0 to F4. Further, as shown in FIG. 3B, when the measurement period is longer than the basic period by one period of the basic clock (basic period+1=4 us+62.5 ns), "01H" is output as data F0 to F4. Conversely, as shown in Fig. 3(C), when the measurement period is one basic clock period smaller than the reference period (basic period - 1 = 4
us-62.5ns), “
1FH" is output.

FIG. 4 shows the relationship between the difference value with respect to the reference period and the corresponding output data F0 to F4, and the difference value "-15" (minimum value) to " Data F0 within the range up to “+15” (maximum value)
- Shows the output state of F4. Therefore, the bias value generation circuit 13-3 receives +/- from the phase comparison circuit 13-1.
The output data F0 to F4 of the period measurement circuit 13-2 is corrected according to the signal and the calculation control signal ADCK, and the values are used as bias values D0 to D4 to output the digital VFO 13-4.
give to

FIG. 5 is a time chart showing the operation of the bias value generation circuit 13-3, taking as an example the case where "00H" is outputted as data F0 to F4 from the period measurement circuit 13-2. Note that “0” is output from the period measurement circuit 13-2.
0H" data is output when the measurement period and the reference period are equal, as described above. First, when the pulse signal DATA has a delayed phase with respect to the window half-cycle signal Q4, the +/- signal from the phase comparison circuit 13-1 becomes a low level, and the arithmetic control signal ADCK is output from the phase comparison circuit 13-1. Therefore, bias value generation circuit 1
3-3 is a period measuring circuit 13-2 as shown in FIG. 5(A).
The output value "00H" is increased by "+1" in response to the output timing of the arithmetic control signal ADCK, and the value "01H" is applied to the digital VFO 13-4 as bias values D0 to D4. Further, when the pulse signal DATA is in a leading phase with respect to the window half-cycle signal Q4, the +/- signal from the phase comparator circuit 13-1 becomes high level, and the phase comparator circuit 13-1 becomes high level.
Since the arithmetic control signal ADCK is output from -1, the bias value generation circuit 13-3 outputs the output value "00H" of the period measuring circuit 13-2 as the arithmetic control signal ADCK, as shown in FIG. 5(B). It is set to "-1" in response to the timing, and the value "FFH" is applied to the digital VFO 13-4 as bias values D0 to D4. Note that when the phase of the pulse signal DATA is synchronized with the window half-cycle signal Q4, the arithmetic control signal ADC is output from the phase comparator circuit 13-1.
Since the output of K cannot be obtained, the bias value generation circuit 13-
3 applies the output value "00H" of the period measuring circuit 13-2 as it is to the digital VFO 13-4 as bias values D0 to D4, as shown in FIG. 5(C).

As a result, the digital VFO 13-4 generates a window signal with a frequency corresponding to the data D0 to D4 from the bias value generation circuit 13-3 and supplies it to the data separation circuit 14, etc., and also generates a window half-cycle signal Q4.
is generated and given to the phase comparator circuit 13-1 as a feedback signal.

FIG. 6 is a time chart showing the operation of the resynchronization circuit 15, and shows a state in which the oscillation frequency of the window signal is controlled by the resynchronization circuit when the same read data signal RD as in FIG. 11 is input. It shows. Here, FIG. 6X shows the output timing of the previous read data signal RD, and FIG. 6Y shows the output timing of the current read data signal RD. In this case, the window signal when the read data signal RD was sent last time was low level.
Therefore, a low level value is stored in the window value storage circuit 15-1 and provided to the window value comparison circuit 15-2. In this case, the window signal when the read data signal RD is sent this time is at a high level, so the window value comparison circuit 15-2 detects a mismatch between the two level values, so the digital VFO 13-4
A data load signal LOAD is input to the bias value generating circuit 13-3, and a reset signal RESET is input to the bias value generating circuit 13-3. Therefore, digital VFO
At 13-4, a preset data load value is switched as an input value instead of the input value from the bias value generation circuit 13-3, and the oscillation frequency of the window signal is controlled in accordance with this data load value. As a result, the window signal is aligned with the center of the half period of the read data signal RD as shown in FIG.
will now be synchronized.

Note that if the level value of the window signal when the read data signal RD was sent last time is equal to the level value of the window signal when it is sent this time,
The load signal LOA is output from the window value comparison circuit 15-2.
Since D is not output, in this case, digital VFO13
-4 controls the oscillation frequency of the window signal based on the input value from the bias value generation circuit 13-3 as in the normal case.

[0024]The above operation is repeated every cycle of the window signal.

[0025]

According to the present invention, the digital VFO is controlled by taking into account the period of the read data signal as well as the phase difference between the read data signal and the window signal within the sink field period of the read data signal. In addition to being able to control the oscillation frequency, it is also possible to quickly resynchronize even if the sync field enters the sync field from a gap in the format, so it is possible to make the window signal follow the read data signal at high speed. In particular, if the window signal is significantly out of synchronization with the read data signal, it is possible to quickly resynchronize it.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an FDD data separator showing an embodiment.

FIG. 2 is a time chart for explaining the operation of the phase comparator circuit 13-1 shown in FIG. 1.

3 is a time chart for explaining the operation of the period measuring circuit 13-2 shown in FIG. 1. FIG.

FIG. 4 is a diagram showing the relationship between a difference value with respect to a reference value and output data F0 to F4 in the period measurement circuit 13-2 shown in FIG. 1;

5 is a time chart for explaining the operation of the bias value generation circuit 13-3 shown in FIG. 1. FIG.

6 is a time chart for explaining the operation of the resynchronization circuit 15 shown in FIG. 1. FIG.

FIG. 7 is a block configuration diagram of an FDD data separator in an embodiment.

FIG. 8 is a diagram for explaining the phase difference between a read data signal and a window signal in a conventional example.

FIG. 9 is a diagram for explaining a sink field in a conventional example.

FIG. 10 is a diagram for explaining the problem to be solved by the present invention, and is a diagram showing the ideal output timing of the SYNC signal.

FIG. 11 is a diagram for explaining the problem to be solved by the present invention, and is a time chart showing the process of resynchronizing the window signal with respect to the read data signal when the synchronization is significantly deviated.

[Explanation of symbols]

11 Oscillation circuit 12 Synchronous circuit 13 Follow-up control circuit 13-1 Phase comparison circuit 13-2 Period measurement circuit 13-3 Bias value generation circuit 13-4 Digital VFO 14 Data separate circuit 15 Re-synchronization circuit 15-1 Window value storage circuit 15-2 Window value comparison circuit

Claims (1)

[Claims] 1. A digital VFO that generates a window signal for separating a read data signal from an FDD into a data pulse and a clock pulse; and a phase comparison circuit that compares the phase difference between the read data signal and the window signal. a period measuring circuit that measures the period of the read data signal;
a control circuit that controls the oscillation frequency of the window signal output from the digital VFO by correcting the input value input to the digital VFO from the output results of the phase comparison circuit and the period measurement circuit; an FDD data separator that controls the oscillation frequency of the window signal during the sink field period of the data signal, and a holding circuit that holds the level value of the window signal when the read data signal was last sent; , a level value comparison circuit that compares the level value of the window signal when the read data signal is sent this time with the level value held in the holding circuit, and is input to the digital VFO. A data separator for an FDD, characterized in that a predetermined standard value is input to the digital VFO by switching the input value based on the comparison result of the level comparison circuit.