JPS6057268U - Vertical synchronization signal detection circuit for high-definition television signals - Google Patents
Vertical synchronization signal detection circuit for high-definition television signalsInfo
- Publication number
- JPS6057268U JPS6057268U JP1983148644U JP14864483U JPS6057268U JP S6057268 U JPS6057268 U JP S6057268U JP 1983148644 U JP1983148644 U JP 1983148644U JP 14864483 U JP14864483 U JP 14864483U JP S6057268 U JPS6057268 U JP S6057268U
- Authority
- JP
- Japan
- Prior art keywords
- definition television
- synchronization signal
- vertical synchronization
- flip
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の好適な一実施例の回路図、第２、第３
及び第４図は第１図の動作を説明する波形図である。
１２：単安定マルチバイブレータ、１８：Ｄフリップ・
フロップ、３０：シフト・レジスタ、３４：フリップ・
フロップ。
ｑＱ Ｆ１４
２０
２
一平／ ｅｌＬス −発生塵
−
、’：１３６
ｄ’８ ’ｆｉｎ
６Figure 1 is a circuit diagram of a preferred embodiment of the present invention;
and FIG. 4 are waveform diagrams illustrating the operation of FIG. 1. 12: Monostable multivibrator, 18: D flip
Flop, 30: Shift register, 34: Flip
Flop. qQ F14 20 2 Ippei/elLsu -Generated dust
-,':136 d'8'fin 6
Claims (1)
リガされ、上記高品位テレビジョン信号の水平同期信号
幅よりも広い幅のパルスを発生する単安定マルチバイブ
レータと、Ｄ入力端に上記複合同期信号を受け、上記単
安定パルチバイブレータの出力パルスの後縁によりクロ
ックされると共に上記複合同期信号の後縁によりリセッ
トされ′ るＤフリップ・フロップと、該Ｄフリップ
・フロップの出力パルスを受ける所定ビット数のシフト
・レジスタと、上記Ｄフリップ・フロップの出カハルス
及ヒ上記シフト書レジスタの出力パルスにより前縁及び
後縁が夫々制御されるパルスを発生するフリップ・フロ
ップとを具え、該フリップ・フロップの出力パルスより
垂直同期信号を得ることを特徴とする高品位テレビジョ
ン信号用垂直同期信号検出回路。a monostable multivibrator that is triggered by a leading edge of a composite sync signal of a high-definition television signal and generates a pulse with a width wider than a horizontal sync signal width of the high-definition television signal; a D flip-flop which is clocked by the trailing edge of the output pulse of the monostable pultivibrator and reset by the trailing edge of the composite synchronization signal; and a predetermined number of bits receiving the output pulse of the D flip-flop. a shift register, and a flip-flop generating pulses whose leading and trailing edges are respectively controlled by the output pulses of the D flip-flop and the output pulse of the shift register; A vertical synchronization signal detection circuit for high-definition television signals, which is characterized in that a vertical synchronization signal is obtained from an output pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983148644U JPS6057268U (en) | 1983-09-26 | 1983-09-26 | Vertical synchronization signal detection circuit for high-definition television signals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983148644U JPS6057268U (en) | 1983-09-26 | 1983-09-26 | Vertical synchronization signal detection circuit for high-definition television signals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6057268U true JPS6057268U (en) | 1985-04-22 |
| JPH0127326Y2 JPH0127326Y2 (en) | 1989-08-15 |
Family
ID=30330191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983148644U Granted JPS6057268U (en) | 1983-09-26 | 1983-09-26 | Vertical synchronization signal detection circuit for high-definition television signals |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6057268U (en) |
-
1983
- 1983-09-26 JP JP1983148644U patent/JPS6057268U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0127326Y2 (en) | 1989-08-15 |
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