JPH0168530U - - Google Patents
Info
- Publication number
- JPH0168530U JPH0168530U JP1987161771U JP16177187U JPH0168530U JP H0168530 U JPH0168530 U JP H0168530U JP 1987161771 U JP1987161771 U JP 1987161771U JP 16177187 U JP16177187 U JP 16177187U JP H0168530 U JPH0168530 U JP H0168530U
- Authority
- JP
- Japan
- Prior art keywords
- microcomputer
- pulse counter
- circuit
- keyboard device
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Input From Keyboards Or The Like (AREA)
Description
第１図は本考案の１実施例に係るキーボード装
置の回路ブロツク図、第２図は本考案の他の実施
例の回路ブロツク図である。
１……マイクロコンピユータ、２……パルスカ
ウンタ、３……上位装置接続コネクタ、４……Ｏ
Ｒ回路、５……カウントリセツト信号、６……命
令読込信号、７……自己リセツト回路、８……リ
セツト信号、９……パルスカウンタの出力信号。
FIG. 1 is a circuit block diagram of a keyboard device according to one embodiment of the present invention, and FIG. 2 is a circuit block diagram of another embodiment of the present invention. 1...Microcomputer, 2...Pulse counter, 3...Host device connection connector, 4...O
R circuit, 5...Count reset signal, 6...Command reading signal, 7...Self reset circuit, 8...Reset signal, 9...Output signal of pulse counter.
Claims (1)
マイクロコンピユータ制御によるキーボード装置
において、パルスカウンタと、上位装置リセツト
信号または自己リセツト信号と前記パルスカウン
タの出力信号との論理和をとるＯＲ回路と、マイ
クロコンピユータの正常動作時に前記パルスカウ
ンタのカウントをリセツトする回路とを有し、前
記マイクロコンピユータの正常動作時には内部Ｒ
ＯＭのみ使用してフアームウエアが作成されてお
り、誤動作時に外部ＲＯＭに対してアクセスを行
つた場合、前記パルスカウンタによりカウント動
作が行われ、前記ＯＲ回路によりマイクロコンピ
ユータのリセツトが行われることを特徴とするマ
イクロコンピユータ制御キーボード装置。 A keyboard device controlled by a microcomputer that can use both an internal ROM and an external ROM includes a pulse counter, an OR circuit that ORs a host device reset signal or self-reset signal, and an output signal of the pulse counter, and a microcomputer-controlled keyboard device. A circuit that resets the count of the pulse counter during normal operation, and an internal R during normal operation of the microcomputer.
The firmware is created using only OM, and when an external ROM is accessed in the event of a malfunction, the pulse counter performs a counting operation, and the OR circuit resets the microcomputer. Microcomputer controlled keyboard device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987161771U JPH0168530U (en) | 1987-10-22 | 1987-10-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987161771U JPH0168530U (en) | 1987-10-22 | 1987-10-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0168530U true JPH0168530U (en) | 1989-05-02 |
Family
ID=31445001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987161771U Pending JPH0168530U (en) | 1987-10-22 | 1987-10-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0168530U (en) |
-
1987
- 1987-10-22 JP JP1987161771U patent/JPH0168530U/ja active Pending
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