JPS5865578U - Chiyotsupa test equipment - Google Patents

Chiyotsupa test equipment

Info

Publication number
JPS5865578U
JPS5865578U JP16031581U JP16031581U JPS5865578U JP S5865578 U JPS5865578 U JP S5865578U JP 16031581 U JP16031581 U JP 16031581U JP 16031581 U JP16031581 U JP 16031581U JP S5865578 U JPS5865578 U JP S5865578U
Authority
JP
Japan
Prior art keywords
test equipment
chiyotsupa
measures
chopper
counter circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16031581U
Other languages
Japanese (ja)
Inventor
弘瀬　憲章
均 村田
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP16031581U priority Critical patent/JPS5865578U/en
Publication of JPS5865578U publication Critical patent/JPS5865578U/en
Pending legal-status Critical Current

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  • Testing Electric Properties And Detecting Electric Faults (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の試験装置のブロック図、第２区は本考案
のブロック図、第３図は各部の波形を示した。 ４・・・発振回路、１２・・・マイクロコンピュータ、
１４・・・第１のカウンター回路、１５・・・第２のカ
ウンター回路。FIG. 1 is a block diagram of a conventional test device, section 2 is a block diagram of the present invention, and FIG. 3 is a waveform of each part. 4...Oscillation circuit, 12...Microcomputer,
14...First counter circuit, 15...Second counter circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロコンピュータで構成された演算制御部と発振回
路を有するチョッパ試験装置において、チョッピング周
期を測定する第一のカウンター回路と、オン時間を測定
する第二のカウンター回路を備えたことを特徴とするチ
ョッパ試験装置。A chopper test device having an arithmetic control section and an oscillation circuit configured with a microcomputer, characterized in that the chopper is equipped with a first counter circuit that measures a chopping period and a second counter circuit that measures an on-time. Test equipment.
JP16031581U 1981-10-29 1981-10-29 Chiyotsupa test equipment Pending JPS5865578U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16031581U JPS5865578U (en) 1981-10-29 1981-10-29 Chiyotsupa test equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16031581U JPS5865578U (en) 1981-10-29 1981-10-29 Chiyotsupa test equipment

Publications (1)

Publication Number Publication Date
JPS5865578U true JPS5865578U (en) 1983-05-04

Family

ID=29952729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16031581U Pending JPS5865578U (en) 1981-10-29 1981-10-29 Chiyotsupa test equipment

Country Status (1)

Country Link
JP (1) JPS5865578U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5614960A (en) * 1979-07-18 1981-02-13 Toyota Motor Corp Duty ratio calculator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5614960A (en) * 1979-07-18 1981-02-13 Toyota Motor Corp Duty ratio calculator

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