JPS6331445U - - Google Patents
Info
- Publication number
- JPS6331445U JPS6331445U JP12310286U JP12310286U JPS6331445U JP S6331445 U JPS6331445 U JP S6331445U JP 12310286 U JP12310286 U JP 12310286U JP 12310286 U JP12310286 U JP 12310286U JP S6331445 U JPS6331445 U JP S6331445U
- Authority
- JP
- Japan
- Prior art keywords
- loop counter
- control circuit
- loop
- input signal
- signal control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Executing Machine-Instructions (AREA)
Description
第１図は、本考案の構成を示すブロツク図、第
２図は、本考案のループカウンタのタイミングチ
ヤートである。
１……データバス、２……ａ‐ラツチ、３……
ａ‐カウンタ、４……カウント終了検出部、５…
…入力信号制御回路部、６……Ｘ‐ラツチ、７…
…Ｘ‐カウンタ、８……入力信号制御回路部、９
……ｂ‐ラツチ、１０……ｂ‐カウンタ、１１…
…ｙ‐ラツチ、１２……ｙ‐カウンタ。
FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a timing chart of the loop counter of the present invention. 1...data bus, 2...a-latch, 3...
a-Counter, 4... Count end detection section, 5...
...Input signal control circuit section, 6...X-latch, 7...
...X-counter, 8...Input signal control circuit section, 9
...b-latch, 10...b-counter, 11...
...y-latch, 12...y-counter.
Claims (1)
カウンタにおいて、内側のループを制御するルー
プカウンタと外側のループを制御するループカウ
ンタを備え、前記内側のループカウンタに入力信
号制御回路を設け、前記内側のループカウンタの
カウント終了を検出する手段により前記入力信号
制御回路と外側のループカウンタへカウントの終
了を通知することを特徴とするループカウンタの
制御回路。 A loop counter that performs multiple loop processing using a nested structure, comprising a loop counter that controls an inner loop and a loop counter that controls an outer loop, wherein the inner loop counter is provided with an input signal control circuit, and the inner loop counter is provided with an input signal control circuit. A control circuit for a loop counter, characterized in that the input signal control circuit and an outer loop counter are notified of the end of counting by means of detecting the end of counting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12310286U JPS6331445U (en) | 1986-08-11 | 1986-08-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12310286U JPS6331445U (en) | 1986-08-11 | 1986-08-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6331445U true JPS6331445U (en) | 1988-03-01 |
Family
ID=31013896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12310286U Pending JPS6331445U (en) | 1986-08-11 | 1986-08-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6331445U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58117050A (en) * | 1981-12-30 | 1983-07-12 | Fujitsu Ltd | Data processor |
-
1986
- 1986-08-11 JP JP12310286U patent/JPS6331445U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58117050A (en) * | 1981-12-30 | 1983-07-12 | Fujitsu Ltd | Data processor |
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