JPS61120955U - - Google Patents
Info
- Publication number
- JPS61120955U JPS61120955U JP239985U JP239985U JPS61120955U JP S61120955 U JPS61120955 U JP S61120955U JP 239985 U JP239985 U JP 239985U JP 239985 U JP239985 U JP 239985U JP S61120955 U JPS61120955 U JP S61120955U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- signal
- abnormality
- period
- clear
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 4
- 230000002596 correlated effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案による異常検出回路の一実施例
を示す構成図、第２図は第１図の構成の動作タイ
ムチヤート、第３図は異常検出回路の従来例を示
す構成図、第４図は第３図の回路の動作タイムチ
ヤートである。
２０：マイクロコンピユータ、２２：異常検出
回路、２３：単安定マルチバイブレータ、２４：
カウンタ、２５：フリツプフロツプ。
FIG. 1 is a block diagram showing an embodiment of the abnormality detection circuit according to the present invention, FIG. 2 is an operation time chart of the configuration shown in FIG. 1, FIG. 3 is a block diagram showing a conventional example of the abnormality detection circuit, and FIG. The figure is an operation time chart of the circuit of FIG. 3. 20: Microcomputer, 22: Abnormality detection circuit, 23: Monostable multivibrator, 24:
Counter, 25: Flip Flop.
Claims (1)
期のパルス信号を入力して、当該コンピユータの
動作異常を検出するための回路において、前記パ
ルス信号を入力して該信号の各パルス毎にクリア
パルスを出力する手段と、前記パルス信号の周期
に相関する周期の基準パルスと前記クリアパルス
とを入力して、前記基準パルスをカウントすると
共に前記クリアパルスが与えられる毎に当該カウ
ントをクリアし、カウント数が所定値になつても
クリアされない場合に異常信号を出力する手段と
を有することを特徴とする異常検出回路。 In a circuit for inputting a pulse signal of a constant or variable period from a microcomputer and detecting an abnormality in the operation of the computer, means for inputting the pulse signal and outputting a clear pulse for each pulse of the signal; A reference pulse with a period correlated to the period of the pulse signal and the clear pulse are input, the reference pulse is counted, and the count is cleared every time the clear pulse is given, until the count reaches a predetermined value. 1. An abnormality detection circuit comprising means for outputting an abnormality signal when the abnormality signal is not cleared.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP239985U JPS61120955U (en) | 1985-01-14 | 1985-01-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP239985U JPS61120955U (en) | 1985-01-14 | 1985-01-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61120955U true JPS61120955U (en) | 1986-07-30 |
Family
ID=30476041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP239985U Pending JPS61120955U (en) | 1985-01-14 | 1985-01-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61120955U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5587252A (en) * | 1978-12-26 | 1980-07-01 | Komatsu Ltd | Display and prevention circuit for computer reckless run |
| JPS5832542B2 (en) * | 1978-11-02 | 1983-07-13 | 松下電器産業株式会社 | Paging receiver signal detection method |
-
1985
- 1985-01-14 JP JP239985U patent/JPS61120955U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5832542B2 (en) * | 1978-11-02 | 1983-07-13 | 松下電器産業株式会社 | Paging receiver signal detection method |
| JPS5587252A (en) * | 1978-12-26 | 1980-07-01 | Komatsu Ltd | Display and prevention circuit for computer reckless run |
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