JPH01147447U - - Google Patents
Info
- Publication number
- JPH01147447U JPH01147447U JP4268588U JP4268588U JPH01147447U JP H01147447 U JPH01147447 U JP H01147447U JP 4268588 U JP4268588 U JP 4268588U JP 4268588 U JP4268588 U JP 4268588U JP H01147447 U JPH01147447 U JP H01147447U
- Authority
- JP
- Japan
- Prior art keywords
- program
- writing
- ram
- directly
- debugger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Debugging And Monitoring (AREA)
- Multi Processors (AREA)
Description
第１図は本考案の一実施例の回路構成を示すブ
ロツク図、第２図は第１図のカードＲＡＭへのプ
ログラム書込みを示すブロツク図、第３図は従来
のマルチＣＰＵ方式のマイクロコンピユータの回
路構成を示すブロツク図、第４図は第３図のＲＯ
Ｍへのプログラム書込みを示すブロツク図である
。
１〜４，１９〜２１……ＣＰＵカード、５……
メモリカード、６，８，１０，１３，２２，２４
，２６……ＣＰＵ、７，９，１１，１６……メモ
リＲＡＭ、１２，１５……通信Ｉ／Ｏポート、１
４，２３，２５，２７……メモリＲＯＭ・ＲＡＭ
、１８……共通バス、２８……デバツガ。
Fig. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing the writing of a program to the card RAM of Fig. 1, and Fig. 3 is a block diagram of a conventional multi-CPU type microcomputer. A block diagram showing the circuit configuration, Figure 4 is the RO of Figure 3.
FIG. 2 is a block diagram showing writing of a program to M. FIG. 1-4, 19-21...CPU card, 5...
Memory card, 6, 8, 10, 13, 22, 24
, 26... CPU, 7, 9, 11, 16... Memory RAM, 12, 15... Communication I/O port, 1
4, 23, 25, 27...Memory ROM/RAM
, 18... common bus, 28... Debatsuga.
Claims (1)
において、 各ＣＰＵに対応するメモリをすべてＲＡＭで構
成し、 電源オン時に上記ＲＡＭへのロード用として用
いられる、メモリバツクアツプを施し制御プログ
ラムを記憶させたＲＡＭで構成された可搬式のカ
ードと、 プログラム開発時に同じ共通バスを持つたデバ
ツガによつて直接プログラムを書込む書込手段と
、 通信時にＩ／Ｏポートを介して他部からプログ
ラムの変更を行なうプログラム変更手段と を備えたことを特徴とするマイクロコンピユー
タ装置。[Claims for Utility Model Registration] In a multi-CPU type microcomputer device, all of the memory corresponding to each CPU is composed of RAM, and a control program is provided with a memory backup that is used for loading into the RAM when the power is turned on. A portable card consisting of a RAM that stores , a writing means for directly writing a program using a debugger that has the same common bus during program development, and a writing means for directly writing a program using a debugger that has the same common bus during program development, and a writing means for writing programs directly from other parts through an I/O port during communication. A microcomputer device comprising: program change means for changing a program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4268588U JPH01147447U (en) | 1988-03-30 | 1988-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4268588U JPH01147447U (en) | 1988-03-30 | 1988-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01147447U true JPH01147447U (en) | 1989-10-12 |
Family
ID=31269093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4268588U Pending JPH01147447U (en) | 1988-03-30 | 1988-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01147447U (en) |
-
1988
- 1988-03-30 JP JP4268588U patent/JPH01147447U/ja active Pending