JPH0299447U - - Google Patents
Info
- Publication number
- JPH0299447U JPH0299447U JP506889U JP506889U JPH0299447U JP H0299447 U JPH0299447 U JP H0299447U JP 506889 U JP506889 U JP 506889U JP 506889 U JP506889 U JP 506889U JP H0299447 U JPH0299447 U JP H0299447U
- Authority
- JP
- Japan
- Prior art keywords
- memory circuit
- microcomputer
- turned
- processing unit
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
- Detection And Correction Of Errors (AREA)
Description
図は本考案実施例の構成を示すブロツク図。
１……ＣＰＵ、２……パラレルポート、３……
ランダムアクセスメモリ回路（ＲＡＭ）、４……
電圧低下検出バツクアツプ電源回路、５……フア
ームプロセツサ、６……データ信号、７……アド
レス信号、８……メモリ書込制御信号、９……入
出力制御信号、１０……データ信号、１１……ア
ドレス・パリテイ読出制御信号、１２……割込信
号、１３……バツクアツプ電源線。
The figure is a block diagram showing the configuration of an embodiment of the present invention. 1...CPU, 2...Parallel port, 3...
Random access memory circuit (RAM), 4...
Voltage drop detection backup power supply circuit, 5... Farm processor, 6... Data signal, 7... Address signal, 8... Memory write control signal, 9... Input/output control signal, 10... Data signal, 11 . . . Address/parity read control signal, 12 . . . Interrupt signal, 13 . . . Backup power supply line.
Claims (1)
と、 電源停止にこのメモリ回路をバツクアツプする
補助電源回路と を備えたマイクロコンピユータにおいて、 上記中央処理装置が上記メモリ回路にデータを
書き込むごとに検査付加符号を生成するフアーム
プロセツサを備え、 このフアームプロセツサも電源停止時にバツク
アツプされる構成であり、 上記中央処理装置は、再起動されたときに電源
停止前から保持されていた上記メモリ回路のデー
タから生成された検査付加符号と上記フアームプ
ロセツサに保持されていた検査付加符号とを比較
し一致するか否かを判断する手段を備えた ことを特徴とするマイクロコンピユータ。[Claims for Utility Model Registration] A microcomputer comprising a central processing unit, a random access memory circuit, and an auxiliary power supply circuit for backing up this memory circuit when the power is turned off, wherein the central processing unit inputs data to the memory circuit. It is equipped with a farm processor that generates a check addition code each time it is written, and this farm processor is also configured to be backed up when the power is turned off. A microcomputer comprising means for comparing the test additional code generated from the data in the memory circuit and the test additional code held in the farm processor to determine whether or not they match.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP506889U JPH0299447U (en) | 1989-01-20 | 1989-01-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP506889U JPH0299447U (en) | 1989-01-20 | 1989-01-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0299447U true JPH0299447U (en) | 1990-08-08 |
Family
ID=31208123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP506889U Pending JPH0299447U (en) | 1989-01-20 | 1989-01-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0299447U (en) |
-
1989
- 1989-01-20 JP JP506889U patent/JPH0299447U/ja active Pending
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