JPS62199863U - - Google Patents

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Publication number
JPS62199863U
JPS62199863U JP8714986U JP8714986U JPS62199863U JP S62199863 U JPS62199863 U JP S62199863U JP 8714986 U JP8714986 U JP 8714986U JP 8714986 U JP8714986 U JP 8714986U JP S62199863 U JPS62199863 U JP S62199863U
Authority
JP
Japan
Prior art keywords
data
data transfer
transfer device
clock signal
model registration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8714986U
Other languages
Japanese (ja)
Other versions
JPH0726757Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986087149U priority Critical patent/JPH0726757Y2/en
Publication of JPS62199863U publication Critical patent/JPS62199863U/ja
Application granted granted Critical
Publication of JPH0726757Y2 publication Critical patent/JPH0726757Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Bus Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係るデータ転送装置の一実施
例を示す斜視図、第２図は第１図示の実施例に係
るデータ転送装置の回路構成例を示すブロツク図
である。 １……装置本体、３……電源スイツチ、５……
表示器、７Ａ，７Ｂ……コネクタ、１１……転送
制御回路、１３Ａ，１３Ｂ……アドレスカウンタ
、１５……表示回路、１７……電源、１００，２
００……メモリ装置。 FIG. 1 is a perspective view showing an embodiment of a data transfer device according to the present invention, and FIG. 2 is a block diagram showing an example of the circuit configuration of the data transfer device according to the embodiment shown in FIG. 1...Device body, 3...Power switch, 5...
Display device, 7A, 7B...Connector, 11...Transfer control circuit, 13A, 13B...Address counter, 15...Display circuit, 17...Power supply, 100,2
00...Memory device.

Claims (1)

【実用新案登録請求の範囲】 (1) データ読出しに係る記憶装置のデータバス
とデータ書込みに係る記憶装置のデータバスとを
直接結合させる接続手段と、 当該書込みおよび読出しに係る記憶装置の双方
のアドレスバスに結合し、クロツク信号の供給に
応じて前記双方の記憶装置の記憶領域のアドレス
を順次歩進しつつ指定するアドレス指定手段と、 データ転送にあたり前記クロツク信号を発生し
て前記アドレス指定手段に供給する転送制御手段
とを具えたことを特徴とするデータ転送装置。 (2) 実用新案登録請求の範囲第１項記載のデー
タ転送装置において、前記転送制御手段は電源の
投入に応じて前記クロツク信号を発生する発振器
を有し、前記アドレス指定手段は前記発振器の出
力を計数して、その計数値をアドレス指定信号と
して出力するアドレスカウンタの形態を有するこ
とを特徴とするデータ転送装置。 (3) 実用新案登録請求の範囲第１項または第２
項記載のデータ転送装置において、データ転送に
あたつてその転送動作実行中を報知する報知手段
を有し、当該報知動作を前記アドレスカウンタの
カウントアツプ出力に応じて停止させるようにし
たことを特徴とするデータ転送装置。[Claims for Utility Model Registration] (1) Connecting means that directly connects the data bus of a storage device for data reading and the data bus of a storage device for data writing, and both of the storage devices for writing and reading. Addressing means coupled to an address bus and sequentially incrementing and specifying the addresses of the storage areas of both storage devices in response to the supply of a clock signal; and Addressing means for generating the clock signal during data transfer. 1. A data transfer device comprising: transfer control means for supplying data to the computer. (2) Utility Model Registration In the data transfer device according to claim 1, the transfer control means includes an oscillator that generates the clock signal when power is turned on, and the addressing means generates the clock signal according to the output of the oscillator. 1. A data transfer device, characterized in that it has the form of an address counter that counts and outputs the counted value as an address designation signal. (3) Scope of claims for utility model registration, paragraph 1 or 2
The data transfer device according to item 1 is characterized in that it has a notification means for notifying that the transfer operation is in progress when transferring data, and the notification operation is stopped in accordance with the count-up output of the address counter. data transfer device.
JP1986087149U 1986-06-10 1986-06-10 Data transfer device Expired - Lifetime JPH0726757Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986087149U JPH0726757Y2 (en) 1986-06-10 1986-06-10 Data transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986087149U JPH0726757Y2 (en) 1986-06-10 1986-06-10 Data transfer device

Publications (2)

Publication Number Publication Date
JPS62199863U true JPS62199863U (en) 1987-12-19
JPH0726757Y2 JPH0726757Y2 (en) 1995-06-14

Family

ID=30944108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986087149U Expired - Lifetime JPH0726757Y2 (en) 1986-06-10 1986-06-10 Data transfer device

Country Status (1)

Country Link
JP (1) JPH0726757Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07104944A (en) * 1993-09-30 1995-04-21 Sony Corp Information transfer device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132629U (en) * 1980-03-10 1981-10-07
JPS59197920A (en) * 1983-04-25 1984-11-09 Nec Corp Address controlling device
JPS60138622A (en) * 1983-12-27 1985-07-23 Oki Electric Ind Co Ltd Bus extension method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132629U (en) * 1980-03-10 1981-10-07
JPS59197920A (en) * 1983-04-25 1984-11-09 Nec Corp Address controlling device
JPS60138622A (en) * 1983-12-27 1985-07-23 Oki Electric Ind Co Ltd Bus extension method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07104944A (en) * 1993-09-30 1995-04-21 Sony Corp Information transfer device

Also Published As

Publication number Publication date
JPH0726757Y2 (en) 1995-06-14

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