JPH0289501U - - Google Patents
Info
- Publication number
- JPH0289501U JPH0289501U JP16693888U JP16693888U JPH0289501U JP H0289501 U JPH0289501 U JP H0289501U JP 16693888 U JP16693888 U JP 16693888U JP 16693888 U JP16693888 U JP 16693888U JP H0289501 U JPH0289501 U JP H0289501U
- Authority
- JP
- Japan
- Prior art keywords
- ram
- data
- decoder
- cpu
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Safety Devices In Control Systems (AREA)
Description
第1図は本考案一実施例の回路図、第2図は従
来例の回路図、第3図および第4図は同上の動作
説明図である。
1はRAM、3はクロツクジエネレータ、4は
CPU、5はデコーダ、7は電圧検出回路である
。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional example, and FIGS. 3 and 4 are explanatory diagrams of the same operation. 1 is a RAM, 3 is a clock generator, 4 is a CPU, 5 is a decoder, and 7 is a voltage detection circuit.
Claims (1)
きのRAMと、クロツクジエネレータを介して入
力されるリセツト信号にてリセツトされRAMに
記憶されたデータの演算処理を行つて動作制御を
行うCPUと、CPUから出力されるコントロー
ル信号をデコードしてRAMのデータ書き込み、
読み出し制御などを行うデコーダとで構成された
マイコン制御機器において、回路電源がCPUの
動作補償電圧以下になつたときに電圧低下検出信
号を出力する電圧検出回路を設け、上記電圧低下
検出信号がデコーダのエイブル端子に入力された
ときRAMへのデータの書き込みを禁止するよう
にしたことを特徴とするマイコン制御機器。 A RAM with a power failure backup function that stores control data, a CPU that is reset by a reset signal input via a clock generator and performs arithmetic processing on data stored in the RAM to control operations; Decode the output control signal and write data to RAM,
In a microcomputer-controlled device configured with a decoder that performs read control, etc., a voltage detection circuit is provided that outputs a voltage drop detection signal when the circuit power supply falls below the operation compensation voltage of the CPU, and the voltage drop detection signal is detected by the decoder. A microcomputer-controlled device characterized in that writing of data to a RAM is prohibited when input to an enable terminal of the device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16693888U JPH0289501U (en) | 1988-12-23 | 1988-12-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16693888U JPH0289501U (en) | 1988-12-23 | 1988-12-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0289501U true JPH0289501U (en) | 1990-07-16 |
Family
ID=31454777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16693888U Pending JPH0289501U (en) | 1988-12-23 | 1988-12-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0289501U (en) |
-
1988
- 1988-12-23 JP JP16693888U patent/JPH0289501U/ja active Pending
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