JPH0289501U - - Google Patents

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Publication number
JPH0289501U
JPH0289501U JP16693888U JP16693888U JPH0289501U JP H0289501 U JPH0289501 U JP H0289501U JP 16693888 U JP16693888 U JP 16693888U JP 16693888 U JP16693888 U JP 16693888U JP H0289501 U JPH0289501 U JP H0289501U
Authority
JP
Japan
Prior art keywords
ram
data
decoder
cpu
microcomputer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16693888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16693888U priority Critical patent/JPH0289501U/ja
Publication of JPH0289501U publication Critical patent/JPH0289501U/ja
Pending legal-status Critical Current

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  • Safety Devices In Control Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案一実施例の回路図、第２図は従
来例の回路図、第３図および第４図は同上の動作
説明図である。 １はＲＡＭ、３はクロツクジエネレータ、４は
ＣＰＵ、５はデコーダ、７は電圧検出回路である
。 FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional example, and FIGS. 3 and 4 are explanatory diagrams of the same operation. 1 is a RAM, 3 is a clock generator, 4 is a CPU, 5 is a decoder, and 7 is a voltage detection circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御データを記憶する停電バツクアツプ機能付
きのＲＡＭと、クロツクジエネレータを介して入
力されるリセツト信号にてリセツトされＲＡＭに
記憶されたデータの演算処理を行つて動作制御を
行うＣＰＵと、ＣＰＵから出力されるコントロー
ル信号をデコードしてＲＡＭのデータ書き込み、
読み出し制御などを行うデコーダとで構成された
マイコン制御機器において、回路電源がＣＰＵの
動作補償電圧以下になつたときに電圧低下検出信
号を出力する電圧検出回路を設け、上記電圧低下
検出信号がデコーダのエイブル端子に入力された
ときＲＡＭへのデータの書き込みを禁止するよう
にしたことを特徴とするマイコン制御機器。 A RAM with a power failure backup function that stores control data, a CPU that is reset by a reset signal input via a clock generator and performs arithmetic processing on data stored in the RAM to control operations; Decode the output control signal and write data to RAM,
In a microcomputer-controlled device configured with a decoder that performs read control, etc., a voltage detection circuit is provided that outputs a voltage drop detection signal when the circuit power supply falls below the operation compensation voltage of the CPU, and the voltage drop detection signal is detected by the decoder. A microcomputer-controlled device characterized in that writing of data to a RAM is prohibited when input to an enable terminal of the device.
JP16693888U 1988-12-23 1988-12-23 Pending JPH0289501U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16693888U JPH0289501U (en) 1988-12-23 1988-12-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16693888U JPH0289501U (en) 1988-12-23 1988-12-23

Publications (1)

Publication Number Publication Date
JPH0289501U true JPH0289501U (en) 1990-07-16

Family

ID=31454777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16693888U Pending JPH0289501U (en) 1988-12-23 1988-12-23

Country Status (1)

Country Link
JP (1) JPH0289501U (en)

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