JPH026323U - - Google Patents

Info

Publication number
JPH026323U
JPH026323U JP8323188U JP8323188U JPH026323U JP H026323 U JPH026323 U JP H026323U JP 8323188 U JP8323188 U JP 8323188U JP 8323188 U JP8323188 U JP 8323188U JP H026323 U JPH026323 U JP H026323U
Authority
JP
Japan
Prior art keywords
system reset
control circuit
synchronization
read
issues
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8323188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8323188U priority Critical patent/JPH026323U/ja
Publication of JPH026323U publication Critical patent/JPH026323U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例によるシステムリ
セツト制御回路のブロツク図、第2図は第1図の
システムリセツト発生タイミング図、第3図は従
来のシステムリセツト制御回路のブロツク図、第
4図は第3図のシステムリセツト発生タイミング
図である。 図において、1……AC入力、2……パワーダ
ウン検出部、3……同期化システムリセツト発生
部、4……CPU部、5……バツテリバツクアツ
プメモリ。なお、図中、同一符号は同一、又は相
当部分を示す。
FIG. 1 is a block diagram of a system reset control circuit according to an embodiment of this invention, FIG. 2 is a timing diagram of system reset occurrence in FIG. 1, FIG. 3 is a block diagram of a conventional system reset control circuit, and FIG. is a system reset generation timing diagram of FIG. 3; In the figure, 1...AC input, 2...Power down detection section, 3...Synchronization system reset generation section, 4...CPU section, 5...Battery backup memory. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] システムリセツト発行要求に対してCPU部か
らのリード信号等のリードサイクルを示す信号に
同期化してシステムリセツトを発行するようにし
たことを特徴とするシステムリセツト制御回路。
A system reset control circuit that issues a system reset in response to a system reset issue request in synchronization with a signal indicating a read cycle such as a read signal from a CPU section.
JP8323188U 1988-06-22 1988-06-22 Pending JPH026323U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8323188U JPH026323U (en) 1988-06-22 1988-06-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8323188U JPH026323U (en) 1988-06-22 1988-06-22

Publications (1)

Publication Number Publication Date
JPH026323U true JPH026323U (en) 1990-01-17

Family

ID=31307957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8323188U Pending JPH026323U (en) 1988-06-22 1988-06-22

Country Status (1)

Country Link
JP (1) JPH026323U (en)

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