JPS60175399U - EEPROM write voltage control circuit - Google Patents
EEPROM write voltage control circuitInfo
- Publication number
- JPS60175399U JPS60175399U JP6246084U JP6246084U JPS60175399U JP S60175399 U JPS60175399 U JP S60175399U JP 6246084 U JP6246084 U JP 6246084U JP 6246084 U JP6246084 U JP 6246084U JP S60175399 U JPS60175399 U JP S60175399U
- Authority
- JP
- Japan
- Prior art keywords
- logic
- voltage
- voltage switching
- time
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来例を示す回路図、第2図はこの考案の一実
施例を示す回路図である。
10・・・EEPROM、 20・・・電圧切換回路、
21 ・・・・切換端子、41・・・オーブンコレ々り
形バッフ゛す、CS・・・制御信号、R3・・・電源投
入リセット信号。 、 −FIG. 1 is a circuit diagram showing a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of this invention. 10... EEPROM, 20... Voltage switching circuit,
21...Switching terminal, 41...Oven collector type buffer, CS...Control signal, R3...Power-on reset signal. , −
Claims (1)
OMの書き込み端子に書き込み時の高電圧あるいは読み
出し時の低電圧を供給する電圧切換回路を中心に構成さ
れ、コンピュータシステム側から発生する読み出しモー
ドと書き込みモードを選択するための制御信号−の出力
系と、システム電源の投入時点より一定時間後に出力論
理が変化する電源投入リセット信号の出力系とをワイヤ
ードロジック接続して上記電圧切換端子に接続し、上記
リセット信号が反転するまでの電源投入後の一定時間は
、上記制御信号の論理に係わらず上記電圧切換端子の入
力論理が上記EEPROMに低電圧を供給する側の論理
に固定されるように構成したことを特徴とするEEEF
ROMの書き込み電圧制御回路。EEPR depending on the logic of the signal applied to the voltage switching terminal.
It is mainly composed of a voltage switching circuit that supplies high voltage for writing or low voltage for reading to the write terminal of OM, and is an output system for control signals generated from the computer system side to select read mode and write mode. and the output system of the power-on reset signal whose output logic changes after a certain period of time from the time the system power is turned on, are connected to the above voltage switching terminal by a wired logic connection. The EEEF is characterized in that the input logic of the voltage switching terminal is fixed to the logic for supplying a low voltage to the EEPROM for a certain period of time, regardless of the logic of the control signal.
ROM write voltage control circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6246084U JPS60175399U (en) | 1984-04-27 | 1984-04-27 | EEPROM write voltage control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6246084U JPS60175399U (en) | 1984-04-27 | 1984-04-27 | EEPROM write voltage control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60175399U true JPS60175399U (en) | 1985-11-20 |
Family
ID=30591691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6246084U Pending JPS60175399U (en) | 1984-04-27 | 1984-04-27 | EEPROM write voltage control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60175399U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01269114A (en) * | 1988-04-20 | 1989-10-26 | Mitsubishi Electric Corp | Resetting circuit |
-
1984
- 1984-04-27 JP JP6246084U patent/JPS60175399U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01269114A (en) * | 1988-04-20 | 1989-10-26 | Mitsubishi Electric Corp | Resetting circuit |
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