JPS5832540U - Abnormal signal generation circuit - Google Patents
Abnormal signal generation circuitInfo
- Publication number
- JPS5832540U JPS5832540U JP12498281U JP12498281U JPS5832540U JP S5832540 U JPS5832540 U JP S5832540U JP 12498281 U JP12498281 U JP 12498281U JP 12498281 U JP12498281 U JP 12498281U JP S5832540 U JPS5832540 U JP S5832540U
- Authority
- JP
- Japan
- Prior art keywords
- signal generation
- generation circuit
- abnormal signal
- logic level
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Input From Keyboards Or The Like (AREA)
- Debugging And Monitoring (AREA)
- Stand-By Power Supply Arrangements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す回路図である。
１・・・・・・インバータ、２・・・・・・押釦スイッ
チ、３・・・・・・切換回路、Ｔｉ・・・・・・入力端
子、Ｅ・・・・・・定電圧電源。FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1... Inverter, 2... Push button switch, 3... Switching circuit, Ti... Input terminal, E... Constant voltage power supply.
Claims (1)
子に、その入力をロジックレベル“Ｏ”に切換可能な非
常用の押釦スイッチと、定電圧電源における電圧降下を
検出して上記インバータの入力をロジックレベル“０゛
に切換える検出回路とをワイヤードオアに接続したこと
を特徴とする異常信号発生回路。At the input terminal of the inverter to which logic level "1" is applied, there is an emergency push button switch that can switch the input to logic level "O", and a voltage drop in the constant voltage power supply is detected and the input terminal of the inverter is set to logic level. An abnormality signal generation circuit characterized in that a detection circuit for switching the level to "0" is connected to a wired OR.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12498281U JPS5832540U (en) | 1981-08-24 | 1981-08-24 | Abnormal signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12498281U JPS5832540U (en) | 1981-08-24 | 1981-08-24 | Abnormal signal generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5832540U true JPS5832540U (en) | 1983-03-03 |
Family
ID=29918825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12498281U Pending JPS5832540U (en) | 1981-08-24 | 1981-08-24 | Abnormal signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5832540U (en) |
-
1981
- 1981-08-24 JP JP12498281U patent/JPS5832540U/en active Pending
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