RU2297029C2 - Self-correcting device - Google Patents

Abstract

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains original circuit, four groups of AND elements, group of OR elements, encoding device, register, error syndrome circuit, checks circuit, three decoders, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

Description

The invention relates to computer technology and can be used to increase the reliability of the operation of combinational devices, as well as storage and transmission devices (online and read-only memory computers, etc.).

A self-correcting discrete device [1] is known that uses a decoding device that corrects modular (byte) errors based on the use of Reed-Solomon codes containing the original circuit, the encoding device, the redundant circuit, the decoding device, including the syndrome calculation circuit, the imaginary syndrome shaper, the error decoder in byte, distorted byte calculation circuit, error switches, error corrector, device inputs are connected to the inputs of the original circuit and to the inputs of the encoder, code outputs the switching device is connected to the inputs of the redundant circuit, the outputs of which are connected to the first inputs of the syndrome calculation circuit, the outputs of the original circuit are connected to the second inputs of the syndrome calculation circuit and to the first inputs of the corrector, the outputs of the syndrome calculation circuit are connected to the inputs of the error decoder, the outputs of which are connected to the second inputs corrector, corrector outputs are device outputs.

The disadvantage of this device is the low reliability of the device, since the Reed-Solomon codes allow you to correct the error in one byte of information and detect an error in two bytes of information.

The closest in technical solution is a self-correcting discrete device [2], containing the original circuit, the first coding device, the error syndrome scheme, error decoder, corrector, the second, third and fourth encoding devices, the first to fourth convolution schemes, error symptom scheme, element OR, the inputs of the device are connected to the original circuit and to the inputs of the first encoding device, to the inputs of the second encoding device, and the outputs of the original circuit are connected to the inputs of the third and fourth encoding devices properties to the first inputs of the corrector, the outputs of which are the outputs of the device, the outputs from the first to fourth encoding devices are connected respectively to the inputs from the first to fourth convolution schemes, the outputs of the first and third convolution schemes are connected to the inputs of the error syndrome circuit, the outputs of the second and fourth convolution schemes connected to the inputs of the error flag circuit, the outputs of the error syndrome circuit and the error flag are connected to the inputs of the error decoder, the first group of outputs of the error decoder is connected to the second inputs of the corrector, and the second The output group is connected to the input of the OR element, the output of which is the signal “device failure”.

The disadvantage of this device is the low reliability of operation, since errors that occur simultaneously in information and control discharges are not corrected.

The aim of the invention is to increase the reliability of the device by correcting the maximum number of errors.

This goal is achieved in that the device containing the original circuit, the encoding device, the scheme of the error syndrome, the first decoder, the corrector, the information inputs of the device are connected to the first inputs of the original circuit, the outputs of which are connected to the first inputs of the corrector, the outputs of the corrector are the outputs of the device, characterized in that it additionally contains first to fourth AND elements, an OR element, a register, a test circuit, a second decoder, a third decoder, address inputs, write input, read input, input " drop ", and the information inputs of the device are connected to the first inputs of the first AND element, the address inputs are connected to the second inputs of the original circuit and to the first inputs of the register, the recording input is connected to the third input of the original circuit, to the second input of the first AND element and to the second input of the register, the read input is connected to the fourth input of the original circuit, to the first input of the second element And, to the first input of the third element And, to the first input of the fourth element And to the third input of the register, the input "Reset" is connected to the fifth input of the original c we are connected to the fourth input of the register, the outputs of the original circuit are connected to the first inputs of the verification circuit and to the second inputs of the second AND element, the outputs of which are connected to the first inputs of the OR element, the second inputs of which are connected to the outputs of the first AND element, and the outputs are connected to the inputs of the encoder , the encoder outputs are connected to the second inputs of the third AND element and to the fifth inputs of the register, the first inputs of the error syndrome circuit are connected to the outputs of the third AND element, the second inputs are connected to the register outputs, and the outputs connected to the second inputs of the test circuit and to the inputs of the first decoder, the outputs of which are connected to the first inputs of the third decoder, the outputs of the test circuit are connected to the inputs of the second decoder, the outputs of which are connected to the second inputs of the third decoder, the outputs of the third decoder are connected to the second inputs of the fourth element And, the outputs of which are connected to the second inputs of the corrector.

The drawing shows a block diagram of a device. The device comprises: an initial circuit 1, a first element 2 AND, a second element 3 AND, a third element 4 AND, a fourth element 5 AND, an element 6 OR, an encoding device 7, a register 8, an error syndrome scheme 9, a test scheme 10, a first decoder 11 , the second decoder 12, the third decoder 13, the corrector 14, the information inputs 15, the address inputs 16, the input 17 records, input 18 read, input 19 reset, outputs 20 of the device.

The information inputs 15 of the device are connected to the first inputs of the original circuit 1 and to the first inputs of the first element 2 AND, the outputs of the original circuit 1 are connected to the second inputs of the second element 3 And, to the first inputs of the circuit 10 checks and to the first inputs of the corrector 14, the outputs of the corrector 14 are the outputs of the device 20, the address inputs 16 are connected to the second inputs of the original circuit 1 and to the first inputs of the register 8, the input 17 of the record is connected to the third input of the original circuit, to the second input of the first element 2 And to the second input of the register 8, the input 18 of the reading is connected to h the fourth input of the original circuit 1, to the first input of the second element 3 And, to the first input of the third element 4 And, to the first input of the fourth element 5 And to the third input of the register 8, input 19 "Reset" is connected to the fifth input of the original circuit 1 and to the fourth input of the register 8, the outputs of the second element 3 AND are connected to the first inputs of the element 6 OR, the second inputs of which are connected to the outputs of the first element 2 AND, the outputs are connected to the inputs of the encoder 7, the outputs of the encoder 7 are connected to the second inputs of the third element 4 AND and by the fifth entrance am 8, the first inputs of circuit 9 of the error syndrome are connected to the outputs of the third element 4 AND, the second inputs are connected to the outputs of register 8, and the outputs are connected to the second inputs of the test circuit 10 and to the inputs of the first decoder 11, the outputs of which are connected to the first inputs of the third decoder 13, the outputs of the test circuit 10 are connected to the inputs of the second decoder 12, the outputs of which are connected to the second inputs of the third decoder 13, the outputs of the third decoder 13 are connected to the second inputs of the fourth element 5 And, the outputs of which are connected to the second corrector inputs 14.

Encoding device 7 is intended for:

1) the implementation of right and left diagonal checks based on the use of a group of adders according to mod 2, when recording information, in accordance with the rules presented in the appendix. Diagonal checks form the vector R = r ₁ , r ₂ , ... r _2l ;

2) the formation (in a similar way) of the vector of control bits R ^{P of the} received code set based on information read from the outputs of the original circuit 1.

Thus, during the recording and reading of information at the output of the encoding device 7, we have, respectively, the vectors of the control bits:

R = r ₁ r _{2 ...,} r _2l ,

R ^P = r ^P ₁ r ^P ₂ ... r ^P _2l .

Scheme 9 of the error syndrome is a bitwise comparison scheme and is intended to generate the values of the error syndrome based on the transmitted and received information.

Register 8 is designed to store the values of the signals of the vector of control bits formed when recording information in the original circuit 1.

Scheme 10 checks on the values of the information bits and the values of the bits of the error syndrome forms a vector of additional checks.

The first decoder 11, when an error occurs, generates a single signal at one of its outputs in accordance with the incoming value of the error syndrome.

The second decoder 12 generates a single signal at one of its outputs in accordance with the incoming value of the additional check.

The third decoder 13 according to the values in accordance with the value of the error syndrome and the value of the additional check generates a control signal to the corrector 14 to correct erroneous information bits.

Corrector 14 is designed to correct errors arising at the outputs of the original circuit 1, and implements a function relative to the control signals ui coming from the outputs of the decoder:

The device operates as follows. Before starting work, a signal is input to input 19, which sets the device to its initial state. When input information arrives at information inputs 15, address inputs 16 and the “Record” signal at input 17, the information is recorded at the specified address in the original circuit 1. At the same time, it is fed to the inputs of the first element 2 AND, opened by the signal from input 17, and then through element 6 OR, the input information is input to the encoder 7. The encoder 7, implemented on a group of adders according to mod 2, implements the right and left diagonal checks of the information matrix.

From the outputs of the encoder 7, the value of the vector of control bits is fed to the input of register 8 and is recorded at the specified address.

When reading information at the specified address, the signals from the output of the original circuit 1, through the second element 3 AND, opened by the signal "Read" from input 18, element 6 OR are re-fed to the input of the encoding device 7, where the signal values are generated in the control bits of the diagonal checks obtained information.

At the same time, the information from the outputs of the encoding device 7 is fed to the first inputs of the error syndrome circuit 9, the second inputs of which receive information read from register 8.

As a result, at the output of error syndrome circuit 9, we have the generated value of the error syndrome.

Scheme 10 checks on the values of the information bits and the values of the bits of the error syndrome forms a vector of additional checks according to rule (11), set out in the appendix.

The first decoder 11, when an error occurs, generates a single signal at one of its outputs in accordance with the incoming value of the error syndrome.

The second decoder 12 generates a single signal at one of its outputs in accordance with the incoming value of the additional check.

The third decoder 13 according to the values in accordance with the value of the error syndrome and the value of the additional check generates a control signal to the corrector 14 to correct erroneous information bits.

application

Error correction in one byte and error detection in the remaining bytes of information is achieved on the basis of an iterative code.

The procedure for constructing a two-dimensional iterative code is as follows [3]. A given set of information symbols is divided into groups (blocks, modules) of information, by b-bits in each group. The resulting information modules are presented in the form of an information matrix (1):

Then the information is encoded using the parity method (by adding mod 2 characters of rows and columns of the resulting matrix). As a result, we have a two-dimensional iterative code that allows us to detect and correct any single error:

where H = h ₁ , h ₂ , ... h _m is the line parity vector; Z = z ₁ , z ₂ , ... z _b is the column parity vector. The parity vectors of rows and columns form the set of control bits R ₁ = {r ₁ , r ₂ , r _m , r _{m + 1} , ..., r _b }. Upon receipt of the code combination relative to the information bits, the values of the control bits R ^P ₁ = {r ₁ , r ₂ , r _m , r _{m + 1} , ..., r _b } are re-formed. In this case, the difference between the transmitted values of the control bits and received after receiving the information forms the error syndrome E:

Moreover, the bits of the error syndrome e ₁ e ₂ ... e _m (obtained with respect to the row parity vector) indicate the module of information that has an error, and the bits e _m e _{m + 1} ... e _b (obtained with respect to the column parity vector) indicate erroneous bit in the information module.

Since code combinations of rows and columns have a minimum distance d = 2, the minimum distance of this code is d = 4. This code allows you to correct any single error and detect a significant proportion of multiple errors.

The structures of errors not detected by the two-dimensional iterative code are shown in the figure.

Fig. 1 Structures of errors not detected by a two-dimensional iterative code: a) errors of multiplicity 4; b) - errors of multiplicity 6.

Fig.2 Error structures of a two-dimensional iterative code, leading to erroneous correction: a) errors of multiplicity 5; b) - errors of multiplicity 7.

In the general case, iterative codes of higher dimension can be constructed (three-dimensional, four-dimensional, etc.), where each information symbol will be a component of x different codewords at the same time. The parameters of iterative codes of dimension x are as follows [3]:

where n _i , k _i , d _i are the length, the number of information bits, the minimum distance of the code sets of rows and columns, respectively.

Based on this, to build iterative codes should use checks that have the highest detecting ability.

Thus, the organization of diagonal checks of the matrix under consideration will allow us to identify error structures that are not detected by an iterative code that implements parity checks of rows and columns.

The structure of diagonal checks that detect the considered errors has the form shown in Fig. 3.

Left diagonal checks are formed according to the rule:

The results of the right diagonal checks are formed by summing the values of the following information bits:

In this case, the total number of diagonal checks is 2l, or:

Example 1. Let the word in question consists of four information bits that have zero meanings. For this code set, the information matrix has the form:

In this case, checks for the parity of rows and columns of the information matrix will give zero values, and, in addition, the results of all right and left diagonal checks will have zero values. If an error occurs in all information bits, we have an even error that cannot be detected by a two-dimensional iterative code, because parity checks of rows and columns of the information matrix have zero values:

At the same time, the right and left diagonal checks will give a result of 101.

Proposition 1. An iterative code that implements right and left diagonal checks detects all even errors that are not detected by the two-dimensional iterative code, and identifies odd errors that are perceived by the two-dimensional iterative code as correctable.

In turn, there are error structures that are not detected by iterative code that implements right and left diagonal checks and checks for the parity of rows and columns. The structures of the errors under consideration are presented in Fig.4.

Fig. 4 Structures of errors not detected by diagonal checks and checks of rows and columns.

So, for example, with respect to the information matrix having zero values, the following error structure will not be detected by diagonal checks.

In order to exclude the appearance of the considered errors, the information matrix should contain no more than two rows.

Proposition 2. For an information matrix b × 2, an iterative code that implements right and left diagonal checks detects all possible errors.

Corollary 1. For an information matrix b × 2, an iterative code that implements right and left diagonal checks distinguishes all possible errors.

Statement 3. When conducting diagonal checks for the b × 2 information matrix, errors are detected and distinguished if the number of control bits is equal to:

where k is the number of information bits.

Thus, when using a four-dimensional iterative code, the code set is transmitted in the form:

The result of the addition of the values of the signals of the control bits transmitted and received will give an error syndrome:

where the bits of the error vector r ₁ , r ₂ ...... r _l - correspond to the right diagonal checks; r _l , r _{l + 1} ...... r _2l - left.

For this example, the encoding of information is as follows:

Table 1 shows the values of the error syndrome (relatively error-free zero-set) obtained by conducting the right and left diagonal checks for erroneous sets of the 2 × 2 information matrix (only errors in information bits are considered).

Based on the obtained coding rules, a decoding strategy is formed that solves the problem of distinguishing between errors in information and control bits, and the rules for correcting errors that occur.

For this purpose, regarding the obtained values of the error syndromes, additional checks are organized:

Table 1. No. p / p y1 y2 y3 y4 e1 e2 e3 e4 e5 e6 0 0 0 0 0 0 0 0 0 0 0 one one one 0 0 one one 0 0 one one 2 0 0 one one 0 one one one one 0 3 one one one one one 0 one one 0 one four one 0 one 0 one one 0 one one 0 5 0 one 0 one 0 one one 0 one one 6 one 0 0 one one 0 one 0 0 0 7 0 one one 0 0 0 0 one 0 one 8 one one one 0 one 0 0 one one one 9 one one 0 one one one one 0 0 one 10 one 0 one one one one one one 0 0 eleven 0 one one one 0 0 one one one one 12 one 0 0 0 one 0 0 0 one 0 13 0 one 0 0 0 one 0 0 0 one fourteen 0 0 0 0 one 0 one 0 0 fifteen 0 0 0 one 0 0 one 0 one 0

For the considered example, Table 2 presents the values of the error syndromes and the values of the additional checks obtained with respect to the part of the errors that occur in the information bits, control bits, and simultaneously in the control and information bits.

Analysis of the table allows us to formulate the following statement:

Statement 4. For the b × 2 information matrix, the values of the error syndromes and the values of the additional checks allow us to detect and distinguish errors that occur in the information and control bits.

In this case, to save hardware costs, you should limit yourself to correcting errors only in information bits. Then the required number of error syndrome values (values of additional checks) will be:

From the considered example, it follows that the proposed coding method allows you to correct any possible error in the information bits, with the exception of such combinations of errors in the information and control bits that translate the erroneous code set into allowed, which is a significant drawback of any linear code.

Information sources

1. Scherbakov N.S. The reliability of digital devices. M.: Engineering, 1989, 224 p., Fig. 39, Fig. 44.

2. A positive decision on the application (21) 99111190/09 dated January 15, 03 (filed May 31, 09), authors: Tsarkov AN, Bezrodny B.Yu., Novikov NN, Romanenko Yu.A., Pavlov A.A.

3. Khetagurov Ya.A., Rudnev Yu.P. Improving the reliability of digital devices using redundant coding methods. M .: Energy, 1974, 270 p.

Claims (1)

A self-correcting device containing an encoding device designed to perform right and left diagonal checks and the formation of a vector of control bits, an error syndrome diagram, a first decoder, a corrector designed to correct errors that occur at the outputs of the original circuit, information inputs of the device are connected to the first inputs of the original circuit the outputs of which are connected to the first inputs of the corrector, the outputs of the corrector are the outputs of the device, characterized in that it additionally contains neighbors from the first to the fourth group of AND elements, a group of OR elements, a register, a test circuit, a second decoder, a third decoder, address inputs, a write input, a read input, a Reset input, and the information inputs of the device are connected to the first inputs of the AND elements of the first group , the address inputs are connected to the second inputs of the original circuit and to the first inputs of the register, the recording input is connected to the third input of the original circuit, to the combined second inputs of the elements of the first group and to the second input of the register, the read input is connected to the fourth the input of the original circuit, to the combined first inputs of the elements AND of the second group, to the combined first inputs of the elements AND of the third group, to the combined first inputs of the elements AND of the fourth group and to the third input of the register, the input "Reset" is connected to the fifth input of the original circuit and to the fourth input of the register, the outputs of the original circuit are connected to the first inputs of the test circuit and to the second inputs of the AND elements of the second group, the outputs of which are connected to the first inputs of the group of OR elements, the second inputs of which are connected to the outputs of the first group of elements in And, and the outputs are connected to the inputs of the encoder, the outputs of the encoder are connected to the second inputs of the AND elements of the third group and to the fifth inputs of the register, the first inputs of the error syndrome circuit are connected to the outputs of the third group of And, the second inputs are connected to the outputs of the register, and the outputs connected to the second inputs of the test circuit and to the inputs of the first decoder, the outputs of which are connected to the first inputs of the third decoder, the outputs of the test circuit are connected to the inputs of the second decoder, the outputs of which are connected to the second m inputs of the third decoder, the outputs of the third decoder are connected to the second inputs of the elements of the fourth group, the outputs of which are connected to the second inputs of the corrector.