JP2013187699A - Fpga configuration processing control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high reliability FPGA configuration processing control circuit for configuring an FPGA.SOLUTION: The FPGA configuration processing control circuit for executing an FPGA configuration process includes: a plurality of nonvolatile memories 3-0, 3-1 storing FPGA configuration data; a volatile memory 2 for storing the data from one nonvolatile memory selected by a selector 8; and a configuration processing section 4 including the selector 8 for selecting one from the plurality of nonvolatile memories, a check section 7 for performing an error check on the FPGA configuration data transferred from the selected nonvolatile memory to the volatile memory, a configuration macro 5 for transferring the configuration data from the volatile memory 2 to an FPGA 1 to perform the configuration process, and a control section 6 for, if the check section 7 detects an error in the FPGA configuration data, alternatively selecting another nonvolatile memory to transfer the FPGA configuration data to the volatile memory 2.

Description

  The present invention relates to an FPGA configuration processing control circuit which can execute an automatic reconfiguration control processing of an FPGA and provides a highly reliable FPGA.

  By forming various control circuits, etc. on a semiconductor substrate by including circuit elements including a large number of logic circuits and gate circuits having the same configuration or different configurations, and by forming a connection configuration in the circuit elements and between the circuit elements Various configurations of an FPGA (Field Programmable Gate Array) having a configuration having a desired processing function have already been proposed and put into practical use. 11 shows a main part of a conventional FPGA configuration processing control circuit, 101 is an FPGA, 102 is a processing unit (CPLD), 103 is a non-volatile memory, and Power_ON is operating power. Supply, CRC_ERROR is an error detection signal by CRC (Cyclic Redundancy Check), re_config is a reconfiguration request terminal of the macro 104 for configuration, and reset is a reset terminal for instructing configuration start.

  The FPGA 101 has a configuration in which a plurality of logical blocks are arranged on a semiconductor substrate, for example, in a two-dimensional arrangement, and can be connected to each other by gates and wirings. By performing setting control, a configuration having a desired logic processing function is obtained. In FIG. 11 of this conventional example, the configuration macro 104 is activated by power-on Power_ON, and data including construction data, an address, a control signal, and the like for the FPGA 101 is transferred from the nonvolatile memory 103 to the FPGA 101. Transfer and set the connection configuration, processing function, etc. between the parts of the FPGA 101. When the CRC check error CRC_ERROR in the FPGA 101 is detected, it is transferred to the configuration macro 104 as a reconfiguration request signal re_config, and the FPGA 101 is reconstructed by the configuration macro 104. At the normal end, the CPLD 102 may be reset and disconnected from the FPGA 101, or the connection state may be maintained and the reconstruction process may be enabled when an error is detected.

  FIG. 12 is an operation explanatory diagram of the conventional example in the configuration shown in FIG. 11, and shows an outline of the configuration operation and the normal operation. In the same figure, Power_ON is a power-on, reset is a power-on to reset the configuration macro 104, a reset signal for starting the configuration, and the data direction is the configuration when the FPGA is configured. 11 indicates the data transfer direction from the non-volatile memory to the FPGA, where (non-volatile → FPGA) is the data transfer direction. INIT_DONE indicates the end of configuration, CRC_ERROR indicates an error detection signal, and re_config indicates a process for reconstructing the FPGA 101 using the error detection signal CRC_ERROR from the FPGA. By starting the configuration, the construction data from the non-volatile memory is transferred to the FPGA, the internal configuration is constructed according to the construction data, and the FPGA 101 is reconfigured by the construction process and the error detection signal (CRC_ERROR) after the construction process is completed. Perform configuration. Such a control process can be performed by a function of a configuration macro in the construction data storage unit CPLD.

  The FPGA can be made large-scale by the miniaturization of the semiconductor integrated circuit, and a device having various processing functions can be constructed relatively easily. In a processing apparatus having various functions constituted by such an FPGA, there is a demand for a configuration that can easily cope with occurrence of a failure during system construction or system operation. For example, when a failure occurs in a device part constituted by an FPGA, the route is changed by a modification process of a lookup table (LUT: Look-Up Table) corresponding to a plurality of cells, and a dormant state in the failure occurrence block There are proposed means for isolating the fault location and restoring it to a sound circuit element configuration by a reconstruction process in which the circuit element can be used and a rebuild process by replacing the faulty block with a pause block ( For example, see Patent Document 1). In addition, a plurality of memories for storing configuration data, a main memory and a sub memory, are provided to measure the processing time when the FPGA is constructed by the main memory, and the processing is not completed even if a predetermined time elapses. If this is detected, it is estimated that a failure of the main memory system has occurred, and switching to the sub memory is performed, and means for executing the FPGA construction process again by using this sub memory is also proposed (for example, see Patent Document 2). .

Japanese Patent Laid-Open No. 2001-136058 JP 2010-066961 A

  When constructing a configuration having a desired function by FPGA, if an error occurs due to the influence of external noise or the like, or an error occurs due to garbled construction data stored in the nonvolatile memory, the construction process is executed again from the beginning. become. However, the occurrence of an error when it is temporarily affected by external noise due to external noise or the like can be terminated normally by the reconstruction process, but there is an error in the FPGA construction data stored in the nonvolatile memory. If it is included, there is a problem that normal termination does not occur even if the reconstruction process is repeated. Even when the process is normally completed, there is a problem that an error occurs during the subsequent restructuring process due to the garbled data in the memory for construction due to the influence of external noise such as cosmic rays. In the above-mentioned Patent Document 1, it is possible to change the function or route in correspondence with the cell, and to reconstruct the replaceable function of the failure occurrence part, and to show the general concept of FPGA reconfiguration. However, no means for automating the reconfiguration of the FPGA and improving the reliability is disclosed. Further, the above-mentioned Patent Document 2 shows a case where a plurality of configuration memories are provided to provide a redundant configuration, and shows a simple duplex configuration.

  The present invention solves the above-mentioned problems of the conventional example. A volatile memory and a plurality of non-volatile memories are provided for FPGA configuration, and errors such as external noise caused by FPGA construction data are generated. This makes it possible to avoid the influence and maintain high reliability of the FPGA even after long-term operation.

  An FPGA configuration processing control circuit according to the present invention is an FPGA configuration processing control circuit that executes FPGA (Field Programmable Gate Array) construction processing, and includes a plurality of nonvolatile memories each storing the construction data of the FPGA, A volatile memory that stores data transferred from a selected nonvolatile memory among a plurality of nonvolatile memories, a selector that selects the plurality of nonvolatile memories, and the nonvolatile memory selected by the selector A check unit that performs error checking of FPGA construction data to be transferred to the volatile memory, a configuration macro that transfers the FPGA construction data from the volatile memory to the FPGA, and performs the FPGA construction processing; Data for FPGA construction by the check unit Upon error detection, and a structuring unit that selects the switching control other of the non-volatile memory and a control unit for controlling transfer of data for FPGA build in the volatile memory.

  The construction processing unit transfers the FPGA construction data from the non-volatile memory selected and switched by the selector to the volatile memory. When the check unit detects an error in the FPGA construction data, the construction processing unit transfers the FPGA construction data. By switching to another nonvolatile memory, the FPGA construction data of all addresses stored in the nonvolatile memory is transferred to the volatile memory and overwritten.

  The construction processing unit transfers the FPGA construction data from the nonvolatile memory to the volatile memory, and when the error is detected in the FPGA construction data by the check unit, it is transferred to another nonvolatile memory by the selector. In this configuration, only the data corresponding to the error detection address is transferred to the volatile memory, and the FPGA construction data in the volatile memory is overwritten.

  The construction processing unit, after completion of the FPGA construction process, sequentially switches the plurality of non-volatile memories, transfers the FPGA construction data to the volatile memory, and repeats the process of checking by the check unit Thus, the normality of the plurality of nonvolatile memories is checked.

  The building processing unit performs a rebuilding process using the FPGA building data stored in the volatile memory when an error occurs after the FPGA building process is completed, and when the error occurs due to the rebuilding process, For the volatile memory, one of the plurality of nonvolatile memories is selected, and the FPGA construction processing is performed by the FPGA construction data stored in the nonvolatile memory.

  Store FPGA construction data in multiple non-volatile memories, transfer the FPGA construction data from the selected non-volatile memory to the volatile memory, check the normality of the FPGA construction data, and error If there is not, the construction data is transferred from the volatile memory to the FPGA, and the FPGA construction processing is executed. When an error is detected, the construction data is switched to another nonvolatile memory and the FPGA construction data is transferred to the volatile memory. Then, only when there is no error, the FPGA construction process is executed to improve the reliability of the FPGA. After the FPGA construction, the FPGA construction data stored in the non-volatile memory is transferred to the volatile memory. By repeatedly checking the normality, the reliability of the FPGA construction data can be maintained over a long period of time.

It is explanatory drawing of Example 1 of this invention. It is processing explanatory drawing of Example 1 of this invention. It is processing explanatory drawing of Example 2 of this invention. It is processing explanatory drawing of Example 3 of this invention. It is a principal part flowchart of Example 3 of this invention. It is processing explanatory drawing of Example 4 of this invention. It is a principal part flowchart of Example 4 of this invention. It is processing explanatory drawing of Example 5 of this invention. It is a principal part flowchart of Example 5 of this invention. It is processing explanatory drawing at the time of normal completion of Examples 1-5 of the present invention. It is principal part explanatory drawing of FPGA of a prior art example. It is operation | movement explanatory drawing of a prior art example.

  Referring to FIG. 1, the FPGA configuration processing control circuit according to the present invention is an FPGA configuration processing control circuit that executes construction processing of an FPGA 1 (Field Programmable Gate Array), and stores a plurality of construction data for the FPGA 1. A non-volatile memory 3-0, 3-1, a volatile memory 2 for storing data transferred from a non-volatile memory selected from these non-volatile memories 3-0, 3-1, and a plurality of non-volatile memories A selector 8 for selecting the volatile memory 3-0, 3-1; a check unit 7 for performing an error check on the FPGA construction data transferred from the nonvolatile memory selected by the selector 8 to the volatile memory 2; The FPGA construction data is transferred from the volatile memory 2 to the FPGA 1 to perform the FPGA construction processing. When an error is detected in the FPGA construction data by the configuration macro 5 and the check section 7, a control section 6 that selectively switches other nonvolatile memories and controls transfer of the FPGA construction data to the volatile memory 2. And a construction processing unit 4 including

  FIG. 1 is an explanatory diagram of Embodiment 1 of the present invention, where 1 is an FPGA (Field Programmable Gate Array), 2 is a volatile memory, 3-0 and 3-1 are nonvolatile memories, and 4 is a programmable logic. A control unit (CPLD; Complex Programmable Logic Device), 5 is a configuration macro, 6 is a control unit, 7 is a check unit, 8 is a selector (SEL), and the control unit 6 of the logic control unit 4 is turned on ( Power_ON) has a configuration in which the nonvolatile memory 3-0 and 3-1 read / configuration control (nonvolatile 0/1 read control / Config control) and the selector 8 are controlled, and the selector 8 is controlled. Then, selection switching of the non-volatile memories 3-0 and 3-1 is performed. It is possible to provide a large number of these nonvolatile memories 3-0 and 3-1, each of which stores the same configuration data. However, the two nonvolatile memories 3-0 , 3-1 will be described.

  Also, the check unit 7 performs a check as shown as (Check Sum for each address) for each address of the nonvolatile memory 3-0 or 3-1, which is selectively connected by the selector 8, and a check error occurs. If (Check Sum_ERROR) exists, the control unit 6 is notified. The control unit 6 controls the selector 8 to switch from one of the nonvolatile memories 3-0 and 3-1 to the other, and transfers the FPGA1 construction data to the volatile memory 2 again. Also in this case, the check unit 7 checks the data, and if there is no error, the control unit 6 transfers the construction data from the volatile memory 2 to the FPGA 1 under the control of the configuration macro 5, The construction process of FPGA1 is executed. In the present invention, as described above, the first embodiment in which two nonvolatile memories 3-0 and 3-1 are provided is shown. However, the number of these nonvolatile memories is three or more. When an error is detected, a plurality of non-volatile memories are selected in order, data for FPGA construction is transferred from the selected non-volatile memory to the volatile memory 2, and the data It is also possible to adopt a configuration for performing a check.

  FIG. 2 is an explanatory diagram of processing according to the first embodiment of the present invention, and shows a state corresponding to the symbol in FIG. 1. Power_ON is a logic control unit (hereinafter referred to as “CPLD” shown in FIG. 1). ) Indicates the power-on state for 4. Note that the operation power is also supplied to the FPGA 1. SEL is a selection state of the non-volatile memories 3-0 and 3-1 by the selector 8 (non-volatile 0 → volatile indicates the data transfer direction from the non-volatile memory 3-0 to the volatile memory 2, and non-volatile 1 → volatile. Indicates a data transfer direction from the nonvolatile memory 3-1 to the volatile memory 2). Check Sum_ERROR indicates the presence or absence of an error (Error) in the check result by the check unit 7. The data direction indicates the configuration data transfer direction (volatile → FPGA; the data transfer direction from the volatile memory 2 to the FPGA 1), and reset is the configuration of the FPGA 1 in addition to the configuration macro 5 from the control unit 6. A reset signal for starting, INIT_DONE is a completion signal indicating that the configuration is complete, CRC_ERROR is a CRC error signal, and No Error indicates no error. In addition, re_config indicates a request signal for reconfiguration processing from the control unit 6 to the configuration macro 5, and FIG. 2 indicates a case where this request signal is not present.

  It is divided into a nonvolatile data copy period by power-on Power_ON, a subsequent configuration period, and a normal operation period after the configuration is completed. The nonvolatile data copy period is first set to power-on Power_ON. Then, the non-volatile memory 3-0 is selected by the selector 8, and the non-volatile memory 3-0 is selected and data is transferred to the volatile memory 2 as shown as (non-volatile 0 → volatile). In the transfer process, if the error is detected by the check unit 7 and the error is detected, the check is also performed at the time of data transfer of all addresses, and then the control unit 6 controls the selector 8 to (nonvolatile 1 → As shown by “volatilization”, one nonvolatile memory 3-0 is switched to the other nonvolatile memory 3-1, and the configuration data is transferred to the volatile memory 2. If no error is detected, the reset signal (reset) is turned on to start the configuration.

  Then, data is transferred from the volatile memory 2 to the FPGA 1 under the control of the configuration macro 5, and when the construction of the desired processing function of the FPGA 1 is completed, the configuration is completed by the completion signal INIT_DONE, and then CRC_ERROR In the normal operation when no error is detected, the selector SEL detects an error with respect to the nonvolatile memory 3-0 in which an error was detected during the nonvolatile data copy period, as shown as nonvolatile 1 → nonvolatile 0. The data of all addresses is transferred from the non-volatile memory 3-1, which has not been checked, and in the transfer process, the check unit 7 checks to confirm the normality of the configuration data. , Nonvolatile 0 → volatile, ... nonvolatile 1 → volatile, as shown All the addresses of the data -0,3-1, to the volatile memory 2 is transferred alternately, in the the transfer process is repeated checks by the checking unit 7. Therefore, the normality of the configuration data when the FPGA 1 is reconstructed can be ensured, and the reliability can be improved. In the case where a larger number of nonvolatile memories are provided, the configuration data for all addresses of the selected nonvolatile memory is transferred to the volatile memory in the same manner, and the normality is confirmed by the check unit 7. .

  FIG. 3 is an explanatory diagram of processing of the second embodiment of the present invention. The same reference numerals as those in FIG. 2 correspond to the same names or the same contents, and the period of nonvolatile data copy, configuration, and normal operation by power-on Power_ON. During the nonvolatile data copy period, the selector SEL (selector 8 in FIG. 1) selects the nonvolatile memory 3-0 by the selector SEL (selector (SEL) 8) as shown as nonvolatile 0 → volatilization. Then, when data is transferred from the nonvolatile memory 3-0 to the volatile memory 2 and the check unit 7 detects a checksum error Check Sum_ERROR as shown as Error, the address of the data in which the error is detected Only the data at the same address is read from the non-volatile memory 3-1, and sent to the volatile memory 2 (non-volatile 1 → To transfer as shown as issued). If no error is detected in the transfer processing process, the FPGA 1 is constructed from the data from the volatile memory 2 by the configuration start, and the normal nonvolatile memory 3- 1 is copied to the nonvolatile memory 3-0 in which an error has been detected and then restored, and thereafter, the nonvolatile memory 3-0 is volatile from the nonvolatile memory 3-0 as in the normal operation period shown in FIG. The data is transferred to the memory 2 and the presence or absence of an error is checked by the check unit 7. If normal, it is switched to the nonvolatile memory 3-1, and the same check is repeated. Therefore, the error processing time in the nonvolatile data copy period can be shortened. In addition, after the configuration is completed, the normality of the configuration data held in the non-volatile memories 3-0 and 3-1 is repeatedly confirmed. Therefore, a reconstruction process due to a failure or the like during the operation of the FPGA 1 is performed. Time reliability can be improved.

  FIG. 4 is a process explanatory diagram of Embodiment 3 of the present invention. The same reference numerals as those in FIGS. 2 and 3 denote the same name portions, and in the process of nonvolatile data copy, configuration, and normal operation, FIG. When the configuration of the FPGA 1 is completed, the control unit 6 controls the selector 8 to select any one of the waiting non-volatile memories 3-0 and 3-1, and the selection is made. The data is read from the non-volatile memory, and an error check is performed by the check unit 7 using the checksum of the data corresponding to the address. If no error is detected, the other non-volatile memory is selected by the selector 8 and the selected non-volatile memory is selected. The data is read from the memory, and an error check is performed by the check unit 7. If no error is detected, the nonvolatile memory is read again. Repeating the reading and error checking by-option. Then, when the CheckSum Error detection detects an error in the data read from the non-volatile memory 3-1 shown as non-volatile 1 → volatile, the address data at the time of error detection is shown in the non-volatile memory as shown as non-volatile 0 → non-volatile 1. The data is read from 3-0, overwritten on the address where the error occurred in the nonvolatile memory 3-1, and restored to normal data. As a result, the data in the nonvolatile memories 3-0 and 3-1 can always be maintained in a normal state, and the reliability can be improved during the rebuilding process of the FPGA 1.

  FIG. 5 is a flowchart showing the main part of the third embodiment of the present invention described above. FIG. 5 shows the main part of the process during the construction of the FPGA. With reference to FIGS. 1 and 4, the configuration of the FPGA 1 will be described. After the completion, under the control of the control unit 6 of the CPLD 4, data is read from the nonvolatile memory 3-0 and written to the volatile memory 2 as shown as nonvolatile 0 → volatile copy (a1). In FIG. 4, it is represented as nonvolatile 0 → volatile (a1). Then, it is checked by the check unit 7, and when there is no Check Sum error (a 2), it switches to the nonvolatile memory 3-1, and nonvolatile 1 → volatile copy (a 3), that is, data is stored from the nonvolatile memory 3-1. Read, write to the volatile memory 2, check by the check unit 7, and if there is a Check Sum error (a4), in order to restore the data in the nonvolatile memory 3-1, the nonvolatile 0 → nonvolatile 1 copy (a5 ), The data in the nonvolatile memory 3-1 is restored as shown as (Nonvolatile 1 Repair), and the restored data in the nonvolatile memory 3-1 is copied to the volatile memory 2 (a6). The data copied from the non-volatile memory 3-1 to the volatile memory 2 is repaired to determine whether there is an error due to Check Sum. And, by no error (a7), by the process of the next nonvolatile 0 → volatile copy (a8), to check the health of the non-volatile memory 3-0. By repeating such processing, it is possible to continue to check the normality of the construction data of the FPGA 1 stored in the non-volatile memories 3-0 and 3-1, and even by rebuilding during long-term operation. A highly reliable FPGA can be provided.

  FIG. 6 is an explanatory diagram of processing according to the fourth embodiment of the present invention, showing processing when an error (CRC_ERROR) is detected after completion of FPGA configuration processing, such as nonvolatile data copy, configuration, normal operation, etc. The case where repetition is performed is shown. Referring also to the configuration shown in FIG. 1 described above, by selecting Power_ON, the nonvolatile memory 3-0 is selected by the selector 8 (SEL) of the CPLD 4 so that the nonvolatile memory 3-0 is selected and the data is transferred to the volatile memory 2. If there is no Check Sum_ERROR by the check unit 7 (No ERROR), the configuration is started and the data is transferred from the volatile memory 2 to the FPGA 1 as indicated by volatile → FPGA. If not, the configuration is complete. In the case of CRC_ERROR detection (Error) as an error occurrence in the FPGA 1 during normal operation, reconfiguration (re_config) is performed. In this case, the error is not a data abnormality in the volatile memory 2 but is mostly caused by the influence of noise or the like in the FPGA 1. Therefore, the data held in the volatile memory 2 is transferred to the FPGA 1 (volatile → FPGA), and FPGA1 is reconstructed. However, if the volatile memory 2 is damaged, CRC_ERROR is detected again even if re-configuration is executed. In this case, first, data is copied from the non-volatile memory 3-0 to the volatile memory 2, and it is confirmed by the check unit 7 that there is no error, and then the data in the volatile memory 2 is transferred to the FPGA1. Perform the rebuild process. Even when the CRC_ERROR is detected during normal processing and the volatile memory 2 is further damaged, high reliability can be provided by the normal nonvolatile memories 3-0 and 3-1.

  FIG. 7 is a main part flowchart of the fourth embodiment of the present invention. In normal operation after building the FPGA (b1), the FPGA 1 notifies that there is an error by CRC_ERROR (b2), and reconfiguration is started. (B3). When CRC_ERROR is present again (b4), as shown as (volatile error), as a data error of the volatile memory 2, as shown as nonvolatile 0 → volatile copy (volatile repair) (b4), the nonvolatile memory 3- Data is copied from 0 to the volatile memory 2, data recovery is performed on the volatile memory 2, and reconfiguration is performed (b6). As a result, there is no CRC_ERROR error from the FPGA 1 (b7), and the normal operation (b8) can be entered.

  FIG. 8 is a process explanatory diagram of the fifth embodiment of the present invention, and will be described with reference to the configuration of FIG. Power_ON, SEL (selector 8 state), Check Sum_ERROR (processing by the check unit 7), data direction (data for construction processing) in the repeated state of the nonvolatile data copy, configuration, and normal operation periods (Transfer direction), reset is a signal for notifying the configuration macro 5 from the control unit 6 of configuration start, INIT_DONE is a configuration completion notification signal, CRC_ERROR is an error signal in the FPGA, and re_config is The reconfiguration signal is shown. After completion of the configuration process of the FPGA 1, when the CRC_ERROR is detected in the FPGA 1, the nonvolatile memory 3-0 selected by the selector 8 (SEL), for example, is indicated as non-volatile 0 → volatile as in the case of power-on Power_ON. The data is copied from the volatile memory 2 to the volatile memory 2 and checked by the check unit 7. If there is no error, the configuration starts as shown in the data direction volatilization → FPGA. If there is no error, the configuration is completed. . In the fifth embodiment, the reliability of data stored in the nonvolatile memories 3-0 and 3-1 is higher than that of the volatile memory 2, so that the rebuilding process of the FPGA 1 can be performed quickly and reliably. Can be maintained and executed.

  FIG. 9 is a flowchart showing the main part of the fifth embodiment of the present invention. In the normal operation state of the FPGA (c1), if there is an error detection indicating that there is a CRC_ERROR error (c2), nonvolatile 0 → volatile copy ( Volatile repair) (c3), for example, when data is copied from the non-volatile memory 3-0 to the volatile memory 2 and an error is included in the volatile memory 2 before, Then, reconfiguration is performed (c4). When this reconfiguration results in no CRC_ERROR (c5), the FPGA 1 can return to normal operation (c6).

  FIG. 10 is a diagram for explaining normal processing in each of the above-described embodiments including the above-described fifth embodiment. The same reference numerals as those in the above-described processing explanation diagrams indicate the same name portion and data. The non-volatile data copy, configuration, Power_ON, SEL, Check_Sum_ERROR, data direction, reset, INIT_DONE, CRC_ERROR, and re_conig during normal operation. Referring to FIG. 1, when Power_ON is started to supply power, the selector 7 (SEL) transfers data from the nonvolatile memory 3-0, which is indicated as nonvolatile 0 → volatile, to the volatile memory 2, and the check unit If no error is detected (No Error), the data is transferred from the volatile memory 2 to the FPGA 1 as shown in the configuration start, as indicated by volatilization → FPGA, and the CRC_ in the FPGA 1 When there is no ERROR (No Error), the configuration is completed, and the FPGA 1 can shift to normal operation. During the normal operation in this case, as shown as non-volatile 0 → volatile and non-volatile 1 → volatile. Transfer and write data from memory 3-0 to volatile memory 2 and check A check is performed by the unit 7 using a checksum or the like, and then data is transferred from the non-volatile memory 3-1 to the volatile memory 2 and checked periodically.

1 FPGA (Field Programmable Gate Array)
2 Volatile memory 3-0, 3-1 Nonvolatile memory 4 CPLD (Complex Programmable Logic Device)
5 Configuration Macro 6 Control Unit 7 Check Unit 8 Selector (SEL)

Claims (5)

In an FPGA configuration processing control circuit that executes construction processing of an FPGA (Field Programmable Gate Array),
A plurality of nonvolatile memories each storing the construction data of the FPGA;
A volatile memory storing data transferred from a selected non-volatile memory of the plurality of non-volatile memories;
A selector that selects the plurality of nonvolatile memories; a check unit that performs error checking of FPGA construction data transferred from the nonvolatile memory selected by the selector to the volatile memory; and the volatile memory to the FPGA. A configuration macro for transferring the FPGA construction data and performing the FPGA construction processing, and an FPGA construction by selectively switching other nonvolatile memories when the check unit detects an error in the FPGA construction data An FPGA configuration processing control circuit comprising: a construction processing unit including a control unit that controls transfer of data to the volatile memory.   The construction processing unit transfers the FPGA construction data from the non-volatile memory selected and switched by the selector to the volatile memory. When the check unit detects an error in the FPGA construction data, the construction processing unit 2. The configuration according to claim 1, further comprising: switching to the non-volatile memory, transferring the FPGA construction data of all addresses stored in the non-volatile memory to the volatile memory, and overwriting the data. FPGA configuration processing control circuit.   The construction processing unit transfers the FPGA construction data from the nonvolatile memory to the volatile memory, and when the error is detected in the FPGA construction data by the check unit, it is transferred to another nonvolatile memory by the selector. 2. The configuration according to claim 1, wherein switching is performed to transfer only the data corresponding to the error detection address to the volatile memory, and the FPGA construction data in the volatile memory is overwritten. FPGA configuration processing control circuit.   The construction processing unit, after completion of the FPGA construction process, sequentially switches the plurality of non-volatile memories, transfers the FPGA construction data to the volatile memory, and repeats the process of checking by the check unit The FPGA configuration processing control circuit according to claim 1, further comprising a configuration for checking normality of the plurality of nonvolatile memories.   The building processing unit performs a rebuilding process using the FPGA building data stored in the volatile memory when an error occurs after the FPGA building process is completed, and when the error occurs due to the rebuilding process, A configuration is provided in which one of the plurality of nonvolatile memories is selected for the volatile memory, and the FPGA construction processing is performed by the FPGA construction data stored in the nonvolatile memory. The FPGA configuration processing control circuit according to claim 1.

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