JP6038706B2 - FPGA with two-wire inspection circuit - Google Patents

Description

The present invention relates to a two-wire inspection circuit-mounted FPGA in which a two-wire inspection circuit incorporated in a fail-safe comparison circuit or the like is formed into an LSI using a single-chip / one-chip look-up table type field programmable gate array.
The two-wire inspection circuit is a logic circuit that checks whether or not the comparison / verification target data pair is matched, and all bit pairs to be compared under one-side inversion become normal codewords having different values of 2 bits. If it is, that is, if the code word is “01” or “10” in the 2-bit codeword, one regular codeword “01” or “10” is output. Of the code word, that is, a 2-bit code word, “00” or “11” is output.
A look-up table type field programmable gate array (also referred to as LUT type FPGA or simply FPGA in this specification) is a look-up table such as an SRAM that can write a general logic that can write a logical function corresponding to a multi-input single-output combinational circuit. It is a general-purpose IC embodied in (herein simply referred to as LUT).

  Multiple-system computers used in the railway signal control field, such as railway signal security systems, output two-line inspection circuits that compare bus line information of multiple computers (computers, CPUs) and the results as alternating signals. A bus verification circuit combined with a pendulum circuit is provided, and the LSI is also realized. That is, for example (see Patent Documents 1 to 5), a two-wire inspection circuit that inputs and outputs input / output information of each of a pair of computers that operate in synchronization and compares the input / output information pairs, and the input / output information pair are one. A pendulum circuit that outputs an alternating signal corresponding to the input / output information when it does, but stops outputting the alternating signal when the input / output information pair does not match, and the two-wire inspection circuit and the pendulum circuit, A bus verification circuit including a single-chip (one-chip) semiconductor integrated circuit device (LSI, IC) is put into practical use and applied to a fail-safe computer or the like.

6A and 6B show the structure of a conventional basic bus verification circuit, where FIG. 6A is a block diagram of the bus verification circuit 10, FIG. 6B is a block diagram of the two-wire inspection circuit 15 and the pendulum circuit 16, and FIG. FIG. 3 is a circuit diagram of a basic narrowing circuit 20. FIG. 7A is a circuit diagram of the narrowing circuit halves 21 to 23 occupying half of the narrowing circuit 20, and the narrowing circuit halves 24 to 26 having the same configuration occupying the other half are also shown in parentheses. Is shown. FIG. 5B is a circuit diagram of the narrowing circuit halves 27 to 29 which is equivalent to the narrowing circuit halves 21 to 23 or 24 to 26 but is embodied in a different manner.
Since their configurations and the like are known in detail (see, for example, Patent Documents 1 and 2), here, a portion useful for understanding the present invention to be described later will be scratched and described.

  The bus verification circuit 10 (see FIG. 6A) includes first latch units 11 and 12 for inputting the input / output information Da from the A system CPU (first computer), that is, the A system latch control circuit 11 and A. System latch circuit 12, second latch units 13 and 14 for inputting input / output information Db from B system CPU (second computer), that is, B system latch circuit 13 and B system latch control circuit 14, and A system latch The input / output information Da is input from the circuit 12 and the input / output information Db from the B-system latch control circuit 14 is bit-inverted (indicated by Db with an upper line in the figure. Input / output information Db￣) and the input / output information pair Da, Db (comparison target data pair) are compared, and the two-wire inspection circuit 15 compares the comparison result with the comparison result. When the output code word “XY” output by the two-wire code is input and the output code word “XY” is the normal code word “01” or “10”, the alternating code corresponding to the input / output information pair Da, Db When the output codeword “XY” is a non-canonical codeword “00” or “11”, the pendulum circuit 16 that stops the output of the alternating signal and the final collation result are output as a relay signal. Therefore, a normal relay R that is driven by the alternating signal detection circuit 17 and is excited / de-energized according to the presence / absence of the alternating signal output is provided.

The two-wire inspection circuit 15 (see FIG. 6B) is a series of basic narrowing circuits 20 connected in a tree-like multi-row multi-stage, and the basic narrowing circuit 20 (see FIG. 6C). ), The two input codewords “AB” and “CD” are aggregated into one codeword “EF” and output. However, if the two input codewords are both regular codewords, For example, one normal codeword is output, and one non-normal codeword is output otherwise.
In the two-wire code used in the two-wire inspection, the normal bit value “0” corresponds to the bit pair “01”, and the normal bit value “1” corresponds to the bit pair “10”. Only the bit pairs of the two bits, that is, the code words having different values of 2 bits are regarded as normal code words. The other bit pairs “00” and “11”, that is, codewords having the same value of 2 bits are regarded as non-normal codewords.

  The two-wire inspection circuit 15 showing a specific example (see FIG. 6B) is for both the A system CPU and the B system CPU when the number of data bus lines is 8, and the input / output of the A system CPU. 8-bit data Da0 to Da7 forming information Da and 8-bit data Db0 to Db7 ￣ forming input / output information Db￣ obtained by bit-inverting the input / output information Db of the B-system CPU (in the figure, Db0, Db7 etc., but in this specification, bit data Db0￣, Db7￣ etc.) are input as 8 pairs of two-line codes in association with each bit, The four narrowing circuits 20 narrow down to four pairs of two-wire codewords, and the two second-stage narrowing circuits 20 narrow down to two pairs of two-wire codewords. One narrowing circuit 20 narrows down to a pair of two-wire codewords and outputs them as output codes It adapted to deliver to the pendulum circuit 16 as "XY". Such a two-wire inspection circuit 15 inputs the input / output information Da of the A system CPU and the input / output information Db of the B system CPU, and inputs the input / output information pair Da, Db (comparison target data pair) into the two lines. A two-line inspection method is used after making the expression code, and a normal code word is output when the input / output information pair Da and Db match, but a non-normal code word is output when they do not match. If the number of bus lines is other than 8 bits, the number of stages and the number of columns of the narrow-down circuit 20 may be increased or decreased according to the number of lines.

  In addition, the first latch units 11 and 12 and the second latch units 13 and 14 provided in front of the two-wire inspection circuit 15 (see FIG. 6A) are not essential for the implementation of the two-wire inspection. Although not provided, many are provided for comparison timing matching and the like. The A-system latch circuit 12 temporarily holds the input / output information Da of the A-system CPU and sends it to the two-wire inspection circuit 15. The A-system latch control circuit 11 is given from the outside or generated internally. The latch operation of the A-system latch circuit 12 is controlled based on the clock CLK and the data read control signal RDa and data write control signal WRa of the A-system CPU. The B-system latch circuit 13 temporarily holds the input / output information Db of the B-system CPU and sends it to the two-wire inspection circuit 15. The B-system latch control circuit 14 includes the clock CLK and the B-system CPU. The latch operation of the B system latch circuit 13 is controlled based on the data read control signal RDb and the data write control signal WRb. In the example shown in the figure, the B-system latch circuit 13 inverts the input / output information Db to make the input / output information Db￣ and then sends it to the two-wire inspection circuit 15, but instead, The A-system latch circuit 12 may invert the output, and the two-wire inspection circuit 15 may invert one of the input / output information pairs Da and Db at the time of input.

  The pendulum circuit 16 (see FIG. 6B) receives the output codeword “XY” of the two-wire inspection circuit 15, and whether or not it is a regular codeword “01” or “10”. A code word detection circuit for detecting whether the code word is “00” or “11” and a flip-flop FF for latching the detection result are provided. While the state where the input / output information pair Da and Db match and the output code word “XY” becomes the normal code word “01” or “10” continues, the output signal of the flip-flop FF and thus the pendulum circuit 16 Z becomes an alternating signal, but if the output code word “XY” becomes an irregular code word “00” or “11” because the input / output information pair Da, Db does not match, the output signal Z is an alternating signal. A pendulum circuit 16 is formed so as not to be a signal.

  Further description will be given of the narrowing circuits 20 incorporated in the two-wire inspection circuit 15 (see FIG. 6B) (see FIGS. 6 and 7). One narrowing circuit 20 has four inputs and two outputs. (Refer to FIG. 6C), and in the comparison and collation of the input / output information pair Da and Db (comparison target data pair) (see FIG. 6B), four inputs A, B, C, and D The narrowing circuit 20 to which the bit data Da0, Db0￣, Da1, Db1￣ are input as the two outputs E, F only when the bit pair Da0, Db0￣ and the bit pair Da1, Db1￣ are all normal code words The narrow-down circuit 20 to which the normal code word is outputted and the bit data Da2, Db2￣, Da3, Db3￣ is inputted as the four inputs A, B, C, D is the bit pair Da2, Db2￣ and the bit pair Da3 Db3￣ is a regular codeword A normal code word is output as only two outputs E and F, and the other narrowing circuit 20 similarly outputs two outputs E only when two sets of normal code words are input as four inputs A, B, C, and D. , F are output as normal code words, and in other cases, non-normal code words are output.

  Such a narrowing circuit 20 (see FIGS. 6 (c) and 7 (a)) is a narrowing circuit that generates one output E of two outputs E and F from four inputs A, D, B, and C. The narrowing circuit halves 24 to 26 for generating the other one output F of the two outputs E and F from the four inputs C, A, D, and B, and the narrowing circuit halves 21 to 23 , 24-26 have the difference that the inputs are interchanged, but each of the narrowing circuit halves 21-23, 24-26 has three logic elements [21, 22, 23], [24, 25, 26]. Each of the logic elements 21, 22, and 23 may be a gate with two inputs and one output, and is a half of a narrow-down circuit that uses two AND gates 21 and 22 and one OR gate 23 as the three logic elements 21, 22, and 23. 21 to 23 (refer to FIG. 7A), and another narrowing-down circuit halves 27 to 29 using NAND gates for any of the three logic elements 27, 28, and 29 are known (FIG. 7B). )reference).

  Here, with respect to a general general-purpose LUT type FPGA (lookup table type field programmable gate array), a part useful for understanding the present invention to be described later will be described. 8 is a schematic configuration diagram of a general LUT type FPGA 30. FIG. 9A is a block diagram of the general-purpose logic unit 32, FIG. 8B is a block diagram of the logic element 33, and FIG. An example of the LUT (look-up table) pair 34, 34 embodying the circuit 20, and (d), (e) are examples of the LUT 34 embodying the narrowing circuit halves 21-23.

  The LUT-type FPGA 30 includes a large number of in-device wirings 31 and general-purpose logic units 32 arranged vertically and horizontally (see FIG. 8), and each of the general-purpose logic units 32 includes a large number of logic elements 33 ( The logic element 33 includes an LUT 34 and a register (flip-flop) 35 (see FIG. 9B). A logic operation value is written in the LUT 34 to obtain a desired logic function / combination circuit. In addition, the user can mount a desired digital circuit on a one-chip IC / single-chip LSI by appropriately connecting these and external input / output terminals via the device internal wiring 31. Yes. When constructing the sequential circuit, the register 35 is also used together with the LUT 34.

Since the LUT 34 is generally composed of a 4-input 1-output or 6-input 1-output SRAM (see, for example, paragraph 0002 of Patent Document 6), when the two-wire inspection circuit 15 is mounted on the LUT-type FPGA 30, It is natural to mount the input / output narrowing circuit halves 21 to 23 in one LUT 34, and the LUT 34 can be used without waste.
As a specific example (see FIG. 9C), the LUT 34 including the narrowing circuit halves 21 to 23 that generate one output E from four inputs A, B, C, and D has four inputs A, B, 1 bit value “0”, “0”, “0”, “0”, “0”, “0”, “1” for each address from “0000” to “1111” with C and D as 4-bit addresses “1”, “0”, “1”, “0”, “1”, “0”, “1”, “1”, “1” are written.

Further, another LUT (34) equipped with the narrowing circuit halves 24 to 26 that generate one output F from four inputs A, B, C, and D (see FIG. 9 (c), broken line frame portion) is also 4 1-bit values “0”, “0”, “0”, “0”, “0”, “1” for each address from “0000” to “1111” with inputs A, B, C, and D as 4-bit addresses , “0”, “1”, “0”, “0”, “1”, “1”, “0”, “1”, “1”, “1” are written.
In this case, when the four inputs A, B, C and D are “0101”, “0110”, “1001” and “1010”, the two outputs E and F are “01”, “10” and “10”, respectively. Although it becomes a normal code word “01” (see FIG. 9C), the other two outputs E and F become non-normal code words “00” or “11” (FIG. 9C × reference).

Further, it is known that the LUT type FPGA 30 may generate a soft error (SER) in which the data value written in the LUT 34 is undesirably reversed due to the influence of cosmic rays or radiation (for example, Patent Document 7). (See paragraphs 0018-0023).
As a specific example, when the data value of the address “0110” of the LUT 34 in which the narrowing circuit halves 21 to 23 are mounted is changed from “1” to “0” (see FIG. 9D), or the narrowing circuit A case where the data value of the address “0111” of the LUT 34 on which the halves 21 to 23 are mounted is changed from “1” to “0” (see FIG. 9E *).
Such a soft error is a single phenomenon failure (Single-Evennt Upset), the occurrence probability at one place is small, and the probability that the data value is inverted at a plurality of places is even smaller.

JP-A-61-201342 JP 04-119435 A JP 2002247701 A JP 2002-31254 A JP 2006-338094 A Japanese Patent No. 3412731 Japanese Patent Application Laid-Open No. 2008-065598

However, although the probability of occurrence of a soft error is small, the two-wire inspection circuit is used for fail-safe, and therefore the operating state must be maintained on the safe side even when the circuit fails.
However, in a normal mounting mode in which one half of the narrowed-down circuit is written in each LUT of the above-described LUT type FPGA, depending on the occurrence location of the soft error, there is a case where the circuit failure due to the occurrence is not manifested and may become latent. In that case, there is a possibility that the mismatch of the comparison / verification target data pair may be missed.

  Specifically, in the above example, in the case where a circuit failure becomes obvious, the comparison / verification target such as the A-system CPU and the B-system CPU is still normal, and there is one comparison / verification target data pair such as the input / output information pair Da, Db. When the data values of the four inputs A, B, C, and D, which are the addresses of the LUT 34 on which the narrowing circuit halves 21 to 23 are mounted, are inverted from “1” to “0” ( Since this data value forms half of the normal code word “10” (see FIG. 9C), the output of the narrowing circuit halves 21 to 23 and the narrowing circuit 20 are shown. Since the output of the two-wire inspection circuit 15 and the output of the two-wire inspection circuit 15 are changed to non-regular codewords, a failure becomes apparent in the form of detection of a mismatch between the comparison verification target data pairs.

  Next, as an example of a potential circuit failure, the data values of 4 inputs A, B, C, and D, which are addresses of the LUT 34 equipped with the narrowing circuit halves 21 to 23, are “0111”. When inverted to “0” (see FIG. 9 (e) *), this inverted data value forms half of the non-normal codeword “11” (see FIG. 9 (c)), and the comparison / collation target is Since it is not yet accessed in a normal state where the comparison / verification target data pair is matched, a failure becomes latent. Moreover, when the comparison / collation target becomes abnormal and the above inverted data value is accessed due to the mismatch of the comparison / collation target data pair (see FIG. 9 (e) *), the output of the corresponding narrowing-down circuit 20 is the original value. Since the correct non-canonical code word “11” (see FIG. 9C) becomes a wrong normal code word “01” due to a soft error, not only does the failure continue to become latent, but there is a risk of erroneous detection.

In this way, in the normal mounting mode in which one half of the narrowing circuit is written in each LUT of the LUT type FPGA, the memory access of the LUT is a so-called codeword-dependent type in which the memory access is concentrated on codewords. It turned out that the soft error of the writing part became latent. Moreover, this latentization continues until a mismatch occurs in the comparison / verification target data pair even when a countermeasure against false detection such as duplication of the two-wire inspection circuit and confirmation of matching is taken. For this reason, the possibility of a soft error occurring in the other two-wire inspection circuit cannot be ignored while the soft error is latent in one of the two-wire inspection circuits that have been duplicated. When a soft error occurs at a location where an irregular code word is written in the inspection circuit, there is a risk that the function of erroneous detection due to duplication may be lost depending on the occurrence.
Therefore, it is a technical problem to realize a two-wire inspection circuit mounted FPGA in which a soft error of the LUT becomes obvious by devising the contents written in the LUT.

  The FPGA equipped with a two-wire inspection circuit of the present invention (Solution 1) was created in order to solve such a problem, and is composed of a combinational circuit of two-input and one-output logic elements, and is a comparison / verification target data pair. A two-wire test circuit that outputs 2-bit different-value normal codewords when all the bit pairs are 2-bit different-value normal codewords, and outputs 2-bit equivalent-value non-normal codewords in other cases In a two-wire inspection circuit-equipped FPGA mounted on a lookup table type field programmable gate array having a large number of lookup tables with multiple inputs of 4 or more, write any one of the logic elements in the lookup table. Each of the embedded devices is characterized in that the reading locations are limited to four locations corresponding to addresses in any of the two-input all bit patterns of the logic element. That.

  Further, the two-wire inspection circuit mounted FPGA of the present invention is (Solution Unit 2), which is the two-wire inspection circuit mounted FPGA of the above Solution Unit 1, and writes any one of the logic elements in the lookup table. All of the mounted devices are multi-input, one-output devices, and each of the logic elements is written and mounted in each look-up table.

  Further, the two-wire inspection circuit mounted FPGA according to the present invention is (solution 3), the two-wire inspection circuit mounted FPGA of the above solution 1, 2, and any one of the logic elements in the lookup table. A fixed value is inputted to a place where none of the two inputs of the logic element is inputted among the multi-inputs of the mounted writing.

In such a two-wire test circuit-equipped FPGA of the present invention (Solution 1), read access to the LUT on which the logic element of the two-wire test circuit is mounted is all bits of two inputs of the mounted logic element. It is limited to four locations corresponding to addresses in any of the patterns.
On the other hand, regarding the comparison / verification target data pair input to the two-wire inspection circuit, when the four inputs of each narrowing circuit are viewed, only the normal code word is input in the normal state as described above. When the input is viewed, not the bit pair to be compared but the adjacent bits are input, and therefore, depending on the data value, a 2-bit all bit pattern is input even in a normal state. Also, with respect to two inputs of other logic elements, depending on the output of the preceding logic element, a 2-bit all-bit pattern is input even in the normal state.

As described above, the read access is limited to the four places that can be accessed even in the normal state depending on the data value. When the occurrence occurs, the two-wire inspection circuit outputs a mismatch detection depending on the data value, regardless of where the occurrence occurs, even if the input comparison target data pair matches. The failure becomes obvious.
Therefore, according to the present invention, it is possible to realize a two-wire inspection circuit-mounted FPGA in which a soft error of the LUT becomes apparent by changing the content written in the LUT from the code word dependent type to the data dependent type. .

  In the two-wire inspection circuit-equipped FPGA according to the present invention (solution 2), two-input one-output logic elements are distributed and written one by one in a multi-input one-output lookup table. Thus, it is possible to easily and accurately limit the reading locations to the four locations described above.

  Furthermore, in the two-wire inspection circuit-equipped FPGA of the present invention (Solution means 3), the input of the lookup table can be easily and accurately entered by inputting a fixed value other than the two inputs of the logic element. Can be narrowed down to limit the reading locations to the four locations described above.

Example 1 of the present invention shows a structure of a two-wire inspection circuit-mounted FPGA, where (a) is a circuit diagram relating to a narrowing circuit half of a two-wire inspection circuit of a bus verification circuit, and (b) is three A block diagram of three logic elements in which the half of the narrowing circuit is distributedly mounted, and (c), (d), and (e) are all LUTs (Look Up Tables) embodying the logic elements of the half of the narrowing circuit. . (A), (b), and (c) are LUTs that embody each logic element of the half of the narrowing circuit, and (d) and (e) are circuit diagrams of the narrowing circuit. (A), (b), and (c) are LUTs that embody each logic element of the half of the narrowing circuit, and (d) and (e) are circuit diagrams of the narrowing circuit. Example 2 of the present invention shows the structure of a two-wire inspection circuit-mounted FPGA, where (a) is a circuit diagram relating to a narrowing circuit half of a two-wire inspection circuit of a bus verification circuit, and (b) is three Block diagrams of three logic elements in which the half of the narrowing circuit is distributedly mounted, and (c), (d), and (e) are all LUTs that embody the logic elements of the half of the narrowing circuit. Example 3 of the present invention shows the structure of a two-wire inspection circuit mounted FPGA, and (a) and (b) are both bus verification circuits mounted on an LUT type FPGA by duplicating the two-wire inspection circuit. It is a block diagram. The structure of the conventional basic bus verification circuit is shown, (a) is a block diagram of the bus verification circuit, (b) is a block diagram of a two-wire inspection circuit and a pendulum circuit, and (c) is a basic narrowing circuit. It is a circuit diagram. (A) is a circuit diagram of a half of the narrowing-down circuit, and (b) is a circuit diagram of an equivalent narrowing-down circuit half of another embodiment. It is a schematic block diagram of a general LUT type FPGA. (A) is a block diagram of a general-purpose logic unit, (b) is a block diagram of a logic element, (c) is an example of a LUT (look-up table) pair that embodies two narrowing circuits, ie, two half narrowing circuits, d) and (e) are examples of LUTs embodying half the narrowing circuit.

With respect to such a two-wire inspection circuit-mounted FPGA of the present invention, specific modes for carrying out this will be described with reference to the following first to third embodiments.
The embodiment 1 shown in FIGS. 1 to 3 embodies all of the above-described solving means 1 to 3 (claims 1 to 3 at the beginning of the application). The embodiment 2 shown in FIG. Example 3 shown in FIG. 5 is a modification thereof.
In addition, since the same reference numerals are given to the same constituent elements as those in the prior art in the illustration thereof, the description in the background art section is also common to the following embodiments, and thus overlaps. The description will be omitted, and the following description will focus on differences from the prior art.

  A specific configuration of the two-wire inspection circuit-mounted FPGA of the present invention will be described with reference to the drawings. 1A is a circuit diagram relating to the narrowing circuit halves 21 to 23 of the two-wire inspection circuit 15 of the bus verification circuit 10, and FIG. 1B is a circuit diagram of three narrowing circuit halves 21 to 23 mounted in a distributed manner. The block diagram concerning the logic element 33, (c) is the LUT (look-up table) 34a which embodies the logic elements 21 of the narrowing circuit halves 21 to 23, and (d) is the logic element 22 of the narrowing circuit halves 21 to 23. Is an LUT 34c that embodies the logic elements 23 of the narrowing circuit halves 21 to 23.

The two-wire inspection circuit mounting FPGA of this embodiment is the same as the above-described conventional two-wire inspection circuit mounting FPGA, in which the two-wire inspection circuit 15 of the bus verification circuit 10 is written and mounted in the LUT type FPGA 30. However, the writing mode to the LUT is different from the conventional product.
In the conventional product, one narrowing circuit half 21 to 23 is written and mounted in one LUT 34 (see FIGS. 9B and 9C), but in the product of the present invention (see FIG. 1), The narrowing circuit halves 21 to 23 are mounted on the LUT in units of individual logic elements, not in units of combinational circuits. That is, the logic elements 21, 22, and 23 are written and mounted on the LUTs 34a, 34b, and 34c, one by one. Similarly, other logic elements included in the two-wire inspection circuit 15 are written and mounted one by one in one LUT. Note that the use of the registers 35a, 35b, and 35c corresponding to the LUTs 34a, 34b, and 34c is arbitrary, but the case of use is shown here (see FIG. 1B).

  The mounting manner of the logic elements 21, 22, and 23 of the narrowing circuit halves 21 to 23 will be described in detail. First, the logic element 21 of the AND gate that generates the intermediate value G from the input values A and D (FIG. 1 (a ), (B), (c)), four input values A and D and fixed values “0” and “0” are input to the four-input one-output LUT 34a assigned thereto, A data value “0” is written at addresses “0000”, “0100”, and “1000”, and a data value “1” is written at address “1100”. The fixed value is exemplified by “0”, but may be “1”.

Next, with respect to the logic element 22 of the AND gate that generates the intermediate value H from the input values B and C (see FIGS. 1A, 1B, and 1D), the four inputs assigned thereto are similarly applied. Four input values B and C and fixed values “0” and “0” are input to one output LUT 34b, and addresses “0000”, “0100”, “1000”, and “1100” are input. Data values “0”, “0”, “0”, “1” are written in
Further, the logic element 23 of the OR gate that generates the output value E from the intermediate values G and H (see FIGS. 1A, 1B, and 1E) is similarly applied to the 4-input 1 assigned thereto. Four values of intermediate values G and H and fixed values “0” and “0” are input to the output LUT 34c, and at addresses “0000”, “0100”, “1000”, and “1100”. Data values “0”, “1”, “1”, and “1” are written, respectively.

  The LUTs 34a, 34b, and 34c that have been written in this way are loaded with one logic element 21, 22, and 23, respectively, and each of the logical values A, B, C, D, G, and H Since two corresponding values are inputted and a fixed value “0” is inputted elsewhere, all the bit patterns “00” of the two inputs A + D, B + C, G + H of the logic elements 21, 22, 23 are input. ”,“ 01 ”,“ 10 ”,“ 11 ”, and four locations corresponding to the addresses“ 0000 ”,“ 0100 ”,“ 1000 ”,“ 1100 ”(see FIG. 1C to FIG. 1E) ) Is limited to the reading location, that is, the memory portion used. Other addresses (refer to the portions without Δ in FIGS. 1C to 1E) can be accessed regardless of the input values A, B, C, and D of the narrowing circuit halves 21 to 23. There is no unused memory part.

  The use mode and operation of the two-wire inspection circuit-mounted FPGA of the first embodiment will be described with reference to the drawings. 2A and 2B show LUTs 34a, LUT34b, and LUT34c that respectively embody the logic elements 21, 22, and 23 of the narrowing-down circuit halves 21 to 23, respectively, (a), (b), and (c). e) is a circuit diagram of the narrow-down circuit 20, and illustrates the operation when a soft error occurs in the unused memory portion. FIG. 3 also shows LUTs 34a, LUT34b, and LUT34c in which (a), (b), and (c) embody the logic elements 21, 22, and 23 of the narrowing circuit halves 21 to 23, respectively. , (E) is a circuit diagram of the narrow-down circuit 20, which illustrates an operation when a soft error occurs in the used memory portion.

Even if the writing mode is different, in the normal state where there is no soft error or other circuit failure, the usage and operation of the two-wire inspection circuit-equipped FPGA is the same as the conventional one. Will be described in detail.
Two cases where a soft error occurs in the LUT 34b in which the logic elements 22 of the narrowing circuit halves 21 to 23 of the narrowing circuit 20 of the two-wire inspection circuit 15 are written and mounted will be described.
The first is a case where a soft error occurs in the unused memory portion (see FIG. 2), and the second is a case where a soft error occurs in the used memory portion (see FIG. 3).

  First, it is assumed that one of the unused memory portions of the LUT 34b in the LUT 34a, LUT 34b, and LUT 34c (see FIGS. 2A to 2C) is inverted due to a soft error (see FIG. 2B *). . In this case, the LUT 34b is partially broken, but the failed portion is not accessed no matter what value of the 2-bit input values B and C, and the function of the logic element 22 is not impaired at all. Since the filter circuit 20 including the logic element 22 is maintained normally (see FIGS. 2D and 2E), the normal code word “01” or “01” is input as the input values A, B, C, and D. When two “10” are input, one normal code word “01” or “10” is output as the output values E and F, and otherwise, the non-normal code word “00” or “11” is output. Since this operation is the same as when there is no circuit failure, it can be said that the soft error in the unused memory portion is not substantially a circuit failure. The same applies to the LUTs 34a and 34c.

  Next, it is assumed that the data value at one location of the used memory portion of the LUT 34b among the LUT 34a, LUT 34b, and LUT 34c (see FIGS. 3A to 3C) is inverted due to a soft error (see FIG. 3B *). . In this case as well, the failure of the LUT 34b is partial, but in this case, the failure location is accessed depending on the pattern of the input values B and C. For example, if the data value of the address “1000” is inverted from “0” to “1” in the LUT 34b in which the logic element 22 is written and mounted, the narrowing-down circuit 20 including the logic element 22 (see FIG. 3D) When two normal code words “01” + “10” are input as the input values A, B, C, D, the correct one normal code word “10” is output as the output values E, F. When the other two normal code words “01” + “01” are input as A, B, C, and D (see FIG. 3E), the non-normal code word “11” is output as the output values E and F. Output.

  When a soft error occurs in the used memory portion of the LUT 34b as described above, the same applies to the LUTs 34a and 34c. However, the input values A, B, C, and D change to all bit patterns depending on data that changes during normal operation. Thus, when a read access is made to the data inversion portion of the LUT 34b, the intermediate value H output from the logic element 22 mounted on the write becomes an abnormal value, and the output value E of the narrow-down circuit 20 accordingly. , F become a non-normal code word, and finally the two-wire inspection circuit 15 outputs a non-normal code word, so that a soft error in the LUT is manifested in the form of detection of a mismatch in the data pair to be compared. To do.

  The specific configuration of the two-wire inspection circuit-mounted FPGA of the present invention will be described with reference to the drawings. 4A is a circuit diagram relating to the narrowing circuit halves 27 to 29 of the two-wire inspection circuit 15 of the bus verification circuit 10, and FIG. The block diagram of the logic element 33, (c) LUT (look-up table) 34a embodying the logic element 27 of the narrowing circuit halves 27-29, (d) the logic element 28 of the narrowing circuit halves 27-29. The embodied LUT 34b, (e) is the LUT 34c that embodies the logic elements 29 of the narrowing circuit halves 27-29.

The two-wire inspection circuit-equipped FPGA differs from that of the first embodiment described above in that the narrowing circuit halves 27 to 29 which are equivalent to the narrowing circuit halves 21 to 23 but have different gate types have three logics. One of the elements 33 to 33 is written and mounted one by one.
That is, the NAND gate logic element 27 is written and mounted in the LUT 34a (see FIGS. 4A, 4B, and 4C), and the NAND gate logic element 28 is written and mounted in the LUT 34b (FIG. 4). (See (a), (b), (d)), and the logic element 29 of the NAND gate is also written and mounted in the LUT 34c (see FIGS. 4 (a), (b), (e)).

Although a detailed description that will be repeated is omitted, the LUTs 34a, LUT34b, and LUT34c in which the logic elements 27, 28, and 29 are written and mounted are all of four inputs and one output, and the LUT34a, LUT34b, and LUT34c, respectively. The logical elements 27, 28, and 29 are written and mounted one by one, and the addresses correspond to any of the two-input all bit patterns of the logical elements in which the LUT 34 a, LUT 34 b, and LUT 34 c are all mounted. 4 reading locations are limited (see FIGS. 4C to 4E), and LUT 34a, LUT 34b, and LUT 34c are all 4 inputs and none of the 2 inputs of the mounted logic element is input. However, the fact that the fixed value “0” is inputted indicates that the FPGA with the two-wire inspection circuit of the first embodiment is used. It is the same.
The usage mode and operation are the same except for small differences due to the difference in gate type.

  The specific configuration of the two-wire inspection circuit-mounted FPGA of the present invention will be described with reference to the drawings. FIGS. 5A and 5B are block diagrams of a bus verification circuit in which the two-wire inspection circuit 15 is duplicated and mounted on the LUT type FPGA 30.

In the case where the two-wire inspection circuit 15 is duplicated, in addition to both circuits 15 and 15, a narrowing circuit 20 that inputs their outputs and combines them into one output code word “XY” is provided, so that the circuit 11 in the preceding stage is provided. 14 and the subsequent circuits 16 and 17 can follow the ready-made products.
The duplexed two-wire inspection circuit 15 + 15 + 20 is mounted on the LUT type FPGA 30 as described above. However, only the duplexed two-wire inspection circuit 15 + 15 + 20 may be mounted (see FIG. 5A). ) In addition to the dual two-wire inspection circuit 15 + 15 + 20, the latches 11 to 14 in the previous stage and the pendulum circuit 16 in the subsequent stage may be mounted (see FIG. 5B).

[Others]
In the above embodiment, the final output of the bus verification circuit 50 is generated by the normal relay R. However, this is an example in consideration of application to the railway signal control field that uses a lot of relay signals. The normal relay R is not essential for the implementation of the present invention.
In the above embodiment, the latch units 11 to 14 are provided in front of the two-wire inspection circuit 15. However, the latch units 11 to 14 are not essential, and may be omitted when there is a margin in comparison timing. It is. On the other hand, when the comparison timing is strict, a dual port or the like that can store continuous data may be placed in front of the latch units 11 to 14 (see Patent Document 5).

  The application of the two-wire inspection circuit-equipped FPGA of the present invention is not limited to the application to the bus verification circuit of the above-described dual system computer, but is more than a triple system including the above-described dual system. It can also be applied to a bus verification circuit of an electronic computer.

10: Bus verification circuit,
11 ... A system latch control circuit (first input / output information input circuit),
12 ... A system latch circuit (first input / output information input circuit),
13 ... B system latch circuit (second input / output information input circuit),
14 ... B-system latch control circuit (second input / output information input circuit),
15 ... Two-wire inspection circuit (comparison circuit),
16 ... pendulum circuit (error display circuit), 17 ... alternating signal detection circuit (error display circuit),
20 ... Narrowing circuit,
21, 22, 23 ... logic elements (half of the narrowing circuit),
24, 25, 26 ... logic elements (half of the narrow-down circuit),
27, 28, 29 ... logic element (half of the narrow-down circuit),
30 ... FPGA (look-up table type field programmable gate array),
31 ... In-device wiring, 32 ... General-purpose logic unit, 33 ... Logic element,
34, 34a, 34b, 34c ... LUT (Look Up Table),
35, 35a, 35b, 35c ... registers (flip-flops),
A, B ... input value (input bit pair), C, D ... input value (input bit pair),
E, F ... output value (output bit pair), G, H ... intermediate value,
R: Normal relay (monitoring relay, final verification result output relay)

Claims (3)

  When each bit pair of the comparison / verification target data pair is a two-bit different value normal code word consisting of a combination circuit of two-input one-output logic elements, a two-bit different value normal code word is output and the other cases Equipped with a two-wire inspection circuit equipped with a two-wire inspection circuit that outputs 2-bit equivalent non-regular codewords in a lookup table type field programmable gate array equipped with a multi-input lookup table with four or more inputs In the FPGA, any one of the look-up tables in which any of the logic elements is written and loaded has read locations at four locations corresponding to addresses in any of the two-input bit patterns of the logic device. A two-wire test circuit-equipped FPGA characterized by being limited.   Of the look-up tables, any one of the logic elements written and mounted is a multi-input one-output, and the logic elements are distributed and written on each of the look-up tables. 2. The two-wire inspection circuit mounted FPGA according to claim 1, wherein the two-wire inspection circuit is mounted.   A fixed value is input to any one of the lookup tables in which any one of the logic elements is written and not two of the two inputs of the logic element are input. An FPGA with a two-wire inspection circuit according to claim 1 or 2, characterized in that:

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