CN103675653A - Satellite mobile terminal CPLD test method - Google Patents
Satellite mobile terminal CPLD test method Download PDFInfo
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- CN103675653A CN103675653A CN201210353828.6A CN201210353828A CN103675653A CN 103675653 A CN103675653 A CN 103675653A CN 201210353828 A CN201210353828 A CN 201210353828A CN 103675653 A CN103675653 A CN 103675653A
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Abstract
The invention discloses a satellite mobile terminal CPLD test method. The method comprises the following steps: pin test points are set, pins of a CPLD is lead out, and the pins of the CPLD are detected whether to be connected; after the CPLD is normally connected, the CPLD is triggered through a FPGA, a high-frequency clock signal is inputted to the CPLD to make the CPLD perform logical negation operation on the high-frequency clock signal, and the operation result is detected whether to be correct; after the operation result is detected to be correct, the CPLD is triggered through the FPGA, a digit counting signal is inputted to the CPLD to make the CPLD perform logical shift and additive operation on the digit counting signal, the operation result is detected whether to be correct, and if the operation result is correct, then the CPLD is in qualified performance condition. The CPLD detected to be qualified through the method of the invention, the CPLD can be applied in a satellite mobile terminal even if other performances of the CPLD are not qualified, so the CPLD waste can be avoided, and the debugging production efficiency can be improved at the same time.
Description
Technical field
The present invention relates to satellite mobile communication technical field, particularly CPLD performance test methods in a kind of satellite mobile phone.
Background technology
CPLD (Complex Programmable Logic Device) CPLD is a kind of user digital integrated circuit of constitutive logic function as required and voluntarily.In satellite communication field, CPLD is applied in satellite mobile communication terminating machine conventionally, realizes the configuration of FPGA to audio coder & decoder (codec).A kind of satellite mobile communication terminating machine based on " Big Dipper " as shown in Figure 1, comprise FPGA chip XC5VLX50T and pronounciation processing chip AMBE2000, wherein, between XC5VLX50T and AMBE2000, by XC95272XL, connect, XC5VLX50T can be configured AMBE2000 by XC95272XL, user also can be configured in real time and detect AMBE2000 by XC95272XL, guarantees the dirigibility of system.
In the production and debug process of satellite mobile phone end plaste, in order to guarantee the correctness of systemic-function, need to detect online timely the function of speech processor, normally FPGA tests the performance of speech processor by CPLD.Researchist finds, even if speech processor performance is normal, if but CPLD performance makes mistakes and also can cause speech processor cisco unity malfunction, so the performance of CPLD is detected and is very important, be CPLD or speech processor to correctly distinguish the device of cisco unity malfunction.After detecting the normal work of CPLD, again speech processor is tested.
The method at present CPLD being detected is, use independently instrument to carry out complete detection to CPLD, its advantage is to guarantee that every part of CPLD is all correct, but its shortcoming is: 1) CPLD having welded can only be taken off and detects from end plaste, whether the pin connection that can not detect like this CPLD is normal, and after detection, CPLD being welded to end plaste also can affect welding effect again; 2) for local damage but still operable CPLD can not distinguish, cause the waste of CPLD; 3) testing expense is high, the time is long, efficiency is low.
Summary of the invention
The object of the invention is to overcome existing above-mentioned deficiency in prior art, CPLD performance test methods in a kind of satellite mobile phone is provided.
In order to realize foregoing invention object, the invention provides following technical scheme:
A CPLD performance test methods in satellite mobile phone, the method comprises the following steps:
Step 1: pin test point is set on the end plaste of satellite mobile phone, draws the pin of CPLD, whether the pin that detects CPLD is communicated with; If pin is communicated with, enter step 2, otherwise change CPLD, re-start the pin communication with detection of CPLD;
Step 2: trigger CPLD by FPGA, to CPLD, input high-frequency clock signal, make CPLD carry out logic NOT computing to high-frequency clock signal, again operation result is outputed to FPGA, whether detection calculations result is correct, if operation result correctly, enters step 3, otherwise change CPLD, return to step 1;
Step 3: trigger CPLD by FPGA, to CPLD input digital count signal, the signal value of described digital count signal is 0 ~ 0xffffffffffff, make CPLD carry out logical shift and additive operation to digital count signal, again operation result is outputed to FPGA, whether detection calculations result is correct, if operation result correctly, CPLD performance is qualified, otherwise change CPLD, return to step 1.
According to the embodiment of the present invention, in described step 1, detecting the method whether pin of CPLD be communicated with is: by FPGA, trigger CPLD, if CPLD has response, connect successively the pin of CPLD with 3.3V test connecting line, if FPGA obtains the level signal of 3.3V successively, CPLD pin is communicated with; If CPLD does not respond, or CPLD has response but pulse signal that FPGA obtains is discontinuous, changes CPLD.
compared with prior art, beneficial effect of the present invention:
1) CPLD directly tests after welding on end plaste, can find in time whether welding is correct.
2) by the inventive method, detect qualified CPLD, even if other performance inconsistency lattice of CPLD also can be applied to satellite mobile terminal, avoid CPLD waste, at utmost reduce the loss.
3) only carry out the necessary performance test of CPLD, improved the labour productivity of debugging maintenance, reduced cost.
Accompanying drawing explanation:
Fig. 1 is a kind of structured flowchart of satellite mobile terminal.
Fig. 2 is method of testing process flow diagram of the present invention.
Embodiment
Below in conjunction with test example and embodiment, the present invention is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the present invention only limits to following embodiment, all technology realizing based on content of the present invention all belong to scope of the present invention.
Figure 1 shows that a kind of structured flowchart of satellite mobile terminal, this satellite mobile terminal comprises FPGA chip XC5VLX50T, described XC5VLX50T is connected with CPLD chip XC95272XL by programmable interface, XC95272XL is connected with pronounciation processing chip AMBE2000 by control interface, and XC5VLX50T is configured AMBE2000 by XC95272XL.
With reference to figure 2, CPLD performance test methods of the present invention is for the performance of the satellite mobile terminal CPLD shown in test pattern 1, and this method of testing comprises the following steps:
S1: trigger XC95272XL by XC5VLX50T, input a clock signal to the input pin of XC95272XL.
S2: whether have response, if XC95272XL has response, the output terminal of XC95272XL is exported this clock signal, enters step S3 if detecting XC95272XL, otherwise check that whether the welding of XC95272XL normally or directly changes XC95272XL, returns to step S1.
S3: pin test point is set on the end plaste of satellite mobile phone, draws all pins of XC95272XL, connect successively the pin of XC95272XL with 3.3V test connecting line.
S4: whether the outputs level signals that detects each pin of XC95272XL is 3.3V signal, if XC5VLX50T obtains the continuous level signal of 3.3V successively, enters step S5, otherwise change XC95272XL, return to step S1.
S5: trigger XC95272XL by XC5VLX50T, input high-frequency clock signal to the input pin of XC95272XL, make XC95272XL carry out logic NOT computing to high-frequency clock signal, then operation result is outputed to XC5VLX50T.
S6: whether detection calculations result is correct, if operation result correctly, enters step S7, otherwise changes XC95272XL, returns to step S1.
S7: trigger XC95272XL by XC5VLX50T, input pin input digital count signal to XC95272XL, the signal value of described digital count signal is changed to 0xffffffffffff successively from 0, make XC95272XL carry out logical shift and additive operation to digital count signal, then operation result is outputed to XC5VLX50T.
S8: whether detection calculations result is correct, if operation result correctly, XC95272XL performance is normal, otherwise changes XC95272XL, returns to step S1.
In described step S2, XC95272XL has the input and output performance of response explanation XC95272XL normal, also illustrates that XC95272XL welding is correct.In described step S4, if XC5VLX50T obtains the continuous level signal of 3.3V successively, illustrate that the function of each pin of XC95272XL is normal.In described step S6, if operation result is correct, illustrate that the dynamic response function of XC95272XL is normal, clock signal can be overturn in time.In described step S8, if operation result correctly illustrates that the logical block function of XC95272XL is normal, can provide in time logical signal.Only have through above-mentioned steps S1 and just can be applied in satellite mobile terminal to the XC95272XL of step S8 test passes, only need to just can be applied in satellite mobile terminal to the XC95272XL of step S8 test passes through above-mentioned steps S1.
According to the performance of method of testing of the present invention and testing sequence test CPLD, whether welding pin function whether normal, CPLD dynamic response performance whether normal, CPLD the logical block performance whether normal and CPLD that can detect CPLD is normal, only has the CPLD by the inventive method test passes just to can be used for the satellite mobile terminal shown in Fig. 1.The implication that CPLD described in the present embodiment is qualified is: CPLD finds after by method of testing of the present invention wrong or defective, i.e. the welding of CPLD is normal, the pin of CPLD is normal, the dynamic response performance of CPLD logical block performance normal, CPLD is normal.Detect qualified CPLD and can be applied to satellite mobile terminal, for other performances of CPLD, do not do requirement.
CPLD performance test methods of the present invention is that the CPLD that directly butt welding connects on end plaste tests, and can find in time whether welding is correct, avoids because of the defective speech processor cisco unity malfunction that causes of CPLD welding.By the inventive method, detect qualified CPLD, even if other performance inconsistency lattice of CPLD also can be applied to satellite mobile terminal, avoid causing a large amount of wastes of CPLD, at utmost reduce the loss.Method of testing of the present invention has only been carried out the necessary performance test of CPLD, has improved the labour productivity of debugging maintenance, is conducive to produce in enormous quantities, reduces costs.
Claims (2)
1. a CPLD performance test methods in satellite mobile phone, is characterized in that, the method comprises the following steps:
Step 1: pin test point is set on the end plaste of satellite mobile phone, draws the pin of CPLD, whether the pin that detects CPLD is communicated with; If pin is communicated with, enter step 2, otherwise change CPLD, re-start the pin communication with detection of CPLD;
Step 2: trigger CPLD by FPGA, to CPLD, input high-frequency clock signal, make CPLD carry out logic NOT computing to high-frequency clock signal, again operation result is outputed to FPGA, whether detection calculations result is correct, if operation result correctly, enters step 3, otherwise change CPLD, return to step 1;
Step 3: trigger CPLD by FPGA, to CPLD input digital count signal, the signal value of described digital count signal is 0 ~ 0xffffffffffff, make CPLD carry out logical shift and additive operation to digital count signal, again operation result is outputed to FPGA, whether detection calculations result is correct, if operation result correctly, CPLD performance is qualified, otherwise change CPLD, return to step 1.
2. CPLD performance test methods in satellite mobile phone according to claim 1, it is characterized in that, in described step 1, detecting the method whether pin of CPLD be communicated with is: by FPGA, trigger CPLD, if CPLD has response, the pin that connects successively CPLD with 3.3V test connecting line, if FPGA obtains the level signal of 3.3V successively, CPLD pin is communicated with; If CPLD does not respond, or CPLD has response but pulse signal that FPGA obtains is discontinuous, changes CPLD.
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Cited By (4)
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| CN105140152A (en) * | 2015-09-29 | 2015-12-09 | 中航海信光电技术有限公司 | Wafer level packaging single chip microcomputer pin welding detection method |
| CN107919139A (en) * | 2017-11-21 | 2018-04-17 | 北京华力创通科技股份有限公司 | ICBM SHF satellite terminal tester, test system and test method |
| CN109765481A (en) * | 2018-12-29 | 2019-05-17 | 西安智多晶微电子有限公司 | A kind of test board of the CPLD chip based on FPGA/MCU |
| CN114077566A (en) * | 2020-08-20 | 2022-02-22 | 鸿富锦精密电子(天津)有限公司 | System and method for data processing between upper computer and CPLD |
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| CN114077566A (en) * | 2020-08-20 | 2022-02-22 | 鸿富锦精密电子(天津)有限公司 | System and method for data processing between upper computer and CPLD |
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