CN209690897U - A kind of interrupt response test device - Google Patents
A kind of interrupt response test device Download PDFInfo
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- CN209690897U CN209690897U CN201920895949.0U CN201920895949U CN209690897U CN 209690897 U CN209690897 U CN 209690897U CN 201920895949 U CN201920895949 U CN 201920895949U CN 209690897 U CN209690897 U CN 209690897U
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- interface
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- transmitting terminal
- control terminal
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Abstract
The utility model discloses a kind of interrupt response test devices, including transmitting terminal, control terminal and Devices to test, control terminal is equipped with first interface, second interface and third interface, first interface is connect with transmitting terminal by serial ports, second interface is connect by GPIO with the interrupt pin on Devices to test, third interface is connect with key switch, to make transmitting terminal start interrupt response test in such a way that serial ports sends instruction to control terminal or by way of pressing the button switch；Mainly realized by control terminal CPLD, transmitting terminal is sent to CPLD by serial ports and is instructed, CPLD sends interrupt signal to Devices to test by GPIO after receiving instruction and starts to start timing, timing terminates and result is returned to transmitting terminal by serial ports after receiving the signal of GPIO return, test accuracy is high, and working efficiency is fast.
Description
Technical field
The utility model relates to the field of test technology, and in particular to a kind of interrupt response test device.
Background technique
In computer and server design, many scenes are required using interruption；Interrupt response is the hair for solving to interrupt
It now with the process of Receiver Problem, is completed by interruption means；Interrupt response is the process that hardware makes a response interrupt requests,
Including identifying interrupt source, retains scene, draw the processes such as interrupt handling routine；Some application scenarios are for interrupt response time
It is required that relatively high, it is therefore desirable to test the interrupt response time of different platform.
Utility model content
Aiming at the problems existing in the prior art, the purpose of this utility model is to provide a kind of tests of interrupt response to fill
It sets.
The technical scheme adopted by the utility model to solve the technical problem is as follows: a kind of interrupt response test device, including
Transmitting terminal, control terminal and Devices to test, the control terminal be equipped with first interface, second interface and third interface, first interface with
Transmitting terminal is connected by serial ports, and second interface is connect by GPIO with the interrupt pin on Devices to test, third interface and key
Switch connection, open transmitting terminal in such a way that serial ports sends instruction to control terminal or by way of pressing the button switch
Dynamic interrupt response test.
Particularly, the control terminal is CPLD, and control terminal receives the instruction that transmitting terminal issues by first interface, and leads to
It crosses second interface and sends interrupt signal to Devices to test.
Particularly, interrupt signal is pulse signal or high level or low level.
Particularly, the transmitting terminal is PC machine.
The utility model has the following beneficial effects:
A kind of interrupt response test device of the utility model design, mainly realizes that transmitting terminal passes through by control terminal CPLD
Serial ports sends to CPLD and instructs, and CPLD sends interrupt signal to Devices to test by GPIO after receiving instruction and starts starting meter
When, timing terminates and result is returned to transmitting terminal by serial ports after receiving the signal of GPIO return, and test accuracy is high, work
Efficiency is fast.
Detailed description of the invention
Fig. 1 is interrupt response test block diagram one.
Fig. 2 is interrupt response test block diagram two.
Specific embodiment
Below with reference to the attached drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out
Clearly and completely further details of explanation.Based on the embodiments of the present invention, those of ordinary skill in the art are not having
Every other embodiment obtained under the premise of creative work is made, is fallen within the protection scope of the utility model.
CPLD:Complex Programmable Logic Device is Complex Programmable Logic Devices, be from PAL and
The device that GAL device development comes out, in contrast scale is big, and structure is complicated, belongs to large scale integrated circuit range.It is a kind of use
Family according to respective the need and voluntarily digital integrated electronic circuit of constitutive logic function.Its basic design method is soft by Integrated Development
Part platform generates corresponding file destination with the methods of schematic diagram, hardware description language, is transmitted code by download cable
Into objective chip, the digital display circuit of design is realized.
GPIO:General Purpose Input Output, is a port expander, have low-power consumption, small package,
The advantages that low cost, simple wiring.
As shown in Figure 1, a kind of interrupt response test device, including transmitting terminal, control terminal and Devices to test, transmitting terminal PC
Machine, control terminal are that CPLD is equipped with first interface, second interface and third interface, and first interface is connect with transmitting terminal by serial ports,
Second interface is connect by GPIO with the interrupt pin on Devices to test, and third interface is connect with key switch, and control terminal passes through
First interface receives the instruction that transmitting terminal issues, and sends interrupt signal, the interrupt signal to Devices to test by second interface
For pulse signal or high level or low level, transmitting terminal in such a way that serial ports sends instruction to control terminal or by press by
The mode of key switch starts interrupt response test.
The utility model is mainly realized that PC machine is sent to CPLD by serial ports and instructed, after CPLD receives instruction by CPLD
Interrupt signal is sent to equipment under test by GPIO and starts to start timing, and timing terminates simultaneously handle after receiving the signal of GPIO return
As a result PC machine is returned to by serial ports, test accuracy is high, and working efficiency is fast.
Interrupt response test method: interrupt response device is mainly made of CPLD, CPLD output GPIO be signally attached to by
In the interrupt pin of measurement equipment, CPLD is connected by serial ports with PC machine, while being reserved with a key switch and being connected to CPLD；PC machine
Instruction is sent to CPLD by serial ports or is tested by pressing the button switch starting interrupt response time, after CPLD receives instruction
It sends interrupt signal according to demand to GPIO pin and to start counting, which can be pulse signal and be also possible to high electricity
Flat or low level, PC machine respond the interruption after receiving interruption and are connect by GPIO one pulse signal of return to CPLD, CPLD
Count results are converted into the time after receiving this pulse and are shown in PC machine by serial ports.
The utility model is not limited to above embodiment, anyone, which should learn, makes under the enlightenment of the utility model
Structure change, it is all that there is same or similar technical solution with the utility model, each fall within the protection scope of the utility model
Within.
Technology that the utility model is not described in detail, shape, construction portion are well-known technique.
Claims (4)
1. a kind of interrupt response test device, it is characterised in that: including transmitting terminal, control terminal and Devices to test, the control terminal
Equipped with first interface, second interface and third interface, first interface is connect with transmitting terminal by serial ports, and second interface passes through GPIO
It is connect with the interrupt pin on Devices to test, third interface is connect with key switch, so that transmitting terminal passes through serial ports to control terminal
It sends the mode of instruction or starts interrupt response test by way of pressing the button switch.
2. interrupt response test device according to claim 1, it is characterised in that: the control terminal is CPLD, control terminal
The instruction that transmitting terminal issues is received by first interface, and interrupt signal is sent to Devices to test by second interface.
3. interrupt response test device according to claim 2, it is characterised in that: interrupt signal is pulse signal or high electricity
Flat or low level.
4. interrupt response test device according to claim 1, it is characterised in that: the transmitting terminal is PC machine.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920895949.0U CN209690897U (en) | 2019-06-14 | 2019-06-14 | A kind of interrupt response test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920895949.0U CN209690897U (en) | 2019-06-14 | 2019-06-14 | A kind of interrupt response test device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209690897U true CN209690897U (en) | 2019-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920895949.0U Active CN209690897U (en) | 2019-06-14 | 2019-06-14 | A kind of interrupt response test device |
Country Status (1)
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111209175A (en) * | 2020-01-06 | 2020-05-29 | 山东超越数控电子股份有限公司 | External interrupt response performance test system and method |
-
2019
- 2019-06-14 CN CN201920895949.0U patent/CN209690897U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111209175A (en) * | 2020-01-06 | 2020-05-29 | 山东超越数控电子股份有限公司 | External interrupt response performance test system and method |
| CN111209175B (en) * | 2020-01-06 | 2023-11-03 | 超越科技股份有限公司 | External interrupt response performance test system and method |
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