CN106597096A - Clock frequency monitoring method - Google Patents
Clock frequency monitoring method Download PDFInfo
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- CN106597096A CN106597096A CN201611111227.9A CN201611111227A CN106597096A CN 106597096 A CN106597096 A CN 106597096A CN 201611111227 A CN201611111227 A CN 201611111227A CN 106597096 A CN106597096 A CN 106597096A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/10—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted, i.e. converting the signal into a square wave
Abstract
The invention provides a clock frequency monitoring method, which belongs to the technical field of semiconductor design and manufacturing and is applicable to detection on the frequency of a low-frequency clock. The low-frequency clock serves as a monitored clock. The method comprises steps: a signal source is provided as a reference clock; a frequency division counter is adopted to carry out frequency division on the lower frequency one of the monitored clock and the reference clock to obtain a second clock; the frequency division counter is adopted to carry out sampling and counting on the second clock through the higher frequency one of the monitored clock and the reference clock to obtain a counting value; a comparator is adopted to carry out comparison and calculation on the counting value and a preset counting value to obtain an error value; and the error value and a preset error threshold are compared and calculated, whether the absolute value of the error value is larger than the preset error threshold is judged, if yes, the frequency of the monitored clock exceeds an allowable range, and if not, the frequency of the monitored clock does not exceed the allowable range. The clock frequency monitoring method has the beneficial effects that the steps are simple, and the monitoring precision is high.
Description
Technical field
The present invention relates to quasiconductor design and manufacturing technology field, more particularly to a kind of clock frequency monitoring method.
Background technology
Clock has in systems very important status.Clock signal is used to provide execution standard to processor, such as when
Clock signal each time high level or it is low level when, CPU carries out once-through operation.When present clock dropout or frequency are unstable
Pledge love condition, be likely to result in processor error or maloperation.Clock signal is also used as synchronizing signal, the behavior to other modules
It is driven.Whether is the working stability of clock system, and the quality of the synchronizing signal produced by it determines to a great extent it
The stable degree of his module.
By taking Timer module as an example, the module is exactly to be used as trigger condition with the rising edge or trailing edge of clock signal to enter
Row timing, if clock frequency is incorrect, dutycycle is not pair or unstable, and it is incorrect to result in timing, in advance or postpones
Produce interruption.If clock signal is not produced, the module even cannot work.With the applied environment of chip it is more and more various
Change, the design of chip becomes increasingly complex, and the design of clock system also becomes increasingly complex.Ensure the clock signal of multiple clock systems
Frequency correctness and stability are even more important for the function and performance that ensure whole chip.
Existing clock frequency piece external monitor method is to measure reading by equipment such as external cymometer, oscillographs.
Existing external monitor method requires external high precision measurement equipment, and the frequency of measured clock is judged by way of artificial reading
Whether satisfaction is required.
Existing interior monitoring method is to carry out periodic samples to the measured clock of low frequency by the reference clock of high frequency
Count value is counted to get, compares the frequency multiple value of this count value and two clocks (reference clock and measured clock) whether phase
Deng judging whether the frequency of measured clock is correct with this.The high frequency standard clock sampling low frequency of existing interior monitoring mode
The method of measured clock requires that the frequency of reference clock is higher, because directly depending on to the resolution of measured clock frequency measurement
The frequency multiple relation of high frequency standard clock and measured clock, the frequency more high measurement accuracy of reference clock is higher.This clock
Frequency accuracy monitoring method or certainty of measurement be not high, or requires that reference clock is more much higher than the frequency of measured clock.
The content of the invention
For problems of the prior art, the invention provides the clock frequency that a kind of step is simple and certainty of measurement is high
Rate monitoring method.
A kind of clock frequency monitoring method, it is adaptable to which the frequency of low-frequency clock is detected, be with the low-frequency clock
Measured clock；Methods described includes：
Step S1, one signal source of offer are used as reference clock；
Step S2, the measured clock and the reference clock medium frequency junior are carried out point using a frequency counter
Frequently, obtaining the second clock that a cycle is a second；
Step S3, using the frequency counter by the measured clock and described reference clock medium frequency the higher person pair
The second clock carries out sample count, to obtain a count value；
Step S4, calculating is compared to the count value and a pre-set count values using a comparator, to obtain a mistake
Difference；
Step S5, calculating is compared to the error amount and a default error threshold, judges the absolute of the error amount
Whether value is more than the default error threshold：
If the determination result is YES, then the frequency of the measured clock exceedes allowed band；
If judged result is no, the frequency of the measured clock is not less than allowed band.
Preferably, the signal source is the clock signal of system in chip.
Preferably, the signal source is the clock signal being input into outside chip.
Preferably, the frequency counter is the frequency counter of 20 bit wides.
Preferably, when the frequency of the measured clock is less than the frequency of the reference clock, step S2 includes：
Step S21a, the second clock is sampled using the reference clock, and identify the upper of the second clock
Rise edge；
Step S22a, described in each two in the second clock between rising edge using the reference clock to the second when
Clock is counted, to obtain the count value.
Preferably, when the frequency of the measured clock is less than the frequency of the reference clock, step S2 includes：
Step S21b, the second clock is sampled using the reference clock, and identified under the second clock
Drop edge；
Step S22b, described in each two in the second clock between trailing edge using the reference clock to the second when
Clock is counted, to obtain the count value.
Preferably, when the frequency of the measured clock is higher than the frequency of the reference clock, step S2 includes：
Step S21c, the second clock is sampled using the measured clock, and identify the upper of the second clock
Rise edge；
Step S22c, described in each two in the second clock between rising edge using the measured clock to the second when
Clock is counted, to obtain the count value.
Preferably, when the frequency of the measured clock is higher than the frequency of the reference clock, step S2 includes：
Step S21d, the second clock is sampled using the measured clock, and identified under the second clock
Drop edge；
Step S22d, between each two trailing edge of the second clock second clock is entered using the measured clock
Row is counted, to obtain the count value.
Preferably, when the frequency of the measured clock is less than the frequency of the reference clock, the institute in step S4
It is the theoretic standard value for carrying out sample count to the second clock using the reference clock to state pre-set count values.
Preferably, when the frequency of the measured clock is higher than the frequency of the reference clock, the institute in step S4
It is the theoretic standard value for carrying out sample count to the second clock using the measured clock to state pre-set count values.
The invention has the beneficial effects as follows：Whether the frequency of accurate measurements measured clock is correctly stable, and step is simple, monitoring essence
Degree is high.
Description of the drawings
Fig. 1 is the schematic diagram of clock frequency monitoring method in a preferred embodiment of the present invention；
Fig. 2 is the flow chart of clock frequency monitoring method in a preferred embodiment of the present invention；
Fig. 3 is the flow chart of step S2 in embodiment one；
Fig. 4 is the flow chart of step S2 in embodiment two；
Fig. 5 is the flow chart of step S2 in embodiment three；
Fig. 6 is the flow chart of step S2 in embodiment three.
Specific embodiment
It should be noted that in the case where not conflicting, following technical proposals can be mutually combined between technical characteristic.
The specific embodiment of the present invention is further described below in conjunction with the accompanying drawings：
As shown in Figure 1-2, a kind of clock frequency monitoring method, said method includes：Suitable for the frequency to low-frequency clock
Detected, with above-mentioned low-frequency clock as measured clock clk1；Said method includes：
Step S1, one signal source of offer are used as reference clock clk0；
It is step S2, relatively low to above-mentioned measured clock clk1 and said reference clock clk0 medium frequencys using a frequency counter
Person is divided, to obtain the second clock clk_1s that a cycle is a second；
Step S3, using above-mentioned frequency counter by above-mentioned measured clock clk1 and said reference clock clk0 medium frequencys
The higher person carries out sample count to above-mentioned second clock clk_1s, to obtain a count value；
Step S4, calculating is compared to above-mentioned count value and a pre-set count values using a comparator, to obtain a mistake
Difference；
Step S5, calculating is compared to above-mentioned error amount and an above-mentioned default error threshold, judges above-mentioned error amount
Whether absolute value is more than above-mentioned default error threshold：
If the determination result is YES, then the frequency of above-mentioned measured clock clk1 exceedes allowed band；
If judged result is no, the frequency of above-mentioned measured clock clk1 is not less than allowed band.
Above-mentioned signal source be chip in clock signal of system or chip outside be input into clock signal, i.e., signal source be piece in
Or the clock signal outside piece.Above-mentioned frequency counter is the frequency counter of 20 bit wides.
In the present embodiment, whether the frequency of accurate measurements measured clock clk1 is correctly stable, and step is simple, monitoring accuracy
It is high.
Embodiment one
As shown in Figure 1, Figure 2 and shown in Fig. 3, it is assumed that the frequency of reference clock clk0 is higher than measured clock clk1, above-mentioned steps
S2 includes：
Step S21a, above-mentioned second clock clk_1s is sampled using said reference clock clk0, and identified above-mentioned
The rising edge of second clock clk_1s；
Step S22a, between the above-mentioned rising edge of each two of above-mentioned second clock clk_1s adopt said reference clock clk0
Above-mentioned second clock clk_1s is counted, to obtain above-mentioned count value.
With frequency counter by the pulse frequency division of measured clock clk1 into 1 second cycle second clock clk_1s；When using benchmark
Clock clk0 samples to second clock clk_1s, identifies a second rising edge of clock clk_1s；In second clock clk_1s per two
Counted with reference clock clk0 between individual rising edge, the value of frequency counter CNTclk0 is 20, is designated as CNTclk0
[19:0]；The frequency error of measured clock clk1：
{CNTclk0[19:0]-Fclk0[19:0]}/Fclk0[19:0]；
The default error threshold values Fdelta [i of frequency is set:0], if
|CNTclk0[i:0]-Fclk0[i:0]|>Fdelta[i:0],
Then measured clock clk1 frequencies exceed chip allowed band.
Wherein, Fclk0 [19:0] it is pre-set count values, CNTclk0 [i:0] it is error amount, Fclk0 [i:0] it is default mistake
Difference limen value.Above-mentioned pre-set count values Fclk0 [19:0] it is to entering in above-mentioned second clock clk_1s using said reference clock clk0
The theoretic standard value of row sample count.Above-mentioned CNTclk0 [i:0], Fclk0 [i:0], Fdelta [i:0] i in be less than
19 numerical value, can be arranged as required to, and the value of the more big then i of scope that error is allowed is bigger.
Embodiment two
As shown in Figure 1, Figure 2 and shown in Fig. 4, it is assumed that the frequency of reference clock clk0 is higher than measured clock clk1, above-mentioned steps
S2 includes：
Step S21b, above-mentioned second clock clk_1s is sampled using said reference clock clk0, and identified above-mentioned
The trailing edge of second clock clk_1s；
Step S22b, between the above-mentioned trailing edge of each two of above-mentioned second clock clk_1s adopt said reference clock clk0
Above-mentioned second clock clk_1s is counted, to obtain above-mentioned count value.
With frequency counter by the pulse frequency division of measured clock clk1 into 1 second cycle second clock clk_1s；When using benchmark
Clock clk0 samples to second clock clk_1s, identifies a second trailing edge of clock clk_1s；In second clock clk_1s per two
Counted with reference clock clk0 between individual trailing edge, the value of frequency counter value CNTclk0 is 20, is designated as CNTclk0
[19:0]；The frequency error of measured clock clk1：
{CNTclk0[19:0]-Fclk0[19:0]}/Fclk0[19:0]；
The default error threshold values Fdelta [i of frequency is set:0], if
|CNTclk0[i:0]-Fclk0[i:0]|>Fdelta[i:0],
Then measured clock clk1 frequencies exceed chip allowed band.
Wherein, Fclk0 [19:0] it is pre-set count values, CNTclk0 [i:0] it is error amount, Fclk0 [i:0] it is default mistake
Difference limen value.Above-mentioned pre-set count values Fclk0 [19:0] it is to entering in above-mentioned second clock clk_1s using said reference clock clk0
The theoretic standard value of row sample count.Above-mentioned CNTclk0 [i:0], Fclk0 [i:0], Fdelta [i:0] i in be less than
19 numerical value, can be arranged as required to, and the value of the more big then i of scope that error is allowed is bigger.
Embodiment three
As shown in Figure 1, Figure 2 and shown in Fig. 5, it is assumed that the frequency of reference clock clk0 is less than measured clock clk1, above-mentioned steps
S2 includes：
Step S21c, above-mentioned second clock clk_1s is sampled using above-mentioned measured clock clk1, and identified above-mentioned
The rising edge of second clock clk_1s；
Step S22c, between the above-mentioned rising edge of each two of above-mentioned second clock clk_1s adopt above-mentioned measured clock clk1
Above-mentioned second clock clk_1s is counted, to obtain above-mentioned count value.
With frequency counter by the pulse frequency division of reference clock clk0 into 1 second cycle second clock clk_1s；When using tested
Clock clk1 samples to second clock clk_1s, identifies a second rising edge of clock clk_1s；In second clock clk_1s per two
Counted with measured clock clk1 between individual rising edge, the value of frequency counter CNTclk1 is 20, is designated as CNTclk1
[19:0]；The frequency error of measured clock clk1：
{CNTclk1[19:0]–Fclk1[19:0]}/Fclk1[19:0]；
The default error threshold values Fdelta [i of frequency is set:0], if
|CNTclk1[i:0]-Fclk1[i:0]|>Fdelta[i:0],
Then measured clock clk1 frequencies exceed chip allowed band.
Wherein, Fclk1 [19:0] it is pre-set count values, CNTclk1 [i:0] it is error amount, Fclk1 [i:0] it is default mistake
Difference limen value.Above-mentioned pre-set count values Fclk1 [19:0] it is to entering in above-mentioned second clock clk_1s using above-mentioned measured clock clk1
The theoretic standard value of row sample count.Above-mentioned CNTclk1 [i:0], Fclk1 [i:0], Fdelta [i:0] i in be less than
19 numerical value, can be arranged as required to, and the value of the more big then i of scope that error is allowed is bigger.
Example IV
As shown in Figure 1, Figure 2 and shown in Fig. 6, it is assumed that the frequency of reference clock clk0 is less than measured clock clk1, above-mentioned steps
S2 includes：
Step S21d, above-mentioned second clock clk_1s is sampled using above-mentioned measured clock clk1, and identified above-mentioned
The trailing edge of second clock clk_1s；
Step S22d, between each two trailing edge of above-mentioned second clock clk_1s using above-mentioned measured clock clk1 on
State a second clock clk_1s to be counted, to obtain above-mentioned count value.
With frequency counter by the pulse frequency division of reference clock clk0 into 1 second cycle second clock clk_1s；When using tested
Clock clk1 samples to second clock clk_1s, identifies a second trailing edge of clock clk_1s；In second clock clk_1s per two
Counted with measured clock clk1 between individual trailing edge, the value of frequency counter CNTclk1 is 20, is designated as CNTclk1
[19:0]；The frequency error of measured clock clk1：
{CNTclk1[19:0]–Fclk1[19:0]}/Fclk1[19:0]；
The default error threshold values Fdelta [i of frequency is set:0], if
|CNTclk1[i:0]-Fclk1[i:0]|>Fdelta[i:0],
Then measured clock clk1 frequencies exceed chip allowed band.
Wherein, Fclk1 [19:0] it is pre-set count values, CNTclk1 [i:0] it is error amount, Fclk1 [i:0] it is default mistake
Difference limen value.Above-mentioned pre-set count values Fclk1 [19:0] it is to entering in above-mentioned second clock clk_1s using above-mentioned measured clock clk1
The theoretic standard value of row sample count.Above-mentioned CNTclk1 [i:0], Fclk1 [i:0], Fdelta [i:0] i in be less than
19 numerical value, can be arranged as required to, and the value of the more big then i of scope that error is allowed is bigger.
For a person skilled in the art, read after described above, various changes and modifications undoubtedly will be evident that.
Therefore, appending claims should regard the whole variations and modifications for covering the true intention and scope of the present invention as.In power
Any and all scope of equal value and content, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (10)
1. a kind of clock frequency monitoring method, it is adaptable to which the frequency of low-frequency clock is detected, with the low-frequency clock be by
Survey clock；Characterized in that, methods described includes：
Step S1, one signal source of offer are used as reference clock；
Step S2, the measured clock and the reference clock medium frequency junior are divided using a frequency counter,
To obtain the second clock that a cycle is a second；
Step S3, using the frequency counter by the measured clock and described reference clock medium frequency the higher person to described
Second clock carries out sample count, to obtain a count value；
Step S4, calculating is compared to the count value and a pre-set count values using a comparator, to obtain an error amount；
Step S5, calculating is compared to the error amount and a default error threshold, judging the absolute value of the error amount is
It is no more than the default error threshold：
If the determination result is YES, then the frequency of the measured clock exceedes allowed band；
If judged result is no, the frequency of the measured clock is not less than allowed band.
2. monitoring method according to claim 1, it is characterised in that the signal source is the system clock letter in chip
Number.
3. monitoring method according to claim 1, it is characterised in that the signal source is the clock letter being input into outside chip
Number.
4. monitoring method according to claim 1, it is characterised in that the frequency counter is the frequency division counter of 20 bit wides
Device.
5. monitoring method according to claim 1, it is characterised in that when the frequency of the measured clock is less than the benchmark
During the frequency of clock, step S2 includes：
Step S21a, the second clock is sampled using the reference clock, and identify the rising edge of the second clock；
Step S22a, between rising edge the second clock is entered using the reference clock described in each two in the second clock
Row is counted, to obtain the count value.
6. monitoring method according to claim 1, it is characterised in that when the frequency of the measured clock is less than the benchmark
During the frequency of clock, step S2 includes：
Step S21b, the second clock is sampled using the reference clock, and identify the trailing edge of the second clock；
Step S22b, between trailing edge the second clock is entered using the reference clock described in each two in the second clock
Row is counted, to obtain the count value.
7. monitoring method according to claim 1, it is characterised in that when the frequency of the measured clock is higher than the benchmark
During the frequency of clock, step S2 includes：
Step S21c, the second clock is sampled using the measured clock, and identify the rising edge of the second clock；
Step S22c, between rising edge the second clock is entered using the measured clock described in each two in the second clock
Row is counted, to obtain the count value.
8. monitoring method according to claim 1, it is characterised in that when the frequency of the measured clock is higher than the benchmark
During the frequency of clock, step S2 includes：
Step S21d, the second clock is sampled using the measured clock, and identify the trailing edge of the second clock；
Step S22d, between trailing edge the second clock is entered using the measured clock described in each two in the second clock
Row is counted, to obtain the count value.
9. monitoring method according to claim 1, it is characterised in that when the frequency of the measured clock is less than the benchmark
During the frequency of clock, the pre-set count values in step S4 are that the second clock is adopted using the reference clock
The theoretic standard value that sample is counted.
10. monitoring method according to claim 1, it is characterised in that when the frequency of the measured clock is higher than the base
During the frequency of punctual clock, the pre-set count values in step S4 are that the second clock is carried out using the measured clock
The theoretic standard value of sample count.
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| CN109342917A (en) * | 2018-08-31 | 2019-02-15 | 青岛海信电器股份有限公司 | The verification method and device of clock signal |
| CN109459612A (en) * | 2019-01-09 | 2019-03-12 | 上海艾为电子技术股份有限公司 | The detection method and device of the sample frequency of digital audio and video signals |
| CN109597457A (en) * | 2018-12-03 | 2019-04-09 | 安徽皖兴通信息技术有限公司 | A kind of clock detection method and device based on programmable logic device |
| CN109839838A (en) * | 2017-11-29 | 2019-06-04 | 中国科学院沈阳自动化研究所 | It is synchronized and integrating device of meeting an urgent need from principal mode submersible high-accuracy self-adaptation |
| CN110308765A (en) * | 2019-06-28 | 2019-10-08 | 苏州浪潮智能科技有限公司 | A kind of server clock signal monitoring system and monitoring method |
| CN110324026A (en) * | 2019-06-21 | 2019-10-11 | 广芯微电子（广州）股份有限公司 | A kind of clock frequency detection method of chip interior clock source |
| CN110998339A (en) * | 2017-08-02 | 2020-04-10 | 高通股份有限公司 | On-chip frequency monitoring |
| CN111175573A (en) * | 2020-02-14 | 2020-05-19 | 深圳市科信通信技术股份有限公司 | Method, device, equipment and medium for detecting alternating voltage frequency |
| CN112748283A (en) * | 2020-12-29 | 2021-05-04 | 成都前锋电子仪器有限责任公司 | Audio signal sampling method, main control chip and audio module thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110998339A (en) * | 2017-08-02 | 2020-04-10 | 高通股份有限公司 | On-chip frequency monitoring |
| CN109839838A (en) * | 2017-11-29 | 2019-06-04 | 中国科学院沈阳自动化研究所 | It is synchronized and integrating device of meeting an urgent need from principal mode submersible high-accuracy self-adaptation |
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| CN109597457A (en) * | 2018-12-03 | 2019-04-09 | 安徽皖兴通信息技术有限公司 | A kind of clock detection method and device based on programmable logic device |
| CN109597457B (en) * | 2018-12-03 | 2022-04-19 | 安徽皖兴通信息技术有限公司 | Clock detection method and device based on programmable logic device |
| CN109459612A (en) * | 2019-01-09 | 2019-03-12 | 上海艾为电子技术股份有限公司 | The detection method and device of the sample frequency of digital audio and video signals |
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| CN110308765A (en) * | 2019-06-28 | 2019-10-08 | 苏州浪潮智能科技有限公司 | A kind of server clock signal monitoring system and monitoring method |
| CN111175573A (en) * | 2020-02-14 | 2020-05-19 | 深圳市科信通信技术股份有限公司 | Method, device, equipment and medium for detecting alternating voltage frequency |
| CN112748283A (en) * | 2020-12-29 | 2021-05-04 | 成都前锋电子仪器有限责任公司 | Audio signal sampling method, main control chip and audio module thereof |
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