CN106597096B - A kind of clock frequency monitoring method - Google Patents
A kind of clock frequency monitoring method Download PDFInfo
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- CN106597096B CN106597096B CN201611111227.9A CN201611111227A CN106597096B CN 106597096 B CN106597096 B CN 106597096B CN 201611111227 A CN201611111227 A CN 201611111227A CN 106597096 B CN106597096 B CN 106597096B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
- G01R23/10—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted, i.e. converting the signal into a square wave
Abstract
The present invention provides a kind of clock frequency monitoring method, belongs to semiconductor design and manufacturing technology field, detects suitable for the frequency to low-frequency clock, using low-frequency clock as measured clock；It include: to provide signal source as reference clock；Frequency junior in measured clock and reference clock is divided to obtain a second clock using frequency counter；Sample count is carried out to second clock by frequency the higher person in measured clock and reference clock using frequency counter and obtains count value；Calculating is compared to count value and pre-set count values using comparator, to obtain error amount；Error threshold is preset to error amount and is compared calculating, whether the absolute value of error in judgement value is greater than default error threshold: if so, the frequency of measured clock is more than allowed band；If it is not, then the frequency of measured clock is less than allowed band.Beneficial effects of the present invention: step is simple, and monitoring accuracy is high.
Description
Technical field
The present invention relates to semiconductor design and manufacturing technology fields more particularly to a kind of clock frequency monitoring method.
Background technique
Clock has very important status in systems.Clock signal for give processor provide execution standard, such as when
Clock signal each time high level or it is low level when, CPU carry out once-through operation.Clock dropout or frequency are unstable when present
Pledge love condition, may cause processor error or maloperation.Clock signal is also used as synchronization signal, the behavior to other modules
It is driven.Whether the operation is stable of clock system, the quality of synchronization signal caused by it largely determines it
The stable degree of his module.
By taking Timer module as an example, the module be exactly with the rising edge or failing edge of clock signal as trigger condition into
Row timing, if clock frequency is incorrect, duty ratio not to or it is unstable, result in timing incorrect, in advance or postpone
Generate interruption.If clock signal does not generate, which can not even work.As the application environment of chip is more and more various
Change, the design of chip becomes increasingly complex, and the design of clock system also becomes increasingly complex.Guarantee the clock signal of multiple clock systems
Frequency correctness and stability are even more important for the function and performance that guarantee entire chip.
Existing clock frequency piece external monitor method is to measure reading by equipment such as external frequency meter, oscillographs.
Existing external monitor method requires external high precision measurement equipment, and the frequency of measured clock is judged by way of manually reading
Whether meet the requirements.
Existing interior monitoring method is to carry out periodic samples to the measured clock of low frequency by the reference clock of high frequency
Count to get count value, compare this count value and two clocks (reference clock and measured clock) frequency multiple value whether phase
Deng whether correct come the frequency for judging measured clock with this.The high frequency standard clock sampling low frequency of existing interior monitoring mode
The method of measured clock requires the frequency of reference clock higher, because directly depending on to the resolution ratio of measured clock frequency measurement
The frequency multiple relationship of high frequency standard clock and measured clock, the frequency of reference clock more high measurement accuracy are higher.This clock
Perhaps measurement accuracy is not high or requires reference clock more much higher than the frequency of measured clock for frequency accuracy monitoring method.
Summary of the invention
Aiming at the problems existing in the prior art, clock simple the present invention provides a kind of step and high measurement accuracy frequency
Rate monitoring method.
A kind of clock frequency monitoring method, is detected suitable for the frequency to low-frequency clock, is with the low-frequency clock
Measured clock；The described method includes:
Step S1, a signal source is provided as reference clock；
Step S2, frequency junior in the measured clock and the reference clock is divided using a frequency counter
Frequently, to obtain the second clock that a period is one second；
Step S3, frequency the higher person pair in the measured clock and the reference clock is passed through using the frequency counter
The second clock carries out sample count, to obtain a count value；
Step S4, calculating is compared to the count value and a pre-set count values using a comparator, to obtain a mistake
Difference；
Step S5, calculating is compared to the error amount and a default error threshold, judges the absolute of the error amount
Whether value is greater than the default error threshold:
If the determination result is YES, then the frequency of the measured clock is more than allowed band；
If judging result be it is no, the frequency of the measured clock is less than allowed band.
Preferably, the signal source is the clock signal of system in chip.
Preferably, the signal source is the clock signal inputted outside chip.
Preferably, the frequency counter is the frequency counter of 20 bit wides.
Preferably, when the frequency of the measured clock is lower than the frequency of the reference clock, the step S2 includes:
Step S21a, the second clock is sampled using the reference clock, and identifies the upper of the second clock
Rise edge；
Step S22a, when using the reference clock to the second between the rising edge described in the every two of the second clock
Clock is counted, to obtain the count value.
Preferably, when the frequency of the measured clock is lower than the frequency of the reference clock, the step S2 includes:
Step S21b, the second clock is sampled using the reference clock, and identified under the second clock
Edge drops；
Step S22b, when using the reference clock to the second between the failing edge described in the every two of the second clock
Clock is counted, to obtain the count value.
Preferably, when the frequency of the measured clock is higher than the frequency of the reference clock, the step S2 includes:
Step S21c, the second clock is sampled using the measured clock, and identifies the upper of the second clock
Rise edge；
Step S22c, when using the measured clock to the second between the rising edge described in the every two of the second clock
Clock is counted, to obtain the count value.
Preferably, when the frequency of the measured clock is higher than the frequency of the reference clock, the step S2 includes:
Step S21d, the second clock is sampled using the measured clock, and identified under the second clock
Edge drops；
Step S22d, between the every two failing edge of the second clock using the measured clock to the second clock into
Row counts, to obtain the count value.
Preferably, the institute when the frequency of the measured clock is lower than the frequency of the reference clock, in the step S4
Stating pre-set count values is to carry out the theoretic standard value of sample count to the second clock using the reference clock.
Preferably, the institute when the frequency of the measured clock is higher than the frequency of the reference clock, in the step S4
Stating pre-set count values is to carry out the theoretic standard value of sample count to the second clock using the measured clock.
The beneficial effects of the present invention are: whether the frequency of accurate measurements measured clock is correctly stablized, step is simple, monitoring essence
Degree is high.
Detailed description of the invention
Fig. 1 is the schematic diagram of clock frequency monitoring method in a preferred embodiment of the present invention；
Fig. 2 is the flow chart of clock frequency monitoring method in a preferred embodiment of the present invention；
Fig. 3 is the flow chart of step S2 in embodiment one；
Fig. 4 is the flow chart of step S2 in embodiment two；
Fig. 5 is the flow chart of step S2 in embodiment three；
Fig. 6 is the flow chart of step S2 in embodiment three.
Specific embodiment
It should be noted that in the absence of conflict, following technical proposals be can be combined with each other between technical characteristic.
A specific embodiment of the invention is further described with reference to the accompanying drawing:
As shown in Figs. 1-2, a kind of clock frequency monitoring method, the above method include: suitable for the frequency to low-frequency clock
It is detected, using above-mentioned low-frequency clock as measured clock clk1；The above method includes:
Step S1, a signal source is provided as reference clock clk0；
Step S2, lower to frequency in above-mentioned measured clock clk1 and said reference clock clk0 using a frequency counter
Person divides, to obtain the second clock clk_1s that a period is one second；
Step S3, frequency in above-mentioned measured clock clk1 and said reference clock clk0 is passed through using above-mentioned frequency counter
The higher person carries out sample count to above-mentioned second clock clk_1s, to obtain a count value；
Step S4, calculating is compared to above-mentioned count value and a pre-set count values using a comparator, to obtain a mistake
Difference；
Step S5, calculating is compared to above-mentioned error amount and an above-mentioned default error threshold, judges above-mentioned error amount
Whether absolute value is greater than above-mentioned default error threshold:
If the determination result is YES, then the frequency of above-mentioned measured clock clk1 is more than allowed band；
If judging result be it is no, the frequency of above-mentioned measured clock clk1 is less than allowed band.
Above-mentioned signal source is the clock signal inputted outside the clock signal of system or chip in chip, i.e. signal source is in piece
Or the clock signal outside piece.Above-mentioned frequency counter is the frequency counter of 20 bit wides.
In the present embodiment, whether the frequency of accurate measurements measured clock clk1 is correctly stablized, and step is simple, monitoring accuracy
It is high.
Embodiment one
As shown in Figure 1, Figure 2 and shown in Fig. 3, it is assumed that the frequency of reference clock clk0 is higher than measured clock clk1, above-mentioned steps
S2 includes:
Step S21a, above-mentioned second clock clk_1s is sampled using said reference clock clk0, and identified above-mentioned
The rising edge of second clock clk_1s；
Step S22a, said reference clock clk0 is used between the above-mentioned rising edge of every two of above-mentioned second clock clk_1s
Above-mentioned second clock clk_1s is counted, to obtain above-mentioned count value.
With frequency counter by the pulse frequency division of measured clock clk1 at the period 1 second second clock clk_1s；When with benchmark
Clock clk0 samples second clock clk_1s, identifies a second rising edge of clock clk_1s；Every the two of second clock clk_1s
It is counted between a rising edge with reference clock clk0, the value of frequency counter CNTclk0 is 20, is denoted as CNTclk0
[19:0]；The frequency error of measured clock clk1:
{CNTclk0[19:0]-Fclk0[19:0]}/Fclk0[19:0]；
The default error threshold values Fdelta [i:0] of frequency is set, if
| CNTclk0 [i:0]-Fclk0 [i:0] | > Fdelta [i:0],
Then measured clock clk1 frequency exceeds chip allowed band.
Wherein, Fclk0 [19:0] is pre-set count values, and CNTclk0 [i:0] is error amount, and Fclk0 [i:0] is default misses
Poor threshold value.Above-mentioned pre-set count values Fclk0 [19:0] be using said reference clock clk0 in above-mentioned second clock clk_1s into
The theoretic standard value of row sample count.Above-mentioned CNTclk0 [i:0], the i in Fclk0 [i:0], Fdelta [i:0] be less than
19 numerical value, can be set as needed, and the value for the more big then i of range that error allows is bigger.
Embodiment two
As shown in Figure 1, Figure 2 and shown in Fig. 4, it is assumed that the frequency of reference clock clk0 is higher than measured clock clk1, above-mentioned steps
S2 includes:
Step S21b, above-mentioned second clock clk_1s is sampled using said reference clock clk0, and identified above-mentioned
The failing edge of second clock clk_1s；
Step S22b, said reference clock clk0 is used between the above-mentioned failing edge of every two of above-mentioned second clock clk_1s
Above-mentioned second clock clk_1s is counted, to obtain above-mentioned count value.
With frequency counter by the pulse frequency division of measured clock clk1 at the period 1 second second clock clk_1s；When with benchmark
Clock clk0 samples second clock clk_1s, identifies a second failing edge of clock clk_1s；Every the two of second clock clk_1s
It is counted between a failing edge with reference clock clk0, the value of frequency counter value CNTclk0 is 20, is denoted as CNTclk0
[19:0]；The frequency error of measured clock clk1:
{CNTclk0[19:0]-Fclk0[19:0]}/Fclk0[19:0]；
The default error threshold values Fdelta [i:0] of frequency is set, if
| CNTclk0 [i:0]-Fclk0 [i:0] | > Fdelta [i:0],
Then measured clock clk1 frequency exceeds chip allowed band.
Wherein, Fclk0 [19:0] is pre-set count values, and CNTclk0 [i:0] is error amount, and Fclk0 [i:0] is default misses
Poor threshold value.Above-mentioned pre-set count values Fclk0 [19:0] be using said reference clock clk0 in above-mentioned second clock clk_1s into
The theoretic standard value of row sample count.Above-mentioned CNTclk0 [i:0], the i in Fclk0 [i:0], Fdelta [i:0] be less than
19 numerical value, can be set as needed, and the value for the more big then i of range that error allows is bigger.
Embodiment three
As shown in Figure 1, Figure 2 and shown in Fig. 5, it is assumed that the frequency of reference clock clk0 is lower than measured clock clk1, above-mentioned steps
S2 includes:
Step S21c, above-mentioned second clock clk_1s is sampled using above-mentioned measured clock clk1, and identified above-mentioned
The rising edge of second clock clk_1s；
Step S22c, above-mentioned measured clock clk1 is used between the above-mentioned rising edge of every two of above-mentioned second clock clk_1s
Above-mentioned second clock clk_1s is counted, to obtain above-mentioned count value.
With frequency counter by the pulse frequency division of reference clock clk0 at the period 1 second second clock clk_1s；With it is tested when
Clock clk1 samples second clock clk_1s, identifies a second rising edge of clock clk_1s；Every the two of second clock clk_1s
It is counted between a rising edge with measured clock clk1, the value of frequency counter CNTclk1 is 20, is denoted as CNTclk1
[19:0]；The frequency error of measured clock clk1:
{CNTclk1[19:0]–Fclk1[19:0]}/Fclk1[19:0]；
The default error threshold values Fdelta [i:0] of frequency is set, if
| CNTclk1 [i:0]-Fclk1 [i:0] | > Fdelta [i:0],
Then measured clock clk1 frequency exceeds chip allowed band.
Wherein, Fclk1 [19:0] is pre-set count values, and CNTclk1 [i:0] is error amount, and Fclk1 [i:0] is default misses
Poor threshold value.Above-mentioned pre-set count values Fclk1 [19:0] be using above-mentioned measured clock clk1 in above-mentioned second clock clk_1s into
The theoretic standard value of row sample count.Above-mentioned CNTclk1 [i:0], the i in Fclk1 [i:0], Fdelta [i:0] be less than
19 numerical value, can be set as needed, and the value for the more big then i of range that error allows is bigger.
Example IV
As shown in Figure 1, Figure 2 and shown in Fig. 6, it is assumed that the frequency of reference clock clk0 is lower than measured clock clk1, above-mentioned steps
S2 includes:
Step S21d, above-mentioned second clock clk_1s is sampled using above-mentioned measured clock clk1, and identified above-mentioned
The failing edge of second clock clk_1s；
Step S22d, between the every two failing edge of above-mentioned second clock clk_1s using above-mentioned measured clock clk1 to upper
It states a second clock clk_1s to be counted, to obtain above-mentioned count value.
With frequency counter by the pulse frequency division of reference clock clk0 at the period 1 second second clock clk_1s；With it is tested when
Clock clk1 samples second clock clk_1s, identifies a second failing edge of clock clk_1s；Every the two of second clock clk_1s
It is counted between a failing edge with measured clock clk1, the value of frequency counter CNTclk1 is 20, is denoted as CNTclk1
[19:0]；The frequency error of measured clock clk1:
{CNTclk1[19:0]–Fclk1[19:0]}/Fclk1[19:0]；
The default error threshold values Fdelta [i:0] of frequency is set, if
| CNTclk1 [i:0]-Fclk1 [i:0] | > Fdelta [i:0],
Then measured clock clk1 frequency exceeds chip allowed band.
Wherein, Fclk1 [19:0] is pre-set count values, and CNTclk1 [i:0] is error amount, and Fclk1 [i:0] is default misses
Poor threshold value.Above-mentioned pre-set count values Fclk1 [19:0] be using above-mentioned measured clock clk1 in above-mentioned second clock clk_1s into
The theoretic standard value of row sample count.Above-mentioned CNTclk1 [i:0], the i in Fclk1 [i:0], Fdelta [i:0] be less than
19 numerical value, can be set as needed, and the value for the more big then i of range that error allows is bigger.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly be will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering true intention and range of the invention as.It is weighing
The range and content of any and all equivalences, are all considered as still belonging to the intent and scope of the invention within the scope of sharp claim.
Claims (10)
1. a kind of clock frequency monitoring method, is detected suitable for the frequency to low-frequency clock, using the low-frequency clock as quilt
Survey clock；It is characterized in that, which comprises
Step S1, a signal source is provided as reference clock；
Step S2, frequency junior in the measured clock and the reference clock is divided using a frequency counter,
To obtain the second clock that a period is one second；
Step S3, using the frequency counter by frequency the higher person in the measured clock and the reference clock to described
Second clock carries out sample count, to obtain a count value；
Step S4, calculating is compared to the count value and a pre-set count values using a comparator, to obtain an error amount；
Step S5, calculating is compared to the error amount and a default error threshold, judges that the absolute value of the error amount is
It is no to be greater than the default error threshold:
If the determination result is YES, then the frequency of the measured clock is more than allowed band；
If judging result be it is no, the frequency of the measured clock is less than allowed band；
The step S2 is used to handle frequency of the frequency of the measured clock lower than the reference clock or described in processing
The frequency of measured clock is higher than the frequency of the reference clock；
According to the frequency multiple relationship of the reference clock and the measured clock, to determine the frequency measurement of the measured clock
Resolution ratio.
2. monitoring method according to claim 1, which is characterized in that the signal source is the system clock letter in chip
Number.
3. monitoring method according to claim 1, which is characterized in that the signal source is the clock letter inputted outside chip
Number.
4. monitoring method according to claim 1, which is characterized in that the frequency counter is the frequency division counter of 20 bit wides
Device.
5. monitoring method according to claim 1, which is characterized in that when the frequency of the measured clock is lower than the benchmark
When the frequency of clock, the step S2 includes:
Step S21a, the second clock is sampled using the reference clock, and identifies the rising edge of the second clock；
Step S22a, between the rising edge described in the every two of the second clock using the reference clock to the second clock into
Row counts, to obtain the count value.
6. monitoring method according to claim 1, which is characterized in that when the frequency of the measured clock is lower than the benchmark
When the frequency of clock, the step S2 includes:
Step S21b, the second clock is sampled using the reference clock, and identifies the failing edge of the second clock；
Step S22b, between the failing edge described in the every two of the second clock using the reference clock to the second clock into
Row counts, to obtain the count value.
7. monitoring method according to claim 1, which is characterized in that when the frequency of the measured clock is higher than the benchmark
When the frequency of clock, the step S2 includes:
Step S21c, the second clock is sampled using the measured clock, and identifies the rising edge of the second clock；
Step S22c, between the rising edge described in the every two of the second clock using the measured clock to the second clock into
Row counts, to obtain the count value.
8. monitoring method according to claim 1, which is characterized in that when the frequency of the measured clock is higher than the benchmark
When the frequency of clock, the step S2 includes:
Step S21d, the second clock is sampled using the measured clock, and identifies the failing edge of the second clock；
Step S22d, between the failing edge described in the every two of the second clock using the measured clock to the second clock into
Row counts, to obtain the count value.
9. monitoring method according to claim 1, which is characterized in that when the frequency of the measured clock is lower than the benchmark
When the frequency of clock, the pre-set count values in the step S4 are to be adopted using the reference clock to the second clock
The theoretic standard value that sample counts.
10. monitoring method according to claim 1, which is characterized in that when the frequency of the measured clock is higher than the base
When the frequency of punctual clock, the pre-set count values in the step S4 are to be carried out using the measured clock to the second clock
The theoretic standard value of sample count.
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| US10514401B2 (en) * | 2017-08-02 | 2019-12-24 | Qualcomm Incorporated | On-chip frequency monitoring |
| CN109839838B (en) * | 2017-11-29 | 2020-10-02 | 中国科学院沈阳自动化研究所 | High-precision self-adaptive synchronous and emergency integrated device for autonomous submersible |
| CN109342917A (en) * | 2018-08-31 | 2019-02-15 | 青岛海信电器股份有限公司 | The verification method and device of clock signal |
| CN109597457B (en) * | 2018-12-03 | 2022-04-19 | 安徽皖兴通信息技术有限公司 | Clock detection method and device based on programmable logic device |
| CN109459612A (en) * | 2019-01-09 | 2019-03-12 | 上海艾为电子技术股份有限公司 | The detection method and device of the sample frequency of digital audio and video signals |
| CN110324026A (en) * | 2019-06-21 | 2019-10-11 | 广芯微电子（广州）股份有限公司 | A kind of clock frequency detection method of chip interior clock source |
| CN110308765A (en) * | 2019-06-28 | 2019-10-08 | 苏州浪潮智能科技有限公司 | A kind of server clock signal monitoring system and monitoring method |
| CN111175573A (en) * | 2020-02-14 | 2020-05-19 | 深圳市科信通信技术股份有限公司 | Method, device, equipment and medium for detecting alternating voltage frequency |
| CN112748283A (en) * | 2020-12-29 | 2021-05-04 | 成都前锋电子仪器有限责任公司 | Audio signal sampling method, main control chip and audio module thereof |
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| CN101582732B (en) * | 2009-06-10 | 2012-07-04 | 中兴通讯股份有限公司 | Clock detection method and device |
| CN202362380U (en) * | 2011-12-14 | 2012-08-01 | 浙江大学 | Multifunctional high-precision digital frequency meter |
| CN102724033A (en) * | 2012-06-07 | 2012-10-10 | 中兴通讯股份有限公司 | Method and main control veneer for realizing alignment of phase positions of master clock and reserved clock |
| CN104407510B (en) * | 2014-11-17 | 2017-12-15 | 江汉大学 | A kind of method and apparatus of time service |
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