CN203069745U - High-precision clock chip output pulse time interval detection apparatus - Google Patents
High-precision clock chip output pulse time interval detection apparatus Download PDFInfo
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- CN203069745U CN203069745U CN 201220688725 CN201220688725U CN203069745U CN 203069745 U CN203069745 U CN 203069745U CN 201220688725 CN201220688725 CN 201220688725 CN 201220688725 U CN201220688725 U CN 201220688725U CN 203069745 U CN203069745 U CN 203069745U
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Abstract
The utility model relates to high-precision clock chip output pulse time interval detection apparatus comprising a signal preprocessing module, a counting module and a display module. The signal preprocessing module has a level conversion unit and a signal integration unit for integrating multi-path input signals into single-path output signals. The counting module consists of main control unit, a clock unit and a counting unit; the main control unit is respectively connected with the clock unit, the counting unit, and the level conversion unit; the clock unit is connected with the counting unit; and the counting unit includes a first counting subunit and a second counting subunit, wherein the subunits are connected in series. According to the utility model, on the one hand, the output pulse time interval of the clock chip can be detected rapidly and thus precise data references can be provided for the chip design personnel at the initial stage of the design, thereby correcting the deviation caused by the production process conveniently; on the other hand, because two counting subunits in series connection are employed, the equipment procurement cost of the enterprise is saved on the premise that the detection precision is not reduced.
Description
Technical field
The utility model relates to pulse interval detection technique field, relates in particular to a kind of high precision clock class chip output pulse interval pick-up unit.
Background technology
Clock class chip commonly used is to come the timing of driving device formula clock and watch by the pulse that two paths is exported certain pulsewidth, the two-way output pulse of clock class chip is the asynchronous clock pulse, the precision of two paths pulse interval is the degree of accuracy that Second hand for clock and watch is walked about, therefore, guarantee that the precision of clock class chip two paths pulse interval is most important for the clock and watch timing.But, clock class chip is vulnerable to the influence of design and production technology in design and production run, as overgauge, minus deviation etc. inevitably occurring, for guaranteeing the accuracy of mechanical clock timing, according to the detection data of checkout equipment, the design by alternate manner such as crystal oscillator or physical construction in later process comes timely position class chip to cause the deviation of precision because of design and production technology.
Clock class chip detecting equipment such as general purpose oscialloscope commonly used, oscillograph for millisecond to the measuring accuracy in second rank time interval generally behind radix point 4 be the 10US rank, and on the market to the minimum accuracy requirement of clock class chip behind radix point 5 be the 1US rank, the accuracy of detection of general purpose oscialloscope can not satisfy the requirement of existing accuracy of detection.For carrying out high-precision test, have in the prior art and design integrated level height, checkout equipment that accuracy of detection is high, though the high precision checkout equipment can satisfy existing other accuracy of detection of 1US level, but its cost is higher, the function design is complicated, is unfavorable for the utilization factor of production control and raising checkout equipment.
Summary of the invention
Technical problem to be solved in the utility model is the problems referred to above that have the low or high precision checkout equipment cost height of accuracy of detection, function complexity at existing clock class chip detecting equipment, and the high precision clock class chip output pulse interval that a kind of cost is low, accuracy of detection is high pick-up unit is provided.
For addressing the above problem, the technical solution of the utility model is:
A kind of high precision clock class chip output pulse interval pick-up unit, comprise the signal pre-processing module for level conversion, the display module that is used for calculating the counting module of clock chip pulse interval and detects data for demonstration, signal pre-processing module, counting module and display module are connected in turn, described signal pre-processing module has a level conversion unit
Described signal pre-processing module also comprises the signal integration unit that the multichannel input signal is integrated into the single channel output signal, the signal integration unit has two-way input signal and at least one road output signal at least, the two-way input signal is respectively the two-way asynchronous clock pulse of clock chip output to be measured, and one tunnel output signal is the input signal of level conversion unit;
Described counting module comprises main control unit, clock unit and counting unit, main control unit respectively with clock unit, counting unit links to each other with level conversion unit, clock unit links to each other with counting unit, counting unit comprises first count sub-element and second count sub-element, first count sub-element and second count sub-element all have the control input end, trigger input end and overflow output terminal, the control input end of first count sub-element links to each other with main control unit, the triggering input end of first count sub-element and second count sub-element links to each other with level conversion unit respectively, and the output terminal that overflows of first count sub-element links to each other with the control input end of second count sub-element.
Signal integration unit in the utility model is the signal integration of the single output of dual input, the two-way asynchronous signal that clock class chip is exported in the signal integration unit is integrated into one-channel signal and is input in the level conversion unit, level conversion unit makes one-channel signal convert the level signal of coincidence counting unit to, this level signal sends to be counted in the counting module and handles, and shows in display module.The two-way asynchronous signal of having avoided clock chip to be measured causes transfer lag respectively after level conversion unit is handled otherness is counted and handled to the employing one-channel signal, and one-channel signal can keep certain lag characteristic in a period of time, can reduce the probability of signal errors significantly; Simultaneously, the signal of two-way asynchronous signal takes place need be by the control of two different interrupt sources, there is difference in different interrupt source operating lags, also increased the probability that error occurs, moreover, the control of different interrupt sources is also more loaded down with trivial details relatively, and one-channel signal adopts single interrupt source, not only control simply and also the probability of error low.Counting unit of the present utility model adopts two count sub-element series connection to realize counting, be 32 counting unit as counting unit, then adopt two 16 count sub-element series connection to realize 32 countings, therefore, under the condition that guarantees accuracy of detection, precision grade after 100NS is radix point 7 has reduced the cost of pick-up unit.The series connection of two count sub-element is also finished by hardware operation, avoided software get involved and produce than mistake may, further guaranteed the accuracy of detection of checkout equipment.
Utilize the utility model in the design production phase of clock class chip, to carry out the detection of pulse interval, can draw the detection data accurately, in time calculate the pulse interval deviation range, modification direction that simultaneously can clear and definite clock class chip later process.In actual use, by the sampling Detection of short run, can detect accurate data for designer's reference, be convenient to the error that the timely modifying factor production technology of designer etc. causes, significantly reduce production cost.
Be compared to prior art, high precision clock class chip output pulse interval pick-up unit of the present utility model can detect the output pulse interval of clock class chip on the one hand rapidly, for the chip design personnel provide the precise information reference at the design initial stage, in order to proofread and correct because the deviation that production technology is brought, on the other hand, the utility model has adopted the count sub-element of two series connection, has saved equipment purchase and the maintenance cost of enterprise under the prerequisite that does not reduce accuracy of detection.
Preferably, described first count sub-element and second count sub-element are a kind of in 16 counting units or 32 counting unit.Forms 32 counting unit or connected by two 32 count sub-element by the series connection of two 16 count sub-element and form 64 counting unit, convenient, flexible application.
Preferably, described first count sub-element and second count sub-element include and trigger controller, wave filter, interruptable controller, input marginal detector and register, interruptable controller links to each other with the input end of wave filter respectively with the output terminal of input marginal detector, the output terminal of wave filter links to each other with the input end that triggers controller, the input marginal detector also links to each other with register, and the input end of clock that triggers controller links to each other with clock unit; Described control input end is the input end of interruptable controller, triggers input end and is the input end of input marginal detector, overflows output terminal for triggering the output terminal of controller.
Preferably; described signal integration unit comprises pulse overshoot holding circuit and multi-path asynchronous pulse integrated circuit; the pulse overshoot holding circuit comprises a plurality of diodes; a plurality of diodes are connected on the two-way asynchronous clock pulse output end of clock chip to be measured; multi-path asynchronous pulse integrated circuit comprises a plurality of isolating diodes; a plurality of isolating diodes link to each other with the two-way asynchronous clock pulse output end of clock chip to be measured, and the output terminal of each isolating diode links to each other by resistance and forms one tunnel output signal of signal integration unit.The pulse overshoot holding circuit detects the output pulse of clock class chip; the pulse that meets the level requirement is directly inputted in the multi-path asynchronous pulse integrated circuit; for the output pulse of crossing high level, the pulse overshoot holding circuit is imported in the multi-path asynchronous pulse integrated circuit after step-down is processed into the maximum level of multi-path asynchronous pulse integrated circuit acquiescence.
Preferably, described level conversion unit comprises anti-jamming circuit and the level shifting circuit that links to each other in turn, anti-jamming circuit is the RC filtering circuit of being made up of filter capacitor and resistance, and level shifting circuit comprises triple gate, and the output terminal of triple gate links to each other with counting module.
Preferably, described counting module also comprises nonvolatile memory, and nonvolatile memory links to each other with counting unit with main control unit respectively.
Preferably, also be provided with the syndrome unit in the described main control unit, the input end of syndrome unit is connected with standard signal source.
Description of drawings
Fig. 1 is the theory diagram of the utility model high precision clock class chip output pulse interval pick-up unit.
Fig. 2 is the theory diagram of counting unit in the utility model high precision clock class chip output pulse interval pick-up unit.
Fig. 3 is the partial circuit schematic diagram of signal integration unit in the utility model high precision clock class chip output pulse interval pick-up unit.
Fig. 4 is the partial circuit schematic diagram of level conversion unit in the utility model high precision clock class chip output pulse interval pick-up unit.
Embodiment
Further describe the utility model below in conjunction with drawings and Examples, but protection domain of the present utility model is not limited to this.
With reference to Fig. 1, high precision clock class chip of the present utility model output pulse interval pick-up unit comprises signal pre-processing module for level conversion, is used for calculating the counting module of clock chip pulse interval and is used for showing the display module that detects data that signal pre-processing module, counting module and display module are connected in turn.
With reference to Fig. 1 and Fig. 4, described signal pre-processing module has a level conversion unit and a signal integration unit, the signal integration unit is the single channel output signal with the dual input signal integration, the signal integration unit has two-way input signal and one tunnel output signal, the two-way input signal is respectively the two-way asynchronous clock pulse of clock chip output to be measured, and one tunnel output signal is the input signal of level conversion unit.Level conversion unit comprises anti-jamming circuit and the level shifting circuit that links to each other in turn, anti-jamming circuit is the RC filtering circuit of being made up of filter capacitor and resistance, be connected with diode D5 between RC filtering circuit and one tunnel output signal, anti-jamming circuit makes the undesired signal Frequency point that may occur away from the frequency of need test signal.Level shifting circuit comprises triple gate TTL, and the input end of triple gate TTL links to each other with the output terminal of anti-jamming circuit, and the control end of triple gate TTL links to each other with counting module, and the output terminal of triple gate TTL links to each other with the counting unit of counting module.Level shifting circuit utilizes the wide characteristic of the quick upset of triple gate TTL and operating voltage range thereof that the low level signal of clock chip to be measured is converted to the discernible level signal of counting module.
With reference to Fig. 3, described signal integration unit comprises pulse overshoot holding circuit and multi-path asynchronous pulse integrated circuit, and the pulse overshoot holding circuit is connected in turn with multi-path asynchronous pulse integrated circuit.The pulse overshoot holding circuit comprises diode D1 and diode D2; diode D1 and diode D2 are connected on the two-way asynchronous clock pulse output end of clock chip to be measured; the other end of diode D1 and diode D2 is power end; to the power end conducting, diode D1 and diode D2 are the diode of low threshold value by pulse output end for diode D1 and diode D2.The pulse overshoot holding circuit detects the output pulse of clock chip to be measured; the pulse that meets the level requirement is directly inputted in the multi-path asynchronous pulse integrated circuit; for the output pulse of crossing high level, the pulse overshoot holding circuit is imported in the multi-path asynchronous pulse integrated circuit after step-down is processed into the maximum level of multi-path asynchronous pulse integrated circuit acquiescence.In when work, when time clock voltage during greater than the power end supply voltage, diode D1 and diode D2 can force down time clock voltage to the voltage that allows.Multi-path asynchronous pulse integrated circuit comprises isolating diode D3, isolating diode D4 and a plurality of resistance, isolating diode D3 links to each other with the two-way asynchronous clock pulse output end of clock chip to be measured respectively with isolating diode D4, the output terminal of isolating diode D3 and isolating diode D4 links to each other with power end by a plurality of resistance respectively, the output terminal of isolating diode D3 and isolating diode D4 links to each other by resistance simultaneously, and the output terminal of isolating diode D3 and isolating diode D4 links to each other by resistance and forms one tunnel output signal of signal integration unit.Multi-path asynchronous pulse signal integrated circuit is isolated the pulse signal of different passages by isolating diode do not interact it, by behind the isolating diode signal merging being inputed in the level conversion unit.
Referring to figs. 1 through Fig. 2, described counting module comprises main control unit, clock unit, counting unit and nonvolatile memory, main control unit links to each other with clock unit, counting unit, level conversion unit and nonvolatile memory respectively, and counting unit links to each other with clock unit with nonvolatile memory respectively.Described counting unit comprises first count sub-element and second count sub-element, first count sub-element and the series connection of second count sub-element, first count sub-element and second count sub-element include and trigger controller, wave filter, interruptable controller, input marginal detector and register, interruptable controller links to each other with the input end of wave filter respectively with the output terminal of input marginal detector, the output terminal of wave filter links to each other with the input end that triggers controller, the input marginal detector also links to each other with register, and the input end of clock that triggers controller links to each other with clock unit.First count sub-element and second count sub-element all have the control input end, trigger input end and overflow output terminal.The control input end of first count sub-element links to each other with main control unit, the triggering input end of first count sub-element and second count sub-element links to each other with level conversion unit, and the output terminal that overflows of first count sub-element links to each other with the control input end of second count sub-element.Wherein, the control input end is the input end of interruptable controller, triggers input end and is the input end of input marginal detector, overflows output terminal for triggering the output terminal of controller.
Wherein, first count sub-element and second count sub-element are a kind of in 16 counting unit or 32 s' the counting unit, can match according to detecting needs.Main control unit comprises main control chip and peripheral circuit, and wherein counting unit is the counting unit that main control chip carries, and counting unit is set dual timer cascade input trap mode in use.When the external pulse rising edge, the input marginal detector of first count sub-element detects porch and wave filter confirms that back first count sub-element begins counting, at this moment, second count sub-element is ready, second count sub-element begins counting after first count sub-element is overflowed, and counting module quits work and notifies main control unit to handle to next rising edge of a pulse the time.The utility model is by outside first rising edge of a pulse flip-flop number element count, the cycle of counting unit is by clock unit and external clock acting in conjunction and produce, clock unit inside is provided with frequency multiplier circuit and frequency departure correcting register, external clock is crystal oscillator, frequency multiplier circuit is brought up to the required count frequency of this pick-up unit with the crystal oscillator frequency of external clock, simultaneously, the frequency departure correcting register can be proofreaied and correct frequency, to guarantee precision.When pick-up unit was in the different environment, all there were certain difference in the signal transmission in the pick-up unit, components and parts performance etc.For improving degree of accuracy, the reduction error that detects, main control unit can pass through syndrome unit examination criteria signal source in advance, and go out the relative error value according to detecting data computation, this error amount is used for the testing result of revised version utility model, and the utility model can significantly improve measuring accuracy by cooperatively interacting of hardware and software.
The utility model high precision clock class chip output pulse interval pick-up unit comprises the steps: in testing process
Step 1: the syndrome unit in the main control unit detects standard signal source in advance, and goes out the relative error value according to detecting data computation;
Step 2: main control unit arranges first count sub-element and second count sub-element, makes first count sub-element be in the trigger-type count status with second count sub-element and the count mode full powers are finished by the hardware of two count sub-element of connecting;
Step 3: the two-way asynchronous clock pulse of clock chip output to be measured is inserted in the signal integration unit, the too high level drops that may exist by the pulse overshoot holding circuit is low to moderate signal integration circuit defaults maximum level, and multi-path asynchronous pulse integrated circuit is integrated into the single channel pulse signal with the asynchronous output pulse of two-way;
Step 4: the single channel pulse signal after the integration inputs in the level conversion unit, main control unit and counting unit operating voltage are at 3.3～5V in the utility model, and the operating voltage of clock chip to be measured is generally operational in 1.1～1.8V, so the low voltage signal that difficulty can't be identified or identify to former main control unit and counting unit by anti-jamming circuit and level shifting circuit is converted to high voltage signal;
Step 5: the signal after level conversion is sent in pattern is set two the series connection count sub-element, and the counting unit paired pulses time interval is delivered to register with count value after counting;
Step 6: main control unit reads count value from register, make count value be scaled double precision numerical value by conversion, according to the relative error value in the step 1 double precision numerical value after converting is revised, revised double precision numerical value is stored in the nonvolatile memory, by main control unit revised double precision numerical value is converted to the ASII sign indicating number simultaneously, is used for showing at display module.
In the above-mentioned explanation, all special instructions that do not add all adopt conventional implementation of the prior art.
Claims (7)
1. a high precision clock class chip is exported the pulse interval pick-up unit, comprise the signal pre-processing module for level conversion, the display module that is used for calculating the counting module of clock chip pulse interval and detects data for demonstration, signal pre-processing module, counting module and display module are connected in turn, described signal pre-processing module has a level conversion unit, it is characterized in that
Described signal pre-processing module also comprises the signal integration unit that the multichannel input signal is integrated into the single channel output signal, the signal integration unit has two-way input signal and at least one road output signal at least, the two-way input signal is respectively the two-way asynchronous clock pulse of clock chip output to be measured, and one tunnel output signal is the input signal of level conversion unit;
Described counting module comprises main control unit, clock unit and counting unit, main control unit respectively with clock unit, counting unit links to each other with level conversion unit, clock unit links to each other with counting unit, counting unit comprises first count sub-element and second count sub-element, first count sub-element and second count sub-element all have the control input end, trigger input end and overflow output terminal, the control input end of first count sub-element links to each other with main control unit, the triggering input end of first count sub-element and second count sub-element links to each other with level conversion unit respectively, and the output terminal that overflows of first count sub-element links to each other with the control input end of second count sub-element.
2. high precision clock class chip according to claim 1 output pulse interval pick-up unit is characterized in that, described first count sub-element and second count sub-element are a kind of in 16 counting units or 32 counting unit.
3. high precision clock class chip according to claim 1 is exported the pulse interval pick-up unit, it is characterized in that, described first count sub-element and second count sub-element include and trigger controller, wave filter, interruptable controller, input marginal detector and register, interruptable controller links to each other with the input end of wave filter respectively with the output terminal of input marginal detector, the output terminal of wave filter links to each other with the input end that triggers controller, the input marginal detector also links to each other with register, and the input end of clock that triggers controller links to each other with clock unit; Described control input end is the input end of interruptable controller, triggers input end and is the input end of input marginal detector, overflows output terminal for triggering the output terminal of controller.
4. high precision clock class chip according to claim 1 is exported the pulse interval pick-up unit; it is characterized in that; described signal integration unit comprises pulse overshoot holding circuit and multi-path asynchronous pulse integrated circuit; the pulse overshoot holding circuit comprises a plurality of diodes; a plurality of diodes are connected on the two-way asynchronous clock pulse output end of clock chip to be measured; multi-path asynchronous pulse integrated circuit comprises a plurality of isolating diodes; a plurality of isolating diodes link to each other with the two-way asynchronous clock pulse output end of clock chip to be measured, and the output terminal of each isolating diode links to each other by resistance and forms one tunnel output signal of signal integration unit.
5. high precision clock class chip according to claim 1 is exported the pulse interval pick-up unit, it is characterized in that, described level conversion unit comprises anti-jamming circuit and the level shifting circuit that links to each other in turn, anti-jamming circuit is the RC filtering circuit of being made up of filter capacitor and resistance, level shifting circuit comprises triple gate, and the output terminal of triple gate links to each other with counting module.
6. high precision clock class chip output pulse interval pick-up unit according to claim 1 is characterized in that described counting module also comprises nonvolatile memory, and nonvolatile memory links to each other with counting unit with main control unit respectively.
7. high precision clock class chip output pulse interval pick-up unit according to claim 1 is characterized in that also be provided with the syndrome unit in the described main control unit, the input end of syndrome unit is connected with standard signal source.
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| CN104101827B (en) * | 2014-06-25 | 2016-08-31 | 东南大学 | A kind of process corner detection circuit based on self-timing oscillation rings |
| CN107132569A (en) * | 2016-02-26 | 2017-09-05 | 赛默艾博林有限公司 | Out-of-service time corrects system and method |
| CN108226756A (en) * | 2018-01-29 | 2018-06-29 | 深圳市兴威帆电子技术有限公司 | The test system and its test method of a kind of clock chip |
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| CN111443587A (en) * | 2020-04-16 | 2020-07-24 | 珠海泰芯半导体有限公司 | External clock calibration method and system |
| CN111953338A (en) * | 2020-09-09 | 2020-11-17 | 绵阳市维博电子有限责任公司 | Real-time low-power-consumption integrated nuclear signal forming counting circuit |
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- 2012-12-11 CN CN 201220688725 patent/CN203069745U/en not_active Expired - Lifetime
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| CN104101827B (en) * | 2014-06-25 | 2016-08-31 | 东南大学 | A kind of process corner detection circuit based on self-timing oscillation rings |
| CN107132569B (en) * | 2016-02-26 | 2019-08-06 | 赛默艾博林有限公司 | Out-of-service time corrects system and method |
| CN107132569A (en) * | 2016-02-26 | 2017-09-05 | 赛默艾博林有限公司 | Out-of-service time corrects system and method |
| US10168435B2 (en) | 2016-02-26 | 2019-01-01 | Thermo Eberline Llc | Dead-time correction system and method |
| CN108226756B (en) * | 2018-01-29 | 2020-06-02 | 深圳市兴威帆电子技术有限公司 | Test system and test method of clock chip |
| CN108226756A (en) * | 2018-01-29 | 2018-06-29 | 深圳市兴威帆电子技术有限公司 | The test system and its test method of a kind of clock chip |
| CN109581220A (en) * | 2018-12-29 | 2019-04-05 | 深圳市汇川技术股份有限公司 | Inverter output voltage detection method, device, equipment and storage medium |
| CN111443587A (en) * | 2020-04-16 | 2020-07-24 | 珠海泰芯半导体有限公司 | External clock calibration method and system |
| CN111443587B (en) * | 2020-04-16 | 2021-09-07 | 珠海泰芯半导体有限公司 | External clock calibration method and system |
| CN111953338A (en) * | 2020-09-09 | 2020-11-17 | 绵阳市维博电子有限责任公司 | Real-time low-power-consumption integrated nuclear signal forming counting circuit |
| CN112255553A (en) * | 2020-09-18 | 2021-01-22 | 北京汽车股份有限公司 | Chip for detecting cell molecular decay, cell activity protection system and method |
| CN112255553B (en) * | 2020-09-18 | 2024-03-05 | 北京汽车股份有限公司 | Chip for detecting decay of battery molecules, battery activity protection system and method |
| CN112433970A (en) * | 2020-12-02 | 2021-03-02 | 上海集成电路研发中心有限公司 | Euse controller, chip and efuse read-write system |
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Effective date of registration: 20160309 Address after: 310012, No. 1, No. 4 Huang Shan Road, Zhejiang, Hangzhou Patentee after: BREMAX TECHNOLOGY CO.,LTD. Address before: 310012 Hangzhou, Zhejiang Province, Gushan Road, No. 4, No. Patentee before: HANGZHOU SILAN MICROELECTRONICS Co.,Ltd. |
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