CN102457268B - Implementation method for 32-bit capture register - Google Patents
Implementation method for 32-bit capture register Download PDFInfo
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- CN102457268B CN102457268B CN201010515766.5A CN201010515766A CN102457268B CN 102457268 B CN102457268 B CN 102457268B CN 201010515766 A CN201010515766 A CN 201010515766A CN 102457268 B CN102457268 B CN 102457268B
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Abstract
The invention provides an implementation method for a 32-bit capture register. The method comprises the following steps of: selecting an I/O (Input/Output) port of a used microprocessor; defining the I/O port as a capture port; setting an interrupt trigger mode of the I/O port as raising edge or falling edge interrupt trigger, wherein the I/O port is used for detecting a square wave signal carrying with frequency information; selecting a 16-bit timer of the used microprocessor; and configuring a first timer/counter and a second timer/counter of the 16-bit timer as a 32-bit period counter by calling a TIMER_CONFIGURE function. By setting a power system frequency measuring program, a frequency capture function of the 32-bit capture register is realized. The implementation method is simple and can guarantee the accuracy of power system frequency measurement.
Description
Technical field
The present invention relates to the implementation method of microprocessor 32 bit registers, 32 implementation methods of catching register particularly measuring for power system frequency.
Background technology
In electric power system, need accurately to measure its electric frequency, but use in the market portioned product in more microcontroller to only have 16 to catch register, these 16 are caught register maximum count value is 65536, timing is spaced apart 1.31072ms, and the power frequency period of general microprocessor is 20ms, in this case, utilize 16 bit frequencies to catch to send device while measuring electric frequency, need full 15 the maximum cycle values of counting just can reach a power frequency time interval, even if can count full power frequency period interval, the resolution of its frequency measurement also can be lower, can not guarantee the precision that electric frequency measurement is calculated.In this case, most protective devices adopt fixed sampling frequency to sample, or adopt slotting point mode to carry out compensation data, and still, above-mentioned sample mode, when measuring system causes frequency change due to fault, just cannot guarantee the accuracy of sample frequency.
Summary of the invention
The object of the present invention is to provide a kind of 32 implementation methods of catching register, can overcome deficiency of the prior art, guaranteed the precision that power system frequency is measured.
For achieving the above object, technical scheme of the present invention is: 32 implementation methods of catching register of the present invention comprise the following steps:
Step 1: an I/O mouth (input/output of selected microprocessor used, input/output port), described I/O mouth is defined as and catches mouth, and the down trigger mode of described I/O mouth is set to rising edge or trailing edge down trigger, this I/O mouth is for detection of the square-wave signal with frequency information;
Step 2: one 16 bit timing devices (timer) of selected described microprocessor, by calling TIMER_CONFIGURE function, one first Timer/Counter (timerA) of 16 described bit timing devices and one second Timer/Counter (timerB) are configured to 32 bit period counters, make this 16 bit timing utensil have 32 bit count functions.
Preferably, described I/O mouth has higher interrupt priority level, or has capturing function.
Preferably, the interrupt priority level of described I/O mouth is set to 2.
Preferably, the first described Timer/Counter and the second Timer/Counter are 16.
Preferably, the loading value of the first described Timer/Counter is as the initial value of 32 bit period counters, and the current count value of the second described Timer/Counter is the currency of 32 described bit period counters.
Preferably, under 32 bit patterns, when the first Timer/Counter and the second Timer/Counter are configured to a complete 32 bit period counter, operations to the first Timer/Counter and the second Timer/Counter, as load initial value, operation and control, interrupt controlling etc., all using the control as 32 bit period counters generally to the operations of the first Timer/Counter, and to the operation of the second Timer/Counter to 32 bit period counters generally without any effect.
Catch register for measuring the electric frequency of electric power system for 32 of the present invention, realize simply, and can guarantee the precision that power system frequency is measured.
Accompanying drawing explanation
Fig. 1 is 32 overview flow charts of catching the implementation method of register of the present invention;
Fig. 2 is the flow chart of an embodiment of 32 of the present invention implementation method of catching register.
Embodiment
For the features and advantages of the present invention can be become apparent more, below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Refer to Fig. 1,32 implementation methods of catching register of the present invention comprise the following steps:
Step 1: an I/O mouth (input/output of selected microprocessor used, input/output port), described I/O mouth is defined as and catches mouth, and the down trigger mode of described I/O mouth is set to rising edge or trailing edge down trigger, this I/O mouth is for detection of the square-wave signal with frequency information;
Step 2: one 16 bit timing devices (timer) of selected described microprocessor, by calling TIMER_CONFIGURE function, one first Timer/Counter (timerA) of 16 described bit timing devices and one second Timer/Counter (timerB) are configured to 32 bit period counters, make this 16 bit timing utensil have 32 bit count functions.
Preferably, described I/O mouth has higher interrupt priority level, or has capturing function.
Preferably, the interrupt priority level of described I/O mouth is set to 2.
Preferably, the first described Timer/Counter and the second Timer/Counter are 16.
Preferably, the loading value of the first described Timer/Counter is as the initial value of 32 bit period counters, and the current count value of the second described Timer/Counter is the currency of 32 described bit period counters.
Preferably, described TIMER_CONFIGURE function comprises two parameter values, respectively timer parameter and figure place parameter, the present embodiment is that the timer 2 of processor is set to 32 bit period counters, timer parameter in TIMER_CONFIGURE function is set to timer 2, figure place parameter is set to 32, the first Timer/Counter of timer 2 and the second Timer/Counter can be configured to 32 bit period counters.
Preferably, under 32 bit patterns, when the first Timer/Counter and the second Timer/Counter are configured to a complete 32 bit period counter, operations to the first Timer/Counter and the second Timer/Counter, as load initial value, operation and control, interrupt controlling etc., all using the control as 32 bit period counters generally to the operations of the first Timer/Counter, and to the operation of the second Timer/Counter to 32 bit period counters generally without any effect.
Refer to Fig. 2, during the invention process, comprise the following steps:
S101: select an I/O mouth (input/output, input/output port) of electric frequency measuring system microprocessor used, this I/O mouth edge triggered interruption mode is set, for detection of the square-wave signal with frequency information; And
The one 16 bit timing devices (the present embodiment is selected the timer 2 of microprocessor used) of selecting microprocessor used, it is for realizing 32 bit period counter function;
S102: the external interrupt of closing microprocessor used;
S103: close the peripheral module of microprocessor used, this peripheral module comprises I/O mouth module, timer module, A/D sampling module and watchdog module etc.;
S104: measuring system clock is set; Enable PLL (Phase Locked Loop, phase-locked loop or phase-locked loop) and be connected to microprocessor as system clock, it is 200MHz that PLL output frequency is set, and the frequency division value of measuring system output frequency divider is set to 4, and to carry out the output frequency after four frequency divisions be 50MHz to system;
S105: enable I/O mouth and interrupt;
S106: initialization I/O mouth, selected I/O mouth is defined as and catches mouth, this is caught and mouthful is set to input port, and this is set catches mouthful rising edge or trailing edge triggering mode;
S107: initialization the first Timer/Counter and the second Timer/Counter, the second Timer/Counter is set to have the counter of capturing function;
S108: enable the first Timer/Counter and the second Timer/Counter;
S109: call TIMER_CONFIGURE function the first Timer/Counter and the second Timer/Counter are configured to 32 bit period counters; In 32 singles triggerings and cycle timer pattern, the first Timer/Counter and the second Timer/Counter connect together and are configured to 32 down counters, and according to writing GPTM the first Timer/Counter pattern (GPTMTAMR, the value of TAMR bit field general purpose timer the first Timer/Counter pattern) can be determined and is chosen as cyclic pattern, now do not need to write GPTM the second Timer/Counter pattern (GPTMTBMR, general purpose timer the second Timer/Counter pattern);
S110: the loading value a of the first Timer/Counter is set (in the present embodiment, operation frequency of microprocessor used is 50MHz, it is 1999999 that a value is set), as the initial value of 32 bit period counters, the current count value b of the second Timer/Counter is set to the currency of 32 bit period counters;
S111: the output Trigger Function of forbidding the first Timer/Counter and the second Timer/Counter;
S112: the interruption of overflowing of the first Timer/Counter and the second Timer/Counter is set;
S113: enable the first Timer/Counter and the second Timer/Counter and start counting.
During enforcement, catch register and start frequency measurement when work when these 32, first, the frequency measurement program of electric power system enters I/O mouth interrupt service routine, this power system frequency process of measurement enters in I/O mouth at every turn and has no progeny and all take out immediately the currency b of 32 bit period counters, and the initial value of 32 bit period counters is set to a (because after frequency measuring system powers on, the data message in 1 second will be dropped) immediately.After frequency measurement program operation 1 second, when this frequency measurement program enters I/O mouth interrupt service routine again, take out the currency b of this 32 bit period counter, with its initial value a, deduct currency b and obtain a difference, this difference is the timing numerical value of a power frequency period, by the dtd--data type definition of this difference, be floating number (float type), computing formula is as follows:
Wherein, the electric frequency values that f is required measurement, the operating frequency that the molecular moiety of this formula is microprocessor used.
Result of the test shows: if adopt 16 to catch the electric frequency that register is measured electric power system, because 16 maximum count value of catching register are 0xffff, timing is spaced apart 1.31072ms, and a power frequency period is 20ms, so, in this case, catch for 16 and send device and need count full 15 maximum cycle values and just can reach a power frequency time interval, but program cannot be processed this situation, also cannot guarantee power system frequency certainty of measurement; If adopt 32 of the present invention to catch register for measuring the electric frequency of electric power system, realize simply, and can guarantee precision≤0.01Hz that power system frequency is measured.
Obviously, above-described embodiment is only the explanation of technical solution of the present invention unrestricted, and various changes that technical scheme of the present invention is carried out and being equal to are replaced and do not departed from the spirit and scope of the present invention, within all should being encompassed in claim scope of the present invention.
Claims (4)
1. 32 implementation methods of catching register, is characterized in that, comprise the following steps:
Step 1: an I/O mouth of selected microprocessor used, the down trigger mode of described I/O mouth is set to rising edge or trailing edge down trigger, and this I/O mouth is for detection of the square-wave signal with frequency information;
Step 2: one 16 bit timing devices of selected described microprocessor, are configured to 32 bit period counters by calling TIMER_CONFIGURE function by one first Timer/Counter of 16 described bit timing devices and one second Timer/Counter;
Step 3: the loading value a of described the first Timer/Counter is set as the initial value of described 32 bit period counters, the current count value b of described the second Timer/Counter is set to the currency of described 32 bit period counters;
Step 4: the output Trigger Function of forbidding described the first Timer/Counter and described the second Timer/Counter;
Step 5: the interruption of overflowing of described the first Timer/Counter and described the second Timer/Counter is set;
Step 6: enable described the first Timer/Counter and described the second Timer/Counter and start counting;
Step 7, when electric frequency measurement program enters the interrupt service routine of described I/O mouth again, take out the described current count value b of described this 32 bit period counter, and adopt described initial value a to deduct described current count value b to obtain a difference, described difference is the timing numerical value in power frequency period;
Wherein, described TIMER_CONFIGURE function comprises two parameter values, is respectively timer parameter and figure place parameter, and the timer parameter in described TIMER_CONFIGURE function is set to described 16 bit timing devices, and figure place parameter is set to 32.
2. 32 implementation methods of catching register according to claim 1, is characterized in that, the interrupt priority level of described I/O mouth is set to 2.
3. 32 implementation methods of catching register according to claim 1, is characterized in that, described the first Timer/Counter and the second Timer/Counter are 16 bit timings/counter.
4. 32 implementation methods of catching register according to claim 3, it is characterized in that, the loading value of the first described Timer/Counter is set to the initial value of 32 described bit period counters, and the current count value of the second described Timer/Counter is set to the currency of 32 described bit period counters.
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| CN102938197A (en) * | 2012-10-26 | 2013-02-20 | 合肥移瑞通信技术有限公司 | Method for decoding infrared remote control by means of input capture interrupt mode |
| CN105302226B (en) * | 2015-10-30 | 2018-01-16 | 北京时代民芯科技有限公司 | A kind of multifunctional mode timer circuit based on APB buses |
| CN105807843B (en) * | 2016-03-17 | 2019-07-23 | 东莞华芯世纪微电子有限公司 | A kind of method that realizing Timer/Counter and device in this way |
| CN112650119A (en) * | 2020-12-22 | 2021-04-13 | 深圳市禾望电气股份有限公司 | Method and device for expanding event occurrence time measurement range based on MCU |
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| CN1553336A (en) * | 2003-05-30 | 2004-12-08 | 中兴通讯股份有限公司 | Testing software timing method |
| US20090184742A1 (en) * | 2008-01-23 | 2009-07-23 | Microchip Technology Incorporated | Externally Synchronizing Multiphase Pulse Width Modulation Signals |
| CN101495959A (en) * | 2006-08-02 | 2009-07-29 | 高通股份有限公司 | Method and system to combine multiple register units within a microprocessor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1553336A (en) * | 2003-05-30 | 2004-12-08 | 中兴通讯股份有限公司 | Testing software timing method |
| CN101495959A (en) * | 2006-08-02 | 2009-07-29 | 高通股份有限公司 | Method and system to combine multiple register units within a microprocessor |
| US20090184742A1 (en) * | 2008-01-23 | 2009-07-23 | Microchip Technology Incorporated | Externally Synchronizing Multiphase Pulse Width Modulation Signals |
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| 党力明等.基于89C55WD单片机的32位高精度计时器.《测绘科学技术学报》.2007,第24卷(第5期),第346页右栏第1段，第347页左栏第1-7段，第348页左栏第2段及图1、3、4. |
| 基于89C55WD单片机的32位高精度计时器;党力明等;《测绘科学技术学报》;20071031;第24卷(第5期);第346页右栏第1段，第347页左栏第1-7段，第348页左栏第2段及图1、3、4 * |
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Inventor after: Di Fuchang Inventor after: Gao Longji Inventor after: Chen Lei Inventor after: Zhao Changbing Inventor after: Li Huiyong Inventor after: Zhang Jian Inventor after: Li Zengli Inventor after: Wang Jingren Inventor after: Liu Guoying Inventor after: Ou Yangqiang Inventor after: Chang Hongqi Inventor before: Di Fuchang Inventor before: Zhao Changbing Inventor before: Xiao Yonghua Inventor before: Li Zengli Inventor before: Wang Jingren Inventor before: Liu Guoying Inventor before: Ou Yangqiang Inventor before: Chang Hongqi Inventor before: Chen Lei |
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Address after: 101300 1, 1 yuan 17, Juyuan Road, Mapo Town, Shunyi District, Beijing. Patentee after: Beijing DeWitt electric Polytron Technologies Inc Address before: 101318 Beijing Shunyi District Tianzhu Airport Industrial Area B area Anqing avenue a 9 Patentee before: Beijing Devote Relay Protection Technology Co., Ltd. |
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