CN1553336A - Testing software timing method - Google Patents
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- CN1553336A CN1553336A CNA031381375A CN03138137A CN1553336A CN 1553336 A CN1553336 A CN 1553336A CN A031381375 A CNA031381375 A CN A031381375A CN 03138137 A CN03138137 A CN 03138137A CN 1553336 A CN1553336 A CN 1553336A
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Abstract
The method includes the following steps: central processor timer is initialized; timer is closed and to record current figure, timer is switched on and to start timing before test is started, tested program module is operated and clock period figure which is occupied time of central processor is recorded simultaneously by timer, current figre of timer is fetched after test is finished andto use the current figure to detuct figure obtained in advance for obtaining difference value between two figures, the difference value is multiplied by clock period of central processor to obtain test time and timing is stopped and timer of central processor is closed.
Description
Technical field
The present invention relates to test and use the software clocking method, relate in particular to a kind of test that is used for wireless communication system software clocking method, its degree of accuracy reaches nanosecond.
Background technology
In wireless communication system, prior art has multiple test clocking method, but existing software clocking method error is bigger, and method is loaded down with trivial details, can not meet the demands.Precision is higher, needs to increase extra hardware such as digital signal processor (DSP) etc.In wireless communication system 1X CDMA2000, existing method of testing is to utilize the message passing mechanism of real-time embedded operating system, timing message is passed to the specific hardware of bottom such as DSP obtains more accurate timing by test process.The system time precision of general operation system can only reach ten milliseconds, and the precision of bottom hardware can reach and receive wise move, and the accuracy of timekeeping of the DSP that is used to test such as 1X CDMA2000 can reach for 40 nanoseconds.Can improve the precision of timing though increase hardware, but this method is more loaded down with trivial details, be subjected to system task, process scheduling mechanism and such as the restriction of system resources such as process priority, message queue message count, timing message may be delayed, and causes time deviation bigger in the message scheduling process; Owing to increased extra hardware, be that cost also increases simultaneously.
Introduce a kind of existing method of testing below based on DSP and timing message, its principle is: send out message beginning to test the program module forward direction DSP that i.e. operation will test, notice DSP picks up counting, send out message to DSP again after the program module that end of test (EOT) promptly will be tested has been moved, notice DSP stops timing; The mode that DSP reports by timer transmits the processing time value that this program module takies CPU.Using the DSP timing is because DSP can be accurate to for 40 nanoseconds, and calls pSOS or the timing of VxWorks real-time embedded operating system can only be accurate to 10 milliseconds.Wherein used following two data structures, and passed to carry out of bottom DSP as message content with the control test with them:
1. start or stop timer E_S_GetVocoderRateSet (T_GetVocoderRateSet) typedef struct tagT_GetVocoderRateSet{＜!--SIPO＜DP n=" 1 "〉--〉＜dp n=" d1 "/Octet Reserved; Octet byLaterLength; Octet byOrderType; Octet byDSPChannelNum; UnsignedShortInt iCause; T_GetVocoderRateSet; 2. timer value reports E_S_VocoderFailure (T_VocoderFailure) typedef struct tagT_VocoderFailure{ Octet Reserved; Octet byLaterLength; Octet byOrderType; Octet byDSPChannelNum; Octet byUnused; Octet byCause; UnsignedLongInt iCounter; T_VocoderFailure;
In the method, need before the program module that operation needs to test, send out timing message to DSP, notice DSP picks up counting, but when this message can be scheduled, when can arrive DSP, being subjected to the influence of process priority, message scheduling mechanism, all is uncertain, thus timing when to begin also be unknown number.Equally, behind the program module end of run of needs test, also to send out message informing DSP and stop timing to DSP, the mode that DSP reports by timer transmits the processing time value, this also is subjected to the influence of process priority, message scheduling mechanism, when receives that therefore the message that stops timing also is a unknown number.Therefore, existing clocking method complexity, and because the process that exists message to transmit can not be accomplished accurate timing, and need to increase extra hardware, cost is than higher.
Summary of the invention
The purpose of this invention is to provide a kind of test software clocking method, its precision reaches nanosecond, this method is utilized the timer of central processing unit, adopt software control, it is the clocking capability of a clock period that precision is provided, because the frequency of central processing unit is higher usually, so the precision of this method can reach the level of nanosecond.The timer of the central processing unit that the present invention utilized is the resource of leaving unused, so the present invention need not to add new hardware, and the timer of central processing unit can directly be called by central processing unit, has avoided the loaded down with trivial details process scheduling and the influence of message scheduling mechanism, can carry out timing accurately.
The technical solution used in the present invention is as follows:
A. the timer of initialization central processing unit;
B. close the timer of central processing unit, and the current count value of the timer of record central processing unit;
C. open the timer of central processing unit and pick up counting, the timer of opening central processing unit must be before beginning test;
D. begin test process, the program module that operation will be tested, the timer of central processing unit writes down the clock periodicity that takies central processing unit simultaneously;
E. after the end of test (EOT), read the current count value of the timer of central processing unit, and deduct the count value that obtains among the step b, obtain the difference of twice count value with current count value;
F. clock period that the difference of twice count value obtaining among the step e be multiply by central processing unit, the time that obtains testing;
G. stop timing, close the timer of central processing unit.
Technical solutions according to the invention are utilized the timer of central processing unit, and the clocking method that is accurate to nanosecond is provided, and do not increase extra hardware again, owing to avoided process scheduling and message passing mechanism, can make timing more accurate simultaneously.
Description of drawings
Fig. 1 is the structured flowchart that adopts the MPC8260 timer of technical scheme of the present invention;
Fig. 2 is the structured flowchart that adopts the MPC8260 timer cascade pattern of technical scheme of the present invention;
Fig. 3 is the process flow diagram of test of the present invention with the software clocking method.
Fig. 4 is the comparison diagram as a result that obtains when adopting test of the present invention to select distribution module (SDM) test with the software clocking method with employing DSP and timing message approach.
Embodiment
Below in conjunction with accompanying drawing technical scheme of the present invention is described in further detail.
Fig. 1 is that to adopt the central processing unit among the mobile radio system 1X CDMA2000 of technical scheme of the present invention be the block diagram of the timer of MPC8260 (PowerPC8260 of Motorola central processing unit).The MPC8260 timer by 4 independently 16 bit timing devices form, each timer all has one group of identical register, comprise: timer global configuration register 11, timer event register 12, timer mode register 13, timer counter 14, timer reference register 15 and timer are caught register 16, can control the work of each timer by them, the general-purpose system clock is that bus clock is input to timer clock generator 17, and the Acquisition Detection module 18 of each timer is finished in the detection of the incident on its input clock edge and caught; Whether clock door 1 control first timer, second timer work, and whether clock door 2 controls the 3rd timer, the 4th timer work; The clock input x of each timer is its outside input clock source signal, wherein (x=1,2,3,4), the i.e. input of clock among the figure 1,2,3,4; The clock output y of each timer is that timer arrives the output signal that clocking value produces, wherein (y=1,2,3,4), the i.e. output of clock among the figure 1,2,3,4.For MPC8260, bus clock is 66MHz, so the maximal accuracy of timing is 1/ (66*10
6) second, promptly about 16 nanoseconds, satisfy the requirement that precision reaches nanosecond.
Fig. 2 is the structured flowchart that adopts the MPC8260 timer cascade pattern of technical scheme of the present invention.Because the MPC8260 timer has 4 independently 16 bit timing devices, therefore they can be cascaded into two 32 timer.Each timer of 32 all have one group with the identical registers group of 16 bit timing devices, and their usage is also identical with 16 bit timing devices, it is unique that not to be both them all be 32.As shown in Figure 2, the registers group of first timer 21 and the 3rd timer 23 is connected to the 0-15 position of data bit, and the registers group of second timer 22 and the 4th timer 24 is connected to the 16-31 position of data bit.Satisfy in precision under the condition of 16 nanoseconds, the maximum timing interval of each 32 bit timing device is about 68 seconds, if the execution time of the program module of test surpasses 68 seconds, then timer can overflow, and the value of being calculated also can be incorrect.But for wireless communication system, can satisfy the test request of any program module in 68 seconds, this that is to say the difference of 32 bit timing devices and 16 bit timing devices, if use 16 bit timing devices, then maximum timing interval is much smaller, with MPC8260 is example, and the maximum timing interval of 16 bit timing devices is 1.048576 milliseconds.
Fig. 3 is a specific embodiment of the present invention, and the process flow diagram of testing with the software clocking method in 1X CDMA2000 wireless communication system specifically may further comprise the steps:
A. the timer of initialization central processing unit, promptly to the employed central processing unit MPC8260 of system with timer carry out initialization, it must use timer to carry out finishing before the timing, total system is as long as initialization once, can be called this step in system-level initialization module.
B. close the timer of central processing unit, and note down the count value in the current timer.Here the count value in the central processing unit is set to 0, can make data computing convenient like this, and the clock period that the count value in the timer that reads after end of test (EOT) directly multiply by central processing unit just can obtain testing used time value.
C. open the timer of central processing unit and pick up counting, opening timer must be before entering the program module that needs test, and in order to guarantee precision of test result, the position of this step preferably can abut against before the program module that will test.
D. begin test procedure, the program module that operation will be tested, the timer of central processing unit writes down the clock periodicity that takies central processing unit simultaneously.
E. after the end of test (EOT), read the current count value of the timer of central processing unit, and deduct the count value that obtains among the step b, obtain the difference of twice count value with current count value.This step preferably can be carried out behind the program module end of run of test at once, to guarantee the accuracy of test duration.If the count value of timer is set to 0 among the step b, then directly can use here read count value, and do not need to do again subtraction.
F. clock period that the difference of twice counter obtaining among the step e be multiply by central processing unit, the time that obtains testing, if the count value of timer is set to 0 among the step b, then the clock period of directly multiply by central processing unit with the count value that reads among the step e promptly obtains the test duration.
G. stop timing, close the timer of central processing unit.
Fig. 4 is the comparison diagram as a result that obtains when adopting test of the present invention to select distribution module (SDM) test with the software clocking method with employing DSP and timing message approach.Test data of this group contrast is all taken from the data of the SDM test gained on the veneer Packet Service control function (PCF) in the Packet Service control function subsystem (PCFS) of 1X CDMA2000 wireless communication system.Ordinate among the figure is the time that takies central processing unit, unit was 16 nanoseconds, horizontal ordinate is the number of times of test, the time of the central processing unit that the SDM on veneer PCF of each data representation operation is shared, every kind of method has been carried out 50 tests, every broken line has comprised the data of 50 tests, and wherein thick lines represent that existing employing DSP and timing message approach test the result of gained, and hachure represents to adopt the result of software clocking method test gained of the present invention.As shown in Figure 4, the broken line that uses software clocking method of the present invention is that the DATA DISTRIBUTION of hachure representative is more even, and deviation is less each other, and its standard variance that records data is littler.Therefore the data of using the present invention to record are more stable, more even.
By above embodiment as can be seen, adopt technical solutions according to the invention, utilized the timer of central processing unit, the clocking method that is accurate to nanosecond is provided, do not increase extra hardware again, owing to avoided process scheduling and message passing mechanism, can make timing more accurate simultaneously.
Claims (7)
1. a test software clocking method is characterized in that, may further comprise the steps:
A. the timer of initialization central processing unit;
B. close the timer of central processing unit, and the current count value of the timer of record central processing unit;
C. open the timer of central processing unit and pick up counting, the timer of opening central processing unit must be before beginning test;
D. begin test process, the program module that operation will be tested, the timer of central processing unit writes down the clock periodicity that takies central processing unit simultaneously;
E. after the end of test (EOT), read the current count value of the timer of central processing unit, and deduct the count value that obtains among the step b, obtain the difference of twice count value with current count value;
F. clock period that the difference of twice count value obtaining among the step e be multiply by central processing unit, the time that obtains testing;
G. stop timing, close the timer of central processing unit.
2. test software clocking method as claimed in claim 1 it is characterized in that described step b closes the timer of central processing unit, and the current count value of the timer of central processing unit is set to 0.
3. test software clocking method as claimed in claim 1 is characterized in that described step c opens the timer of central processing unit and picks up counting, and a step that is right after after this step is the program module that operation will be tested.
4. test software clocking method as claimed in claim 1 is characterized in that, the current count value that described step e reads the timer of central processing unit is immediately following a step behind the program module end of run that will test.
5. test software clocking method as claimed in claim 1 is characterized in that, this method can be used in and comprise 4 independently 16 on the central processing unit of timer.
6. as any described test software clocking method in the claim 1 to 5, it is characterized in that this method can be used in 4 independently 16 are cascaded on 2 32 the central processing unit of timer for timer.
7. as any described test software clocking method in the claim 1 to 6, it is characterized in that this method can be used on the PowerPC8260 of the Motorola central processing unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031381375A CN1295614C (en) | 2003-05-30 | 2003-05-30 | Testing software timing method |
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| CNB031381375A CN1295614C (en) | 2003-05-30 | 2003-05-30 | Testing software timing method |
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| CN1553336A true CN1553336A (en) | 2004-12-08 |
| CN1295614C CN1295614C (en) | 2007-01-17 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102087513A (en) * | 2010-12-14 | 2011-06-08 | 广东雅达电子股份有限公司 | Timing extension method of PLC (programmable logic controller) timer |
| CN102404497A (en) * | 2010-09-16 | 2012-04-04 | 北京中星微电子有限公司 | Digital zoom method and device for image pickup equipment |
| CN102457268A (en) * | 2010-10-15 | 2012-05-16 | 北京德威特电力系统自动化有限公司 | Implementation method for 32-bit capture register |
| CN103823756A (en) * | 2014-03-06 | 2014-05-28 | 北京京东尚科信息技术有限公司 | Method for running application under test and scheduler |
| CN104850458A (en) * | 2014-02-15 | 2015-08-19 | 瞿浩正 | Timestamp based method for measuring million instructions per second (MIPS) required by embedded software module |
| CN105653242A (en) * | 2015-12-28 | 2016-06-08 | 北京经纬恒润科技有限公司 | Timing method and apparatus |
| CN106066829A (en) * | 2016-06-13 | 2016-11-02 | 江西洪都航空工业集团有限责任公司 | A kind of missile-borne time-consuming real-time computing technique of embedded Control software cycle |
| CN107038109A (en) * | 2016-02-03 | 2017-08-11 | 龙芯中科技术有限公司 | Interruption delay method of testing and device based on MIPS frameworks |
| CN109491877A (en) * | 2017-09-12 | 2019-03-19 | 江西洪都航空工业集团有限责任公司 | A kind of flight control computer software time-consuming calculation method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6530031B1 (en) * | 1999-11-08 | 2003-03-04 | International Business Machines Corporation | Method and apparatus for timing duration of initialization tasks during system initialization |
-
2003
- 2003-05-30 CN CNB031381375A patent/CN1295614C/en not_active Expired - Lifetime
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102404497B (en) * | 2010-09-16 | 2015-11-25 | 北京中星微电子有限公司 | A kind of digital zooming method of picture pick-up device and device |
| CN102404497A (en) * | 2010-09-16 | 2012-04-04 | 北京中星微电子有限公司 | Digital zoom method and device for image pickup equipment |
| CN102457268A (en) * | 2010-10-15 | 2012-05-16 | 北京德威特电力系统自动化有限公司 | Implementation method for 32-bit capture register |
| CN102457268B (en) * | 2010-10-15 | 2014-10-22 | 北京德威特继保自动化科技股份有限公司 | Implementation method for 32-bit capture register |
| CN102087513A (en) * | 2010-12-14 | 2011-06-08 | 广东雅达电子股份有限公司 | Timing extension method of PLC (programmable logic controller) timer |
| CN104850458A (en) * | 2014-02-15 | 2015-08-19 | 瞿浩正 | Timestamp based method for measuring million instructions per second (MIPS) required by embedded software module |
| CN103823756A (en) * | 2014-03-06 | 2014-05-28 | 北京京东尚科信息技术有限公司 | Method for running application under test and scheduler |
| CN105653242A (en) * | 2015-12-28 | 2016-06-08 | 北京经纬恒润科技有限公司 | Timing method and apparatus |
| CN105653242B (en) * | 2015-12-28 | 2018-01-26 | 北京经纬恒润科技有限公司 | A kind of clocking method and device |
| CN107038109A (en) * | 2016-02-03 | 2017-08-11 | 龙芯中科技术有限公司 | Interruption delay method of testing and device based on MIPS frameworks |
| CN107038109B (en) * | 2016-02-03 | 2019-12-13 | 龙芯中科技术有限公司 | interrupt delay testing method and device based on MIPS framework |
| CN106066829A (en) * | 2016-06-13 | 2016-11-02 | 江西洪都航空工业集团有限责任公司 | A kind of missile-borne time-consuming real-time computing technique of embedded Control software cycle |
| CN109491877A (en) * | 2017-09-12 | 2019-03-19 | 江西洪都航空工业集团有限责任公司 | A kind of flight control computer software time-consuming calculation method |
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| Publication number | Publication date |
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| CN1295614C (en) | 2007-01-17 |
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