CN105653242A - Timing method and apparatus - Google Patents
Timing method and apparatus Download PDFInfo
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- CN105653242A CN105653242A CN201511001181.0A CN201511001181A CN105653242A CN 105653242 A CN105653242 A CN 105653242A CN 201511001181 A CN201511001181 A CN 201511001181A CN 105653242 A CN105653242 A CN 105653242A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
Abstract
The invention discloses a timing method and apparatus. The method comprises the steps of determining the value of a current bit; setting a level as a first preset level corresponding to the value of the current bit and determining a first time parameter corresponding to the first preset level, wherein the first time parameter is used for representing the duration of the first preset level; when the duration of the first preset level is up, entering an interruption program, setting the level as a second preset level corresponding to the value of the current bit and determining a second time parameter corresponding to the second preset level, wherein the second time parameter is used for representing the duration of the second preset level; and when the duration of the second preset level is up, enabling a next bit of the current bit to serve as the current bit and returning to execute the step of determining the value of the current bit until the current bit is a last byte. Through the method and apparatus, quick and accurate timing can be realized without the need for adjusting timing parameters.
Description
Technical field
The present invention relates to wireless communication technology field, say more specifically, relate to a kind of timing method and device.
Background technology
In prior art, adopt the mode of software delay (such as circulation) to carry out timing more, concrete, every time after the level of adjustment port, suitable cycle index is set, to reach timing object.
Above-mentioned timing mode adds decision condition or amendment decision condition before timing or after timing, the cycle index all needing setting for circulation again is (namely, timing parameter), and this assignment procedure is the physical length being observed timing by oscilloscope, carry out adjusting again, finally to be obtained appropriate timing parameter quite consuming time, and accuracy is not high. Such as, performing empty for and circulate 100 times, measuring result is timing 500us, therefore uses 100 as 500us timing parameter; If but before carrying out timing, add other statements, such as judgement/assignment, timing result may be caused to turn into 600us, therefore, time in order to carry out the timing of 500us, first use 80 as timing parameter, it is 400us by oscilloscope observations, so needing adjustment timing parameter to be 100, be 510us by oscilloscope observations again, then adjusting timing parameter again is 98, just obtains the result closest to 500us.
Summary of the invention
In view of this, the present invention provides a kind of timing method and device, to overcome in prior art owing to adding decision condition or amendment decision condition before timing or after timing, the cycle index all needing setting for circulation again is (namely, timing parameter), and this assignment procedure is the physical length being observed timing by oscilloscope, then carry out adjusting, finally to be obtained appropriate timing parameter quite consuming time, and the problem that accuracy is not high.
For achieving the above object, the present invention provides following technical scheme:
A kind of timing method, described method comprises:
Determine the value of present bit;
Level is set to first predetermined level corresponding with the value of described present bit, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting;
When reaching described first predetermined level lasting long time, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting;
When reaching described 2nd predetermined level lasting long time, make next position of described present bit as present bit, and return the step performing the described value determining present bit, till described present bit is last byte.
Preferably, described level is set to first predetermined level corresponding with described present bit, specifically comprises:
Timing mark is set to first particular value corresponding with the value of described present bit;
Level is set to first predetermined level corresponding with described first particular value;
Then, described level is set to two predetermined level corresponding with described present bit, specifically comprises:
Timing mark is set to two particular value corresponding with the value of described present bit;
Level is set to two predetermined level corresponding with described 2nd particular value.
Preferably, the value of described present bit is 0 or 1.
Preferably, when the value of described present bit is 0, described first particular value is 0-H, and described 2nd particular value is 0-L; Or, described first particular value is 0-L, and described 2nd particular value is 0-H; When the value of described present bit is 1, described first particular value is 1-H, and described 2nd particular value is 1-L; Or, described first particular value is 1-L, and described 2nd particular value is 1-H.
Preferably, when described first particular value is 0-H, when described 2nd particular value is 0-L, and, when described first particular value is 1-H, when described 2nd particular value is 1-L, described first predetermined level is high level, and described 2nd predetermined level is lower level; When described first particular value is 0-L, when described 2nd particular value is 0-H, and, when described first particular value is 1-L, when described 2nd particular value is 1-H, described first predetermined level is lower level, and described 2nd predetermined level is high level.
A kind of timing device, described device comprises:
Determining unit, for determining the value of present bit;
Level setting unit, for level is set to first predetermined level corresponding with the value of described present bit, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting;
Interrupt unit, for when reaching described first predetermined level lasting long time, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting;
Cycling element, for when reaching described 2nd predetermined level lasting long time, make next position of described present bit as present bit, and trigger the step that determining unit performs the described value determining present bit, till described present bit is last byte.
Preferably, described level setting unit specifically for:
Timing mark is set to first particular value corresponding with the value of described present bit;
Level is set to first predetermined level corresponding with described first particular value;
Then described interruption unit specifically for:
Timing mark is set to two particular value corresponding with the value of described present bit;
Level is set to two predetermined level corresponding with described 2nd particular value.
Preferably, the value of described present bit is 0 or 1.
Preferably, when the value of described present bit is 0, described first particular value is 0-H, and described 2nd particular value is 0-L; Or, described first particular value is 0-L, and described 2nd particular value is 0-H;When the value of described present bit is 1, described first particular value is 1-H, and described 2nd particular value is 1-L; Or, described first particular value is 1-L, and described 2nd particular value is 1-H.
Preferably, when described first particular value is 0-H, when described 2nd particular value is 0-L, and, when described first particular value is 1-H, when described 2nd particular value is 1-L, described first predetermined level is high level, and described 2nd predetermined level is lower level; When described first particular value is 0-L, when described 2nd particular value is 0-H, and, when described first particular value is 1-L, when described 2nd particular value is 1-H, described first predetermined level is lower level, and described 2nd predetermined level is high level.
Via above-mentioned technical scheme it will be seen that compared with prior art, the present invention discloses a kind of timing method and device, it is determined that the value of present bit; Level is set to first predetermined level corresponding with the value of described present bit, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting; When reaching described first predetermined level lasting long time, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting; When reaching described 2nd predetermined level lasting long time, make next position of described present bit as present bit, and return the step performing the described value determining present bit, till described present bit is last byte. By aforesaid method and device, quick and precisely timing can be realized under the prerequisite without the need to adjusting timing parameter.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, it is briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, it is also possible to obtain other accompanying drawing according to the accompanying drawing provided.
Fig. 1 is the schematic flow sheet of a kind of timing method disclosed in the embodiment of the present invention;
Fig. 2 is the disclosed a kind of code level schematic diagram of the embodiment of the present invention;
Fig. 3 is the schematic flow sheet of disclosed another kind of timing method of the embodiment of the present invention;
Fig. 4 is the disclosed a kind of waveform diagram of the embodiment of the present invention;
Fig. 5 is the concrete structural representation of a kind of timing device disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only the present invention's part embodiment, instead of whole embodiments. Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Term " first " in the specification sheets of the present invention and claim book and above-mentioned accompanying drawing, " the 2nd " etc. are for distinguishing similar object, and need not be used for describing specific order or precedence. Should be appreciated that the term of use like this can exchange in the appropriate case, this is only describe in embodiments of the invention the differentiation mode adopted by the object of same alike result when describing.In addition, term " comprises " and " having " and their any distortion, intention is to cover does not arrange his comprising, to comprise the process of a series of unit, method, system, product or equipment being not necessarily limited to those unit, but can comprise that clearly do not list or for intrinsic other unit of these processes, method, product or equipment.
From background technology, in prior art, decision condition or amendment decision condition is added before timing or after timing, the cycle index all needing setting for circulation again is (namely, timing parameter), and this assignment procedure is the physical length being observed timing by oscilloscope, then carry out adjusting, finally to be obtained appropriate timing parameter quite consuming time, and accuracy is not high.
For this reason, this application discloses a kind of timing method and device, it is determined that the value of present bit; Level is set to first predetermined level corresponding with the value of described present bit, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting; When reaching described first predetermined level lasting long time, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting; When reaching described 2nd predetermined level lasting long time, make next position of described present bit as present bit, and return the step performing the described value determining present bit, till described present bit is last byte. By aforesaid method and device, quick and precisely timing can be realized under the prerequisite without the need to adjusting timing parameter.
For enabling above-mentioned purpose, the feature and advantage of the present invention more become apparent, below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Referring to accompanying drawing 1, the schematic flow sheet of a kind of timing method disclosed in the embodiment of the present invention, the method specifically comprises the steps:
S101: the value determining present bit.
In the present embodiment, the value of present bit can be binary zero or 1, it is possible to think other systems 0,1,2 ..., n. Such as, one frame message comprises 21 bytes, i.e. 168 positions (bit), but owing to mcu resource is limited, disposable these 168 bit can not be read into internal memory, therefore take the mode of value one by one, namely a frame message to be read complete, need 168 for circulations, every circulation primary, it is necessary to determine the value of current bit (the 5th such as the 2nd byte).
S102: level is set to first predetermined level corresponding with the value of described present bit, and determine the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting.
In the present embodiment, the first predetermined level can be high level, it is possible to think lower level.
S103: time long when reaching described first predetermined level lasting, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting.
In the present embodiment, when the first predetermined level is high level, the 2nd predetermined level is then lower level, and when the first predetermined level is lower level, the 2nd predetermined level is then high level.
S104: time long when reaching described 2nd predetermined level lasting, make next position of described present bit as present bit, and return the step performing the described value determining present bit, till described present bit is last byte.
Taking the value of present bit as the 0, first predetermined level for high level, the 2nd predetermined level is lower level, and very first time parameter is 200us, and the 2nd time parameter is 600us is example, then the final code level generated is as shown in Figure 2.
Present embodiment discloses a kind of timing method, it is determined that the value of present bit; Level is set to first predetermined level corresponding with the value of described present bit, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting; When reaching described first predetermined level lasting long time, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting; When reaching described 2nd predetermined level lasting long time, make next position of described present bit as present bit, and return the step performing the described value determining present bit, till described present bit is last byte. By aforesaid method, quick and precisely timing can be realized under the prerequisite without the need to adjusting timing parameter.
Referring to accompanying drawing 3, the schematic flow sheet of another kind of timing method disclosed in the embodiment of the present invention, the method specifically comprises the steps:
S201, it is determined that the value of present bit.
S202, is set to first particular value corresponding with the value of described present bit by timing mark.
In the present embodiment, the first particular value only has mark effect, welcomes positive rise or negative edge for marking waveform.
S203, is set to first predetermined level corresponding with described first particular value by level, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting.
In the present embodiment, the first predetermined level can be high level, it is possible to think lower level.
S204, time long when reaching described first predetermined level lasting, enter interrupt routine, and described timing mark is set to two particular value corresponding with the value of described present bit.
In the present embodiment, when the first particular value welcomes positive rise for marking waveform, then for marking, waveform welcomes negative edge to the 2nd particular value, contrary, when the first particular value welcomes negative edge for marking waveform, then for marking, waveform welcomes positive rise to the 2nd particular value.
S205, is set to two predetermined level corresponding with the value of described present bit by level, and determines the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting.
In the present embodiment, when the first predetermined level is high level, the 2nd predetermined level is then lower level, and when the first predetermined level is lower level, the 2nd predetermined level is then high level.
S206, time long when reaching described 2nd predetermined level lasting, make next position of described present bit as present bit, and returns the step performing the described value determining present bit, till described present bit is last position.
Present embodiment discloses a kind of timing method, it is determined that the value of present bit; Timing mark is set to first particular value corresponding with the value of described present bit; Level is set to first predetermined level corresponding with described first particular value, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting;When reaching described first predetermined level lasting long time, enter interrupt routine, and described timing mark be set to two particular value corresponding with the value of described present bit; Level is set to two predetermined level corresponding with the value of described present bit, and determines the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting; When reaching described 2nd predetermined level lasting long time, enter interrupt routine, make next byte of described present bit as present bit, and return the step performing the described value determining present bit, till described present bit is last position. By aforesaid method, quick and precisely timing can be realized under the prerequisite without the need to adjusting timing parameter.
The value of present bit is binary zero or 1, with the value of present bit be other systems 0,1,2 ..., n compare, signal state is few, coding, is not easily misread because of interference in transmitting procedure. Therefore, on the basis of above-mentioned embodiment disclosed by the invention, the present invention discloses several implementations that the value of a kind of present bit is binary zero or 1, specific as follows:
Mode one: when the value of described present bit is 0, described first particular value is 0-H, and described 2nd particular value is 0-L; When the value of described present bit is 1, described first particular value is 1-H, and described 2nd particular value is 1-L; Described first predetermined level is high level, and described 2nd predetermined level is lower level.
Mode two:
When the value of described present bit is 0, described first particular value is 0-L, and described 2nd particular value is 0-H; When the value of described present bit is 1, described first particular value is 1-L, and described 2nd particular value is 1-H; Described first predetermined level is lower level, and described 2nd predetermined level is high level.
Fig. 4 shows a kind of concrete waveform example of mode one. Wherein, when the value of present bit is 0, the time length of high level is 200us, and the low level time length is 600us, and when the value of present bit is 1, the time length of high level is 600us, and the low level time length is 200us.
Describing method in detail in above-mentioned embodiment disclosed by the invention, method for the present invention can adopt the device of various ways to realize, and therefore the invention also discloses a kind of timing device, provides specific embodiment below and be described in detail.
Referring to accompanying drawing 5, the concrete structural representation of a kind of timing device disclosed in the embodiment of the present invention, this device specifically comprises such as lower unit:
Determining unit 11, for determining the value of present bit;
Level setting unit 12, for level is set to first predetermined level corresponding with the value of described present bit, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting;
Interrupt unit 13, for when reaching described first predetermined level lasting long time, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting;
Cycling element 14, for when reaching described 2nd predetermined level lasting long time, make next position of described present bit as present bit, and trigger the step that determining unit performs the described value determining present bit, till described present bit is last byte.
Wherein, described level setting unit specifically for:
Timing mark is set to first particular value corresponding with the value of described present bit;
Level is set to first predetermined level corresponding with described first particular value;
Then described interruption unit specifically for:
Timing mark is set to two particular value corresponding with the value of described present bit;
Level is set to two predetermined level corresponding with described 2nd particular value.
Concrete, the value of described present bit is 0 or 1, and when the value of described present bit is 0, described first particular value is 0-H, and described 2nd particular value is 0-L; Or, described first particular value is 0-L, and described 2nd particular value is 0-H; When the value of described present bit is 1, described first particular value is 1-H, and described 2nd particular value is 1-L; Or, described first particular value is 1-L, and described 2nd particular value is 1-H. When described first particular value is 0-H, when described 2nd particular value is 0-L, and, when described first particular value is 1-H, when described 2nd particular value is 1-L, described first predetermined level is high level, and described 2nd predetermined level is lower level; When described first particular value is 0-L, when described 2nd particular value is 0-H, and, when described first particular value is 1-L, when described 2nd particular value is 1-H, described first predetermined level is lower level, and described 2nd predetermined level is high level.
It should be noted that, the concrete function of each unit above-mentioned realizes illustrating in detail in embodiment of the method, and the present embodiment repeats no more.
In sum:
The present invention discloses a kind of timing method and device, it is determined that the value of present bit; Level is set to first predetermined level corresponding with the value of described present bit, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting; When reaching described first predetermined level lasting long time, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting; When reaching described 2nd predetermined level lasting long time, make next position of described present bit as present bit, and return the step performing the described value determining present bit, till described present bit is last byte. By aforesaid method and device, quick and precisely timing can be realized under the prerequisite without the need to adjusting timing parameter.
In this specification sheets, each embodiment adopts the mode gone forward one by one to describe, and what each embodiment emphasis illustrated is the difference with other embodiments, between each embodiment identical similar portion mutually see. For device disclosed in embodiment, owing to it corresponds to the method disclosed in Example, so what describe is fairly simple, relevant part illustrates see method part.
It should be noted that in addition, device embodiment described above is only schematic, the wherein said unit illustrated as separating component or can may not be and physically separates, parts as unit display can be or may not be physical location, namely can be positioned at a place, or can also be distributed on multiple NE. Some or all of module wherein can be selected according to the actual needs to realize the object of the present embodiment scheme. In addition, in device embodiment accompanying drawing provided by the invention, the connection relational table between module shows to have communication connection between them, specifically can be implemented as one or more communication bus or signal wire. Those of ordinary skill in the art, when not paying creative work, are namely appreciated that and implement.
Through the above description of the embodiments, the technician of art can be well understood to the present invention and can realize by the mode that software adds required general hardware, naturally it is also possible to comprises application specific integrated circuit, dedicated cpu, private memory, special components and parts etc. by specialized hardware and realizes.Generally, all functions completed by computer program can realize with corresponding hardware easily, and, the concrete hardware structure being used for realizing same function can also be diversified, such as mimic channel, digital circuit or special circuit etc. but, under more susceptible for the purpose of the present invention condition, software program realization is better enforcement mode. based on such understanding, the technical scheme of the present invention in essence or says that part prior art contributed can embody with the form of software product, this computer software product is stored in the storage media that can read, such as the floppy disk of computer, USB flash disk, portable hard drive, read-only storage (ROM, Read-OnlyMemory), random access memory (RAM, RandomAccessMemory), magnetic disc or CD etc., comprise some instructions with so that a computer equipment (can be Personal Computer, server, or the network equipment etc.) perform the method described in each embodiment of the present invention.
In sum, above embodiment only in order to the technical scheme of the present invention to be described, is not intended to limit; Although with reference to above-described embodiment to invention has been detailed description, it will be understood by those within the art that: the technical scheme described in the various embodiments described above still can be modified by it, or wherein part technology feature is carried out equivalent replacement; And these amendments or replacement, do not make the spirit and scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution.
Claims (10)
1. a timing method, it is characterised in that, described method comprises:
Determine the value of present bit;
Level is set to first predetermined level corresponding with the value of described present bit, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting;
When reaching described first predetermined level lasting long time, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting;
When reaching described 2nd predetermined level lasting long time, make next position of described present bit as present bit, and return the step performing the described value determining present bit, till described present bit is last byte.
2. method according to claim 1, it is characterised in that, described level is set to first predetermined level corresponding with described present bit, specifically comprises:
Timing mark is set to first particular value corresponding with the value of described present bit;
Level is set to first predetermined level corresponding with described first particular value;
Then, described level is set to two predetermined level corresponding with described present bit, specifically comprises:
Timing mark is set to two particular value corresponding with the value of described present bit;
Level is set to two predetermined level corresponding with described 2nd particular value.
3. method according to claim 2, it is characterised in that, the value of described present bit is 0 or 1.
4. method according to claim 3, it is characterised in that, when the value of described present bit is 0, described first particular value is 0-H, and described 2nd particular value is 0-L; Or, described first particular value is 0-L, and described 2nd particular value is 0-H; When the value of described present bit is 1, described first particular value is 1-H, and described 2nd particular value is 1-L;Or, described first particular value is 1-L, and described 2nd particular value is 1-H.
5. method according to claim 4, it is characterized in that, when described first particular value is 0-H, when described 2nd particular value is 0-L, and, when described first particular value is 1-H, when described 2nd particular value is 1-L, described first predetermined level is high level, and described 2nd predetermined level is lower level; When described first particular value is 0-L, when described 2nd particular value is 0-H, and, when described first particular value is 1-L, when described 2nd particular value is 1-H, described first predetermined level is lower level, and described 2nd predetermined level is high level.
6. a timing device, it is characterised in that, described device comprises:
Determining unit, for determining the value of present bit;
Level setting unit, for level is set to first predetermined level corresponding with the value of described present bit, and determines the very first time parameter corresponding with described first predetermined level, long when described very first time parameter is for representing described first predetermined level lasting;
Interrupt unit, for when reaching described first predetermined level lasting long time, enter interrupt routine, level is set to two predetermined level corresponding with the value of described present bit, and determine the two time parameter corresponding with described 2nd predetermined level, long when described 2nd time parameter is for representing described 2nd predetermined level lasting;
Cycling element, for when reaching described 2nd predetermined level lasting long time, make next position of described present bit as present bit, and trigger the step that determining unit performs the described value determining present bit, till described present bit is last byte.
7. device according to claim 1, it is characterised in that, described level setting unit specifically for:
Timing mark is set to first particular value corresponding with the value of described present bit;
Level is set to first predetermined level corresponding with described first particular value;
Then described interruption unit specifically for:
Timing mark is set to two particular value corresponding with the value of described present bit;
Level is set to two predetermined level corresponding with described 2nd particular value.
8. device according to claim 7, it is characterised in that, the value of described present bit is 0 or 1.
9. device according to claim 8, it is characterised in that, when the value of described present bit is 0, described first particular value is 0-H, and described 2nd particular value is 0-L; Or, described first particular value is 0-L, and described 2nd particular value is 0-H; When the value of described present bit is 1, described first particular value is 1-H, and described 2nd particular value is 1-L; Or, described first particular value is 1-L, and described 2nd particular value is 1-H.
10. device according to claim 9, it is characterized in that, when described first particular value is 0-H, when described 2nd particular value is 0-L, and, when described first particular value is 1-H, when described 2nd particular value is 1-L, described first predetermined level is high level, and described 2nd predetermined level is lower level; When described first particular value is 0-L, when described 2nd particular value is 0-H, and, when described first particular value is 1-L, when described 2nd particular value is 1-H, described first predetermined level is lower level, and described 2nd predetermined level is high level.
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| CN109032665A (en) * | 2017-06-09 | 2018-12-18 | 龙芯中科技术有限公司 | Output processing method and device are instructed in microprocessor |
| CN110699863A (en) * | 2019-09-24 | 2020-01-17 | 杰克缝纫机股份有限公司 | Timing method, system, computer readable storage medium and server |
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| CN108825314B (en) * | 2018-05-30 | 2021-01-19 | 中广核工程有限公司 | Nuclear power plant steam turbine control platform and control method thereof |
| CN110699863A (en) * | 2019-09-24 | 2020-01-17 | 杰克缝纫机股份有限公司 | Timing method, system, computer readable storage medium and server |
| CN110699863B (en) * | 2019-09-24 | 2022-02-25 | 杰克科技股份有限公司 | Timing method, system, computer readable storage medium and server |
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| CN105653242B (en) | 2018-01-26 |
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