CN107656187B - Differential line test information determining method and device - Google Patents
Differential line test information determining method and device Download PDFInfo
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- CN107656187B CN107656187B CN201710801731.XA CN201710801731A CN107656187B CN 107656187 B CN107656187 B CN 107656187B CN 201710801731 A CN201710801731 A CN 201710801731A CN 107656187 B CN107656187 B CN 107656187B
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
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Abstract
The invention provides a method and equipment for determining differential line test information, wherein the method comprises the steps of obtaining a printed circuit board design file, wherein the printed circuit board design file contains information such as all network information and test point information of a printed circuit board, determining a network name of a differential line pair according to the printed circuit board design file, and determining test index information of the differential line pair according to the network name of the differential line pair and the printed circuit board design file. According to the differential circuit test information determining method provided by the invention, after the test index information of the differential circuit pair is extracted, the automatic equipment reads the information and carries out automatic test according to the point information, so that the test efficiency and accuracy are greatly improved, the impedance information of the whole circuit board can be tested, and the problems that the test efficiency is low and the impedance strip inside the circuit board cannot be tested in the differential impedance test of the circuit board in the prior art are solved.
Description
Technical Field
The invention relates to the technical field of circuit board testing, in particular to a method and equipment for determining differential circuit testing information.
Background
In order to improve the transmission rate and the transmission distance, high-speed serial buses are increasingly adopted in the computer industry and the communication industry to realize high-speed interconnection among chips, board cards, a back plate and service boards. The rates of these high speed serial buses range from hundreds of Mbps for conventional USB2.0, LVDS and FireWire1394, to several Gbps to 30Gbps for today's PCI-Express G1/G2, SATAG1/G2, XAUI/2XAUI, XFI. The increasing requirements for controlling the impedance of differential traces by PCB customers in the computer and communications industries have created unprecedented challenges for PCB manufacturers and high-speed PCB designers, and it is also a problem how to test these differential traces.
At present, a common practice in PCB factories is to add several impedance bars on the edge of a circuit board and then manually measure the impedance bars, which cannot reflect the actual situation of an impedance circuit in the circuit board. If the impedance strip in the test circuit board, then the test point number is too many, and the manual work can't test.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and an apparatus for determining differential line test information, so as to solve the problems that in the prior art, for testing differential impedance of a circuit board, the test efficiency is low and an impedance bar inside the circuit board cannot be tested.
Therefore, the embodiment of the invention provides the following technical scheme:
the embodiment of the invention provides a method for determining differential line test information, which comprises the following steps: acquiring a printed circuit board design file; determining the network name of the differential circuit pair according to the printed circuit board design file; and determining the test index information of the differential circuit pair according to the network name and the printed circuit board design file.
Optionally, the printed circuit board design file includes a network information file, where the network information file records a network name and an identifier of whether each network is a differential network; the determining the network name of the differential circuit pair according to the printed circuit board design file comprises the following steps: and extracting the network names of the differential line pairs from the network information file according to the network names in the network information file and the identification of whether each network is a differential network.
Optionally, the printed circuit board design file includes a test point information file, and the test point information file records a network name and corresponding endpoint coordinate information; the test index information includes coordinate information of the same-end test point of the differential line pair.
Optionally, the determining test index information of the differential circuit pair according to the network name and the printed circuit board design file includes: inquiring the network name of the differential circuit pair and the corresponding endpoint coordinate information in the test point information file; and determining coordinate information of the same-end test point according to the endpoint coordinate information.
Optionally, the determining coordinate information of the peer test point according to the endpoint coordinate information includes: determining the end point coordinate information with the same horizontal coordinate value; and selecting a group of end point coordinate information with the same abscissa value as the coordinate information of the same-end test point.
Optionally, the test index information further includes angle information between the same-end test points.
Optionally, after determining the coordinate information of the peer test point, the method further includes: and obtaining the angle information between the same-end test points by utilizing an arc tangent formula.
Optionally, the test index information further includes information of distances between the same-end test points.
Optionally, after determining the coordinate information of the peer test point, the method further includes: and calculating the distance information between the same-end test points by using a distance formula between two points and the coordinate information of the same-end test points.
Optionally, the printed circuit board design file includes a line width information file, and the line width information file records a network name and corresponding line length information of a layer where the network name is located; the test index information includes line length information of the layer where the test index information is located.
Optionally, the determining test index information of the differential circuit pair according to the network name and the printed circuit board design file includes: inquiring the network name of the differential circuit pair in the line width information file; comparing the inquired line length information of the layer corresponding to the network name of the differential line pair; the line length information of the layer having the maximum value is extracted.
Optionally, the printed circuit board design file includes a line width information file and an impedance design value file, and the line width information file records a network name, corresponding layer information and line length information of the layer; the impedance design value file records layer information and at least one of corresponding line width information, corresponding impedance information and corresponding tolerance information; the test indicator information includes at least one of line width information, impedance information, and tolerance information.
Optionally, the step of determining test index information of the differential circuit pair according to the network name and the printed circuit board design file includes: inquiring the network name of the differential circuit pair in the line width information file; comparing the inquired line length information of the layer corresponding to the network name of the differential line pair; extracting the information of the layer corresponding to the line length information of the layer with the maximum value; inquiring the extracted information of the layer in the impedance design value file; and extracting at least one of the line width information, the corresponding impedance information and the corresponding tolerance information corresponding to the inquired layer information.
Optionally, the printed circuit board design file includes a line width information file, and the line width information file records a network name and corresponding total line length information; the test indicator information includes total length of line information.
Optionally, the step of determining test index information of the differential circuit pair according to the network name and the printed circuit board design file includes: inquiring the network name of the differential circuit pair in the line width information file; and extracting total line length information corresponding to the inquired network name.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the differential line test information determining method according to any one of claims 1 to 15.
An embodiment of the present invention further provides a computer device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to cause the at least one processor to perform the differential line test information determination method of any one of claims 1-15.
The technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a method and equipment for determining differential line test information. According to the differential circuit test information determining method provided by the embodiment of the invention, after the test index information of the differential circuit pair is extracted, the automatic equipment reads the information and carries out automatic test according to the point information, so that the test efficiency and accuracy are greatly improved, the impedance information of the whole circuit board can be tested, and the problems that the test efficiency is low and the impedance strip inside the circuit board cannot be tested in the differential impedance test of the circuit board in the prior art are solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a differential line test information determination method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a network of differential line pairs for a differential line test information determination method according to an embodiment of the invention;
FIG. 3 is a flowchart of a method for determining coordinate information of test points at the same end of a differential line according to a preferred embodiment of the present invention;
fig. 4 is a flowchart of a line length information determination method of a layer where a differential line has a maximum value according to a preferred embodiment of the present invention;
FIG. 5 is a flow chart of a differential line test information determination method in accordance with a preferred embodiment of the present invention;
fig. 6 is a flowchart of a differential line total length information determining method according to a preferred embodiment of the present invention;
fig. 7 is a hardware configuration diagram of a computer device of the differential line test information determination method according to the embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
In this embodiment, a differential line test information determining method is provided, and fig. 1 is a flowchart of a differential line test information determining method according to an embodiment of the present invention, as shown in fig. 1, the flowchart includes the following steps:
s101: acquiring a printed circuit board design file; after the PCB is designed, a PCB design file can be automatically extracted according to design software cadence, the PCB design file comprises a plurality of types, such as a test point information file, a line width information file, an impedance design value file and the like, and one or more types can be obtained.
S102: determining the network name of the differential circuit pair according to the printed circuit board design file; the extracted printed circuit board design file contains all network information of the PCB and information such as whether the PCB is a differential network or not, and therefore the network name of the differential line pair can be determined.
S103: and determining the test index information of the differential circuit pair according to the network name of the differential circuit pair and the printed circuit board design file. Specifically, the printed circuit board design file includes various information, such as test point information, line width information, impedance design value information, and the like, and according to the network name of the differential line pair, test index information of the differential line pair to be tested, such as a test point position, a distance between test points, a length of the differential line, and the like, can be extracted from various files.
According to the differential line test information determining method provided by the embodiment of the invention, the network name of the differential line pair is determined according to the printed circuit board design file by obtaining the printed circuit board design file, and the test index information of the differential line pair is determined according to the network name and the printed circuit board design file, so that the indexes required to be detected by all the differential line pairs on the circuit board can be automatically determined according to the method. After the test index information of the differential circuit pair is extracted, the automatic equipment can automatically detect the circuit board based on the information, and compares the detected information with the extracted test index information to determine whether the differential circuit pair on the circuit board is abnormal.
Specifically, the printed circuit board design file includes a network information file, where the network information file records a network name and an identifier of whether each network is a differential network, such as all network information of the PCB, including the network name, whether each network is a differential network, an electrical length, a PIN number, and the like, and the step S102 involves determining the network name of the differential line pair according to the printed circuit board design file, in one embodiment, extracting the network name of the differential line pair from the network information file according to the network name in the network information file and the identifier of whether each network is a differential network, for example:
Item3(NET)
Net Name:$40I575\DDRH_DQS3_N
Member of Diff Pair:$40I575\DDRH_DQS3_
Item 7(NET)
Net Name:$40I575\DDRH_DQS3_P
Member of Diff Pair:$40I575\DDRH_DQS3_
a group of differential test Pair network information of $40I575\ DDRH _ DQS3_ N and $40I575\ DDRH _ DQS3_ P is extracted according to the information of the "Member of Diff Pair", and the network schematic diagram of the extracted differential line Pair is shown in FIG. 2.
In an optional embodiment, the printed circuit board design file includes a test point information file, usually in an IPC-356 file format, where the file records information of a network name, a coordinate, a layer where the file is located, that is, the test point information file records the network name and corresponding endpoint coordinate information, and the test index information of the differential circuit includes coordinate information of the test point at the same end of the differential circuit pair. The step S103 involves determining the test index information of the differential circuit pair according to the network name of the differential circuit pair and the printed circuit board design file, as shown in fig. 3, the step S103 may specifically include the following steps:
S1031A, inquiring the network name of the differential line pair and the corresponding endpoint coordinate information in the test point information file;
S1032A, determining coordinate information of the same-end test point according to the coordinate information of the end point.
The automatic detection equipment can search the same-end test point on the circuit board according to the coordinate information of the same-end test point, and judge whether the same-end test point exists at the position indicated by the coordinate information according to the impedance signal, so as to determine whether the position of the actual same-end test point on the circuit board is consistent with that of the same-end test point during design, and when the position is not consistent, the detected abnormality of the same-end test point can be recorded.
S1032A may specifically include the following steps:
S1032A1, determining the endpoint coordinate information with the same abscissa value;
s1032a2, selecting a set of end point coordinate information with the same abscissa value as the same end point coordinate information. For example, a difference test pair has four endpoint coordinate information values in total, and two endpoint coordinates with the same abscissa value are found, namely the coordinate information of the same-end test point.
For example, in one embodiment, the network names of the differential line pair are $40I575\ DDRH _ DQS3_ N and $40I575\ DDRH _ DQS3_ P, and the corresponding coordinate information is as follows:
$40I575\DDRH_DQS3_N A01X+013517Y-001376X0180Y0180R270S0
$40I575\DDRH_DQS3_P A01X+013517Y-001927X0200Y0200R270S1
therefore, the coordinates of one endpoint corresponding to the network name $40I575\ DDRH _ DQS3_ N are (13517, -1376), and the coordinates of one endpoint corresponding to the network name $40I575\ DDRH _ DQS3_ P are (13517, -1927), because the coordinates of the endpoints (13517, -1376) and (13517, -1927) are the same, it is determined that the two endpoints are coordinate points of the same endpoint, and therefore the two coordinates are coordinate information of the test points of the same endpoint, and the automatic device determines whether the coordinates of the actual test points of the same endpoint are abnormal according to the positions of the test points of the same endpoint during design.
In an optional embodiment, the printed circuit board design file includes a test point information file, the test point information file records a network name and corresponding endpoint coordinate information, and the test index information includes coordinate information of the same-end test points of the differential circuit pair, and also includes angle information between the same-end test points.
And obtaining the angle information between the same-end test points by utilizing an arc tangent formula. Specifically, after coordinate information of the same-end test points of the differential line pair is obtained, for example, coordinate values of two same-end test points are: point 1 coordinate value is (x)1,y1) The coordinate value of point 2 is (x)2,y2) The angle between two points can then be according to the arctan formula:
angular information between the two points is found. For example, for the above-mentioned co-terminal test point coordinates (13517, -1376) and (13517, -1927), the angle formed by the two endpoints is 270 ° as obtained by the arctan equation:
after reading the angle information among the same-end test points, the automation equipment determines whether the actual angles of the same-end test points are consistent or not according to the angle information of the same-end test points during design, and if not, the detected same-end test points are recorded to be abnormal, so that the detection efficiency is improved.
In an optional embodiment, the printed circuit board design file includes a test point information file, the test point information file records a network name and corresponding endpoint coordinate information, and the test index information includes coordinate information of the same-end test points of the differential circuit pair and distance information between the same-end test points.
After the coordinate information of the same-end test points is determined, the distance information between the same-end test points is calculated by using a distance formula between two points and the coordinate information of the same-end test points. For example, the coordinate values of the two same-end test points are: point 1 coordinate value is (x)1,y1) The coordinate value of point 2 is (x)2,y2) Then the distance between two points can be calculated according to the distance formula between two points:
for example, for the coordinates (13517, -1376) and (13517, -1927) of the same-end test point, the distance between the two end points is calculated by the formula of the distance between the two end points as follows:
after reading the distance information between the same-end test points, the automation equipment determines whether the actual distances of the same-end test points are consistent or not according to the distance information of the same-end test points during design, and if not, the detected same-end test points are recorded to be abnormal, so that the detection efficiency is improved.
In an alternative embodiment, the printed circuit board design file includes a line width information file, the line width information file records a network name and corresponding line length information of a layer where the network name is located, and the test index information includes differential line length information of the layer where the network name is located.
As shown in fig. 4, the step S103 may include the steps of:
S1031B, inquiring the network name of the differential line pair in the line width information file;
S1032B, comparing the line length information of the layer corresponding to the network name of the inquired differential line pair;
S1033B, the line length information of the layer where the maximum value exists is extracted. In the PCB, there may be a plurality of circuit board layers, and the differential lines may have different wiring lengths on each layer of the circuit board, and the differential line length on the layer having the maximum value is extracted according to the extracted differential line length on each layer of the printed circuit board corresponding to the network name of the differential line pair.
And the automation equipment compares the extracted differential line length information with the differential line length information during design to judge whether the differential line length arrangement in the circuit board is reasonable or not.
In an optional embodiment, the printed circuit board design file includes a line width information file and an impedance design value file, the line width information file records a network name and corresponding layer information and line length information of the layer, the impedance design value file records layer information and at least one of corresponding line width information, corresponding impedance information and corresponding tolerance information, and the test index information includes at least one of line width information, impedance information and tolerance information.
As shown in fig. 5, the step S103 may include the steps of:
S1031C, inquiring the network name of the differential line pair in the line width information file; the printed circuit board design file comprises a line width information file and an impedance design value file, wherein the line width information file records a network name, corresponding layer information and line length information of the layer;
S1032C, comparing the line length information of the layer corresponding to the network name of the inquired differential line pair;
S1033C, extracting the layer information corresponding to the line length information of the layer with the maximum value; for example, the line width information of the differential lines obtained from the network names of the differential line pair $40I575\ DDRH _ DQS3_ N and $40I575\ DDRH _ DQS3_ P of the network names of the differential line pair is shown in table 1.
TABLE 1
| Network name | Layer name | Total length (mils) | Line width (mils) | Length of layer (mils) |
| $40I575\DDRH_DQS3_N | top | 219.54 | 5 | 22.3 |
| $40I575\DDRH_DQS3_N | ART22 | 219.54 | 4.5 | 197.24 |
| $40I575\DDRH_DQS3_P | top | 219.54 | 5 | 22.3 |
| $40I575\DDRH_DQS3_P | ART22 | 219.54 | 4.5 | 197.24 |
According to the network name of the differential line pair and the characteristic that the line length of the differential line in the circuit board is longer, data required by the 2 nd row and the 4 th row are obtained from the table 1, namely the layer where the differential line is located is an ART22 layer.
S1034C, inquiring the extracted information of the layer in the impedance design value file; the impedance design value file records layer information and at least one of corresponding line width information, corresponding impedance information and corresponding tolerance information; for example, the impedance design value information table is shown in table 2.
TABLE 2
| Layer(s) | Single ended/differential | Line width | Impedance (L) | Tolerance of |
| top | Difference of difference | 5 | 50 | 10％ |
| ART22 | Difference of difference | 4.5 | 50 | 10％ |
In step S1033C, the layer where the differential line is located is the ART22 layer, and thus the 2 nd row of data in table 2 is the required data.
S1035C, extracting at least one of the line width information, the impedance information, and the tolerance information corresponding to the inquired layer information. Specifically, by integrating the information of the differential line pairs in tables 1 and 2, the obtained differential line test information data is shown in table 3.
TABLE 3
In an optional embodiment, the printed circuit board design file comprises a line width information file, and the line width information file records a network name and corresponding total line length information; the test indicator information includes total length of line information.
As shown in fig. 6, the step S103 may include the steps of:
S1031D, inquiring the network name of the differential line pair in the line width information file; the line width information file records a network name and corresponding total line length information;
S1032D, the total length of line information corresponding to the queried network name is extracted. In the printed circuit board, the total length of the differential lines includes the total length of the differential lines passing through each layer of the circuit board. For example, in table 1 of the line width information of the differential line, the total length information of the differential line is 219.54 mils.
With the differential circuit test information determining method in the above embodiment, a set of test pair data required by the finally obtained automated test is shown in table 5:
TABLE 5
And after reading the line length information, the line width information, the impedance information, the tolerance information and the spacing information between the test points of the layer with the maximum value by the automatic equipment, calculating an actual impedance value, if the impedance value is within a designed impedance value range, the differential line is designed to be qualified, and if the impedance value exceeds the designed impedance value range, the impedance design of the differential line is recorded to be unqualified.
By the differential circuit test information determining method, all differential circuit pair data in the PCB design file can be automatically extracted, automatic equipment reads the data, automatic test is carried out according to point information, test efficiency and accuracy are greatly improved, and impedance test can be carried out on the whole printed circuit board.
Example 2
The embodiment of the invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions can execute the differential line test information determination method in any method embodiment. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a hard disk (hard disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
Example 3
Fig. 7 is a schematic diagram of a hardware structure of a computer device of a differential line test information determining method according to an embodiment of the present invention, as shown in fig. 7, the device includes one or more processors 710 and a memory 720, and one processor 710 is taken as an example in fig. 7.
The apparatus for performing the differential line test information determining method may further include: an input device 730 and an output device 740.
The processor 710, the memory 720, the input device 730, and the output device 740 may be connected by a bus or other means, such as the bus connection in fig. 7.
The memory 720, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the differential line test information determining method in the embodiments of the present application. The processor 710 executes various functional applications and data processing of the server by executing non-transitory software programs, instructions and modules stored in the memory 720, namely, implements the differential line test information determination method in the above method embodiment.
The memory 720 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by use of the differential line test information determination device, and the like. Further, the memory 720 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 720 optionally includes memory located remotely from processor 710, and these remote memories may be connected over a network to a processing device determined by the differential line test information. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 730 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the differential line test information determination processing device. The output device 740 may include a display device such as a display screen.
The one or more modules are stored in the memory 720 and, when executed by the one or more processors 710, perform the methods illustrated in fig. 1-6.
The above-mentioned product can execute the method provided by the embodiment of the present invention, and has corresponding functional modules and beneficial effects of the execution method and technical details that are not described in detail in the embodiment, which can be specifically referred to the related descriptions in the embodiments shown in fig. 1 to fig. 6.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (16)
1. A differential line test information determining method is characterized by comprising the following steps:
acquiring a printed circuit board design file; the printed circuit board design file comprises a test point information file, and the test point information file records a network name and corresponding endpoint coordinate information;
determining the network name of the differential circuit pair according to the printed circuit board design file;
determining test index information of the differential circuit pair according to the network name and the printed circuit board design file; the test index information comprises coordinate information of the same-end test points of the differential circuit pair;
the differential line test information determining method further includes:
searching the same-end test points on the printed circuit board according to the coordinate information of the same-end test points, and judging whether the same-end test points exist in the positions indicated by the coordinate information of the same-end test points according to impedance signals;
and when the same-end test point does not exist in the position indicated by the coordinate information of the same-end test point, determining that the position of the actual same-end test point on the printed circuit board is inconsistent with the position of the same-end test point in design, and recording the abnormality of the same-end test point.
2. The differential line test information determining method according to claim 1, wherein the printed circuit board design file includes a network information file, and the network information file records a network name and an identifier of whether each network is a differential network; the determining the network name of the differential circuit pair according to the printed circuit board design file comprises the following steps:
and extracting the network names of the differential line pairs from the network information file according to the network names in the network information file and the identification of whether each network is a differential network.
3. The method for determining differential line test information according to claim 1, wherein the determining test index information of the differential line pair from the network name and the printed circuit board design file includes:
inquiring the network name of the differential circuit pair and the corresponding endpoint coordinate information in the test point information file;
and determining coordinate information of the same-end test point according to the endpoint coordinate information.
4. The method of claim 3, wherein the determining the co-terminal test point coordinate information based on the terminal point coordinate information comprises:
determining the end point coordinate information with the same horizontal coordinate value;
and selecting a group of end point coordinate information with the same abscissa value as the coordinate information of the same-end test point.
5. The differential line test information determining method according to claim 1, wherein the test index information further includes angle information between the same-end test points.
6. The differential line test information determining method of claim 5, further comprising, after determining the same-end test point coordinate information:
and obtaining the angle information between the same-end test points by utilizing an arc tangent formula.
7. The differential line test information determining method according to claim 1, wherein the test index information further includes information on a distance between the same-end test points.
8. The differential line test information determining method of claim 7, further comprising, after determining the same-end test point coordinate information:
and calculating the distance information between the same-end test points by using a distance formula between two points and the coordinate information of the same-end test points.
9. The method according to claim 1, wherein the printed circuit board design file includes a line width information file, and the line width information file records a network name and line length information of a corresponding layer; the test index information includes line length information of the layer where the test index information is located.
10. The method for determining differential line test information according to claim 9, wherein the determining test index information of the differential line pair from the network name and the printed circuit board design file includes:
inquiring the network name of the differential circuit pair in the line width information file;
comparing the inquired line length information of the layer corresponding to the network name of the differential line pair;
the line length information of the layer having the maximum value is extracted.
11. The method for determining differential line test information according to claim 1, wherein the printed circuit board design file includes a line width information file and an impedance design value file, and the line width information file records a network name, corresponding layer information and line length information of the layer; the impedance design value file records layer information and at least one of corresponding line width information, corresponding impedance information and corresponding tolerance information; the test indicator information includes at least one of line width information, impedance information, and tolerance information.
12. The differential line test information determining method according to claim 11, wherein the step of determining test index information of the differential line pair based on the network name and the printed circuit board design file includes:
inquiring the network name of the differential circuit pair in the line width information file;
comparing the inquired line length information of the layer corresponding to the network name of the differential line pair;
extracting the information of the layer corresponding to the line length information of the layer with the maximum value;
inquiring the extracted information of the layer in the impedance design value file;
and extracting at least one of the line width information, the corresponding impedance information and the corresponding tolerance information corresponding to the inquired layer information.
13. The differential line test information determining method according to claim 1, wherein the printed circuit board design file includes a line width information file, the line width information file recording a network name and corresponding line total length information; the test indicator information includes total length of line information.
14. The differential line test information determining method according to claim 13, wherein the step of determining test index information of the differential line pair from the network name and the printed circuit board design file includes:
inquiring the network name of the differential circuit pair in the line width information file;
and extracting total line length information corresponding to the inquired network name.
15. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out a differential line test information determination method according to any one of claims 1 to 14.
16. A computer device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to cause the at least one processor to perform the differential line test information determination method of any one of claims 1-14.
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| CN201710801731.XA CN107656187B (en) | 2017-09-07 | 2017-09-07 | Differential line test information determining method and device |
| PCT/CN2017/114422 WO2019047392A1 (en) | 2017-09-07 | 2017-12-04 | Differential line testing information determination method and device |
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| CN201710801731.XA CN107656187B (en) | 2017-09-07 | 2017-09-07 | Differential line test information determining method and device |
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| CN112444676A (en) * | 2019-08-27 | 2021-03-05 | 南京泊纳莱电子科技有限公司 | Resistance detection method and device, resistance detector and readable storage medium |
| CN112946365B (en) * | 2021-03-01 | 2024-05-28 | 广州广合科技股份有限公司 | Method for automatically manufacturing impedance test file, electronic equipment and storage medium |
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| CN107656187A (en) | 2018-02-02 |
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