CN113704035B - Time delay detection method and device and related equipment - Google Patents
Time delay detection method and device and related equipment Download PDFInfo
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- CN113704035B CN113704035B CN202110987890.XA CN202110987890A CN113704035B CN 113704035 B CN113704035 B CN 113704035B CN 202110987890 A CN202110987890 A CN 202110987890A CN 113704035 B CN113704035 B CN 113704035B
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The application discloses a time delay detection method, which comprises the steps of obtaining signal line information and PCB lamination information; calculating to obtain the length of the signal wire according to the signal wire information and the PCB lamination information; calculating according to the length of the signal line and the signal propagation speed to obtain signal time delay; calculating the time delay of each signal by using a transmission time delay formula to obtain the transmission time delay; when the transmission delay does not exceed the standard, delaying, and outputting a detection passing prompt; the delay detection method can effectively improve the delay detection efficiency of the PCIE common clock and improve the accuracy of detection results. The application also discloses a time delay detection device, equipment and a computer readable storage medium, which have the beneficial effects.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method for detecting a time delay, and a device, an apparatus, and a computer readable storage medium for detecting a time delay.
Background
Currently, for evaluation and inspection of a PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) common clock design, the line length is generally manually searched and sorted, and then the delay and sorting report are calculated. Obviously, the implementation mode is more dependent on manual experience, is time-consuming and labor-consuming, needs frequent repeated operation, is low in efficiency, and cannot effectively guarantee the accuracy of the inspection result.
Therefore, how to effectively improve the delay detection efficiency of the PCIE common clock and improve the accuracy of the detection result at the same time is a problem to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide a time delay detection method which can effectively improve the time delay detection efficiency of PCIE common clocks and improve the accuracy of detection results; another object of the present application is to provide a delay detecting apparatus, a device and a computer readable storage medium, which have the above advantages.
In a first aspect, the present application provides a method for detecting a time delay, including:
acquiring signal line information and PCB lamination information;
calculating to obtain the length of the signal wire according to the signal wire information and the PCB lamination information;
calculating according to the length of the signal line and the signal propagation speed to obtain signal time delay;
calculating the time delay of each signal by using a transmission time delay formula to obtain the transmission time delay;
and when the transmission delay does not exceed the standard, delaying and outputting a detection passing prompt.
Preferably, the calculating to obtain the signal line length according to the signal line information and the PCB lamination information includes:
determining coordinate information of each horizontal signal line segment in the corresponding signal line on the corresponding PCB layer according to the signal line information;
calculating and obtaining the horizontal total length of all horizontal signal line segments in the signal line according to the coordinate information;
calculating and obtaining the vertical total length of all vertical signal segments in the signal line according to the PCB lamination information;
and calculating according to the horizontal total length and the vertical total length to obtain the signal line length.
Preferably, before the signal delay is obtained according to the signal line length and the signal propagation speed calculation, the method further includes:
determining the dielectric constants of all PCB layers according to the PCB lamination information;
and calculating according to the light speed and each dielectric constant to obtain the signal propagation speed on the corresponding signal line segment.
Preferably, when the number of PCBs to be tested is greater than 1, the calculating the signal delays using a transmission delay formula further includes:
counting the transmission time delays corresponding to all the tested PCBs;
counting the intermediate transmission time delay of the connecting cables and/or connectors among the tested PCBs;
and calculating to obtain total transmission delay according to the transmission delay corresponding to all the tested PCBs and each intermediate transmission delay.
Preferably, the counting the intermediate transmission delay of the connecting cable and/or the connector between the PCBs under test includes:
acquiring identification information of each connecting cable and/or each connector;
and inquiring and obtaining the intermediate transmission delay of the corresponding connecting cable and/or connector from a preset database according to the identification information.
Preferably, the delay detection method further includes:
counting detection process information and detection result information;
generating a topological graph according to the detection process information and the detection result information;
and sending the topological graph to a display interface for visual display.
Preferably, the delay detection method further includes:
generating a detection report according to the detection process information and the detection result information;
archiving the detection report.
In a second aspect, the present application also discloses a delay detection device, including:
the information acquisition module is used for acquiring signal line information and PCB lamination information;
the length calculation module is used for calculating and obtaining the length of the signal wire according to the signal wire information and the PCB lamination information;
the signal delay calculation module is used for calculating and obtaining signal delay according to the length of the signal line and the signal propagation speed;
the transmission delay calculation module is used for calculating the signal delay by utilizing a transmission delay formula to obtain the transmission delay;
and the detection result output module is used for delaying when the transmission delay does not exceed the standard and outputting a detection passing prompt.
In a third aspect, the present application also discloses a delay detection device, including:
a memory for storing a computer program;
a processor for implementing the steps of any of the delay detection methods described above when executing the computer program.
In a fourth aspect, the present application also discloses a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of any of the latency detection methods described above.
The application provides a time delay detection method, which comprises the steps of obtaining signal line information and PCB lamination information; calculating to obtain the length of the signal wire according to the signal wire information and the PCB lamination information; calculating according to the length of the signal line and the signal propagation speed to obtain signal time delay; calculating the time delay of each signal by using a transmission time delay formula to obtain the transmission time delay; and when the transmission delay does not exceed the standard, delaying and outputting a detection passing prompt.
Therefore, according to the delay detection method provided by the application, automatic delay detection is realized by developing a delay detection program, when PCIE common clock delay of a PCB (Printed Circuit Board, a printed circuit board) is required to be detected, corresponding signal line information and PCB lamination information are obtained, so that signal delay detection of each signal line is realized, signal delay of each signal line is further calculated according to a transmission delay formula, PCIE common clock delay is obtained, namely the transmission delay is finally compared with standard delay, and whether the PCIE common clock delay of the PCB is qualified can be determined. Obviously, the implementation mode can realize the rapid evaluation of PCIE common clock delay, greatly improve the delay detection efficiency and improve the accuracy of the detection result.
The delay detection device, the delay detection equipment and the computer readable storage medium provided by the application have the beneficial effects and are not repeated here.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the following will briefly describe the drawings that need to be used in the description of the prior art and the embodiments of the present application. Of course, the following drawings related to embodiments of the present application are only a part of embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any inventive effort, and the obtained other drawings also fall within the scope of the present application.
Fig. 1 is a schematic flow chart of a delay detection method provided by the application;
fig. 2 is a PCIE common clock topology diagram provided by the present application;
fig. 3 is a front-end interface display diagram of PCIE common clock delay detection based on a single PCB according to the present application;
FIG. 4 is a diagram of a Clock topology of one or more Clock schemes provided by the present application;
fig. 5 is a front-end interface display diagram of PCIE common clock delay detection based on multiple PCBs according to the present application;
fig. 6 is a schematic structural diagram of a delay detection device according to the present application;
fig. 7 is a schematic structural diagram of a delay detection device provided by the present application.
Detailed Description
The core of the application is to provide a time delay detection method which can effectively improve the time delay detection efficiency of PCIE common clocks and improve the accuracy of detection results; another core of the present application is to provide a delay detecting apparatus, a device and a computer readable storage medium, which also have the above advantages.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The embodiment of the application provides a time delay detection method.
Referring to fig. 1, fig. 1 is a flow chart of a delay detection method provided by the present application, where the delay detection method may include:
s101: acquiring signal line information and PCB lamination information;
this step aims at achieving the acquisition of signal line information and PCB lamination information. Firstly, it should be noted that the delay detection method provided by the present application aims to implement PCIE common clock delay detection in a PCB, so the signal line information may be related information of all signal lines (number is not unique) included in a clock loop to be detected, and the PCB lamination information is lamination information of the PCB to be detected (the PCB generally includes multiple layers, such as a signal layer and a plane layer).
The signal line information may be a signal line name, a signal line keyword, a signal line ID, etc., which may be directly input by a user on a front page, so as to obtain the signal line information; the above-mentioned PCB lamination information may include information about names of each layer in the tested PCB, thicknesses of each layer, dielectric constants of each layer, thicknesses between layers, etc., which may be directly extracted based on the tested PCB.
S102: calculating to obtain the length of the signal wire according to the signal wire information and the PCB lamination information;
the step aims to realize the calculation of the length of the signal wire, namely the length of the signal wire is obtained according to the calculation of the information of the signal wire and the information of the PCB lamination, namely the arrangement condition of each signal wire on the corresponding PCB in the measured Zhong Huilu can be determined according to the information of the signal wire and the information of the PCB lamination, and then the calculation of the length of each signal wire is realized according to the arrangement condition of the signal wire.
As a preferred embodiment, the calculating the signal line length according to the signal line information and the PCB stacking information may include: determining coordinate information of each horizontal signal line segment in the corresponding signal line on the corresponding PCB layer according to the signal line information; calculating and obtaining the horizontal total length of all horizontal signal line segments in the signal line according to the coordinate information; calculating and obtaining the vertical total length of all vertical signal fragments in the signal line according to the PCB lamination information; the signal line length is calculated from the horizontal total length and the vertical total length.
The preferred embodiment provides a method for calculating the length of a signal line. As described above, the PCB generally includes a plurality of layers, and it is conceivable that the disposition of the signal lines on the PCB generally includes the horizontal disposition thereof on each of the layers of the PCB and the vertical disposition thereof through the layers of the plurality of PCBs by way of the layer-changing holes, and thus, for each signal line in the clock circuit, the length value thereof in the horizontal direction of the PCB to be tested and the length value thereof in the vertical direction of the PCB to be tested can be calculated, respectively, to thereby calculate and obtain the total length of the corresponding signal line, that is, the length of the signal line as described above.
In the specific implementation process, firstly, coordinate information of each horizontal signal line segment in a corresponding signal line on a corresponding PCB layer is determined according to signal line information, wherein the horizontal signal segment is a signal line segment which is horizontally arranged on each PCB layer in the corresponding signal line, and in the PCB development stage, the arrangement information of each signal line on the PCB is known, for example, the arrangement information can be stored in a corresponding storage space, so that the coordinate information of each horizontal signal line segment in the signal line on the corresponding PCB layer can be directly inquired and obtained in the storage space according to the signal line information (such as a signal line name or ID), and obviously, the coordinate information specifically comprises start-stop coordinates of the corresponding horizontal signal segment; then, calculating according to the coordinate information to obtain the length value of the corresponding horizontal signal segment, and further obtaining the total length of all horizontal signal segments in the current signal line, namely the horizontal total length, through addition calculation; further, calculating and obtaining the total length of all vertical signal segments in the current signal line, namely the vertical total length, according to PCB lamination information, wherein the vertical signal segments are vertically deployed signal line segments when corresponding signal lines penetrate through each PCB layer, and similarly, the PCB lamination information is also known in the PCB development stage, namely, the PCB lamination information can be directly extracted from a storage space; finally, the total length of the signal line can be calculated and obtained according to the horizontal total length and the vertical total length of the current signal line.
S103: calculating according to the length of the signal line and the signal propagation speed to obtain signal time delay;
the step aims at realizing signal delay calculation, and of course, the signal delay is delay information of a corresponding signal line, and is not delay of the whole clock loop. It can be understood that the signal delay of the corresponding signal line is obtained by calculating according to the length of the signal line and the signal propagation speed, specifically, the quotient of the length of the signal line and the signal propagation speed is calculated, and the quotient is the signal delay.
As a preferred embodiment, before the signal delay is obtained according to the signal line length and the signal propagation speed calculation, the method may further include: determining the dielectric constants of all PCB layers according to the PCB lamination information; and calculating according to the light speed and each dielectric constant to obtain the signal propagation speed on the corresponding signal line segment.
The step provides a method for calculating the signal propagation speed. As described above, PCBs generally include multiple layers, possibly including signal layers and planar layers, and it is understood that the materials used for each layer may not be the same, and that the propagation speeds of signals on the corresponding PCB layers may be calculated based on the dielectric constants of each PCB layer, since the propagation speeds of signals on different media are different. Specifically, the dielectric constants of the layers of each PCB in the tested PCB can be determined according to the PCB lamination information, and then the signal propagation speed on the corresponding signal line segment can be obtained through calculation according to the light speed and the dielectric constants. The calculation formula of the signal propagation speed is as follows:
v＝c/sqrt(er)；
where v is the signal propagation speed, c is the speed of light, and er is the dielectric constant.
S104: calculating the time delay of each signal by using a transmission time delay formula to obtain the transmission time delay;
the step aims at realizing transmission delay calculation, wherein the transmission delay is delay information of a clock loop, namely PCIE common clock delay. Specifically, after the signal delay corresponding to each signal line is obtained, the transmission delay formula can be used to calculate each signal delay, thereby obtaining the transmission delay.
The transmission delay formula is used for realizing transmission delay calculation, and different PCIEs share a clock topology and correspond to different transmission delay formulas. For example, referring to fig. 2, fig. 2 is a PCIE common clock topology diagram provided by the present application, communications between a motherboard and PCIE devices, specifically communications between a processor sending end in the motherboard and a receiver in the PCIE devices, where a data transmission channel and a clock transmission channel are provided between the two, and for the PCIE common clock topology diagram, a calculation formula of a transmission delay difference is as follows:
Transport Delay Delta＝Total Data Transport Delay-Total Sampling Transport Delay；
wherein Total Data Transport Delay =ext_tx_clk+int_tx_clk_data+ext_tx_data+int_rx_data;
Total Sampling Transport Delay＝Ext_Rx_clk+Int_Rx_clk；
wherein Transport Delay Delta is a transmission delay difference, total Data Transport Delay is a total data transmission delay, total Sampling Transport Delay is a total sampling transmission delay, ext_tx_clk is a CPU input clock transmission delay, int_tx_clk_data is a CPU internal clock data transmission delay, ext_tx_data is a data transmission delay between the CPU and the PCIe device, int_rx_data is a PCIe device internal data transmission delay, ext_rx_clk is a PCIe device input clock transmission delay, and int_rx_clk is a PCIe device internal clock transmission delay.
Based on the above formula, it can be derived:
Transport Delay Delta＝[Ext_Tx_clk+Int_Tx_clk_data+Ext_Tx_data+Int_Rx_data]–[Ext_Rx_clk+Int_Rx_clk]。
according to the PCIE protocol specification, transport_delay_delta PCIE requires 12ns, assuming that the intra-chip correlation Delay is <2ns (i.e., int_rx_data+int_tx_clk_data-int_rx_clk <2 ns), and the design is further tightened to 2ns, the design on the PCB can be finally evaluated by 8ns, i.e., ext_tx_clk-ext_rx_clk+ext_tx_data <8ns. At this time, the calculation formula of the PCIE common clock delay on the PCB is as follows: transmission delay = ext_tx_clk-ext_rx_clk+ext_tx_data. In addition, regarding the internal delay of the chip and the design delay of the tightening, the internal delay of the chip and the design delay of the tightening can be modified according to actual demands, and the internal delay of the chip and the design delay of the tightening can be specifically manually input by technicians, and the internal delay of the chip and the design delay of the tightening can be calculated and evaluated by default of 8ns without input.
S105: and when the transmission delay does not exceed the standard, outputting a detection passing prompt.
The step aims at realizing transmission delay detection, and obviously, when the transmission delay does not exceed the standard delay, the PCIE common clock delay of the PCB to be detected is indicated to be in the standard range, and the detection is passed; and when the transmission delay exceeds the standard time delay, the PCIE common clock delay of the PCB to be tested is not in the standard range, and the detection is not passed. Further, after the detection is finished, a corresponding prompt message is output, so that a technician is informed of the current detection result. The specific value of the standard time delay does not affect the implementation of the technical scheme, and the technical scheme is set by a technician according to actual requirements, so that the method is not limited by the method, and in addition, the setting process of the standard time delay can be directly input by the technician through a terminal interface, can be modified manually and can be preset as a default value.
As a preferred embodiment, when the number of PCBs to be tested is greater than 1, the calculating the delay of each signal by using the transmission delay formula may further include: counting the transmission time delays corresponding to all the tested PCBs; counting the intermediate transmission time delay of the connecting cables and/or connectors among the PCBs to be tested; and calculating and obtaining the total transmission delay according to the transmission delays corresponding to all the tested PCBs and the intermediate transmission delays.
It can be understood that the PCIE common clock design may need to use multiple PCBs, and each PCB is generally connected by using a connection cable and/or a connector to implement data communication, so when PCIE common clock delays based on the multiple PCBs need to be detected, transmission delays corresponding to all PCBs to be detected can be counted, intermediate transmission delays (because signals also have delays when transmitted in the connection cable and the connector) between the PCBs to be detected are counted, and then sum of the two is calculated to obtain a total transmission delay. Therefore, the total transmission time delay can be compared with the standard time delay, and a corresponding detection result is obtained.
As a preferred embodiment, the counting the intermediate transmission delay of the connection cable and/or the connector between the PCBs under test may include: acquiring identification information of each connecting cable and/or connector; and inquiring and obtaining the intermediate transmission delay of the corresponding connecting cable and/or connector from a preset database according to the identification information.
The preferred embodiment provides a method for acquiring intermediate transmission delay. Specifically, for different types and types of connection cables and connectors, the internal time delay (known in the development stage) and the identification information (such as ID information and model information) thereof can be stored in a preset database in advance, so that when calculation is performed, the identification information of each connection cable and/or connector can be extracted first, and then the corresponding intermediate transmission time delay can be obtained by inquiring from the preset database according to the identification information.
As a preferred embodiment, the delay detection method may further include: counting detection process information and detection result information; generating a topological graph according to the detection process information and the detection result information; and sending the topological graph to a display interface for visual display.
The time delay detection method provided by the preferred embodiment can realize visual display of the detection information, and in order to facilitate a technician to more intuitively know the time delay detection information, the time delay detection process information and the result information can be visually displayed in a topological diagram mode. Specifically, in the time delay detection process, the detection process information can be counted in real time; further, after the time delay detection is finished, a topological graph is constructed together by combining detection result information; and finally, sending the topological graph to a display interface for visual display.
As a preferred embodiment, the delay detection method may further include: generating a detection report according to the detection process information and the detection result information; the detection report is archived.
The time delay detection method provided by the preferred embodiment can realize the generation and archiving of the detection report, specifically, after the detection process information and the detection result information are obtained, the detection report can be imported into a preset template to generate a unified detection report, and the unified detection report is archived. The preset template is set by a technician according to actual requirements, for example, the template can be a Word template or an Excel template, and the application is not limited to this.
Therefore, according to the delay detection method provided by the application, automatic delay detection is realized by developing a delay detection program, when PCIE common clock delay of a PCB is required to be detected, corresponding signal line information and PCB lamination information are obtained, so that signal delay detection of each signal line is realized, signal delay of each signal line is further calculated according to a transmission delay formula, PCIE common clock delay is obtained, namely the transmission delay is finally compared with standard delay, and whether the PCIE common clock delay of the PCB is qualified can be determined. Obviously, the implementation mode can realize the rapid evaluation of PCIE common clock delay, greatly improve the delay detection efficiency and improve the accuracy of the detection result.
Based on the above embodiments, another delay detection method is provided in the embodiments of the present application.
According to the time delay detection method provided by the embodiment of the application, the Cadence SKILL language is adopted for development, the Cadence SKILL language is the SKILL language for providing secondary development for users by Cadence companies, the users can access through the SKILL language, and the tools based on Cadence platforms can be developed. The application relates to a time delay detection tool, which comprises two parts: PCIE common clock delay detection based on single PCB, and PCIE common clock delay detection based on multiple PCIs.
1. Inspection for single PCB system:
referring to fig. 3, fig. 3 is a front-end interface display diagram of PCIE common clock delay detection based on a single PCB according to the present application, which includes five modules in total:
module a-select signal line module:
clicking a button for selecting a signal line, inputting the signal line to be inspected according to the inspection requirement of a user, and inputting keywords for quick filtering so as to select the filtered signal line for subsequent inspection; the complete signal line name may also be entered for subsequent inspection.
Module B-rule setting module:
(1) For the delay specification, 8ns can be defaulted without input; other can also be manually input according to the need;
(2) For the laminated DK (dielectric constant) of the PCB, the numerical value automatically extracted by the PCB can be directly used without input; other can also be manually input according to the need;
(3) Clicking on "Specification output" can output the currently used inspection Specification in text form for archiving.
Module C-check module:
(1) And extracting lamination information of the PCB, obtaining names of each signal layer and each plane layer, thickness of each layer, thickness between layers, dielectric constant between layers and the like, and recording the information into a database for standby.
(2) According to a group of selected signal lines, extracting ID information of each signal line by an automatic detection program, further inquiring initial coordinates, layers, layer change hole information and the like of each signal segment, and obtaining the length of each layer of signal line through mathematical operation; for the layer-changing hole, the length of the signal line in the vertical direction can be calculated according to thickness information, signal layer information and the like in the PCB lamination, and finally, the total length of the signal line is calculated through addition. In addition, considering that PCIE data may have multiple pairs, the longest TX & RX signal (longest signal line) may be selected for subsequent computation (so that when the longest signal line meets the requirements, other signal lines also necessarily meet the requirements). Further, PCIE data and Clock signals are converted from signal line length to delay: time = length/speed = c/sqrt (er), c is the speed of light, and er is the dielectric constant of the medium. On this basis, the transmission delay is obtained according to the transmission delay=ext_tx_clk-ext_rx_clk+ext_tx_data, and then compared with a rule (standard delay), if the transmission delay is greater than or equal to the rule, the label is "Fail", and if the transmission delay is less than the rule, the label is "Pass".
In addition, for various Clock schemes, as shown in fig. 4, fig. 4 is a Clock topology diagram of the various Clock schemes provided by the present application, there are two schemes from CLK1 to PCIe expansion chip, and the two schemes can be output from Clock pin 2 of the Clock source or output from Clock pin 0 of the Clock source through a Clock buffer, and the implementation mode is realized by connecting resistors in series and sharing a pad. Then, in calculating CLK delay, CLK1 to the PCIe expansion chip needs to calculate two paths, one from pin (pin) clock pin 2 to the PCIe expansion chip and the other from pin clock pin 0 to the clock buffer to the PCIe expansion chip. The delay information of the clock buffer can be obtained by extracting the part information of the clock buffer and searching the part information of the clock buffer in the database (the delay of the clock buffer is stored in the database for standby). For the two schemes, after Clock delay is calculated, the corresponding PCIE data delay is calculated, and finally the final delay is calculated through the formula (transmission delay = ext_Tx_clk-ext_Rx_clk + ext_Tx_data), and is compared with the specification, and the two schemes can be sequenced to give the optimal scheme in the current calculation result.
Module D-result display module:
after inspection, the inspection result can be displayed in an 'result display unit', and the topological graph is displayed, so that the inspection is convenient.
Module E-report generation module:
after passing through the inspection module, the "report generation" can be clicked to store PCIE data, clock information, inspection results, and the like into the document, and specifically, the inspection results can be imported into a unified edited Excel template to be output as a unified analysis report.
2. Checking for multi-PCB systems:
referring to fig. 5, fig. 5 is a front-end interface display diagram of PCIE common clock delay detection based on multiple PCBs according to the present application, where a module a-information importing module is different from a module a-selection signal line module in fig. 4:
(1) The information of each PCB is imported, namely the information of each PCB is imported, and a single PCB inspection tool is referred;
(2) The "Cable/Connector information import" is the delay of importing Cable/Connector information, which is available from the provider (of course, cable/Connector information may also be stored in the database in advance, and the database may be updated continuously).
Other module functions are similar to a single PCB.
In specific implementation, according to the importing of each PCB information, the Cable/Connector information is imported, a check button is clicked, a detection program automatically sums up the final PCIe common clock delay, then the final PCIe common clock delay is compared with a standard, if the final PCIe common clock delay is larger than or equal to the standard, the final common clock delay is marked, and if the final common clock delay is smaller than the standard, the final common clock delay is marked by the final common clock delay. Furthermore, the checking result can be displayed in a result display unit, and the topological graph is displayed, so that the checking is convenient; the report generation can be clicked to store PCIE data, clock information and inspection results into the document, and the report can be imported into a unified and edited Excel template to be output as a unified analysis report. It is conceivable that in the inspection module, the delays in the respective PCB information and Cable/Connector information need to be summed as a final result and then compared with the specification.
Therefore, according to the delay detection method provided by the embodiment of the application, automatic delay detection is realized by developing a delay detection program, when PCIE common clock delay of a PCB is required to be detected, corresponding signal line information and PCB lamination information are obtained, so that signal delay detection of each signal line is realized, signal delay of each signal line is further calculated according to a transmission delay formula, PCIE common clock delay is obtained, namely the transmission delay is finally compared with standard delay, and whether the PCIE common clock delay of the PCB is qualified can be determined. Obviously, the implementation mode can realize the rapid evaluation of PCIE common clock delay, greatly improve the delay detection efficiency and improve the accuracy of the detection result.
In order to solve the above technical problems, the present application further provides a delay detection device, please refer to fig. 6, fig. 6 is a schematic structural diagram of the delay detection device provided by the present application, the delay detection device may include:
an information acquisition module 1 for acquiring signal line information and PCB lamination information;
a length calculation module 2 for calculating the length of the signal line according to the signal line information and the PCB lamination information;
the signal delay calculation module 3 is used for calculating and obtaining signal delay according to the length of the signal line and the signal propagation speed;
the transmission delay calculation module 4 is configured to calculate the delay of each signal by using a transmission delay formula, so as to obtain a transmission delay;
and the detection result output module 5 is used for delaying when the transmission delay does not exceed the standard and outputting a detection passing prompt.
Therefore, according to the delay detection device provided by the embodiment of the application, automatic delay detection is realized by developing a delay detection program, when PCIE common clock delay of a PCB is required to be detected, corresponding signal line information and PCB lamination information are obtained, so that signal delay detection of each signal line is realized, signal delay of each signal line is further calculated according to a transmission delay formula, PCIE common clock delay is obtained, namely the transmission delay is finally compared with standard delay, and whether the PCIE common clock delay of the PCB is qualified can be determined. Obviously, the implementation mode can realize the rapid evaluation of PCIE common clock delay, greatly improve the delay detection efficiency and improve the accuracy of the detection result.
As a preferred embodiment, the length calculating module 2 may be specifically configured to determine coordinate information of each horizontal signal line segment in the corresponding signal line on the corresponding PCB layer according to the signal line information; calculating and obtaining the horizontal total length of all horizontal signal line segments in the signal line according to the coordinate information; calculating and obtaining the vertical total length of all vertical signal fragments in the signal line according to the PCB lamination information; the signal line length is calculated from the horizontal total length and the vertical total length.
As a preferred embodiment, the delay detection device may further include a speed calculation module, configured to determine a dielectric constant of each PCB layer according to PCB stack information before calculating the signal delay according to the signal line length and the signal propagation speed; and calculating according to the light speed and each dielectric constant to obtain the signal propagation speed on the corresponding signal line segment.
As a preferred embodiment, the delay detection device may further include a total delay calculation module, configured to calculate, when the number of PCBs to be tested is greater than 1, the delays of the signals by using the transmission delay formula, and calculate the transmission delays corresponding to all PCBs to be tested after obtaining the transmission delays; counting the intermediate transmission time delay of the connecting cables and/or connectors among the PCBs to be tested; and calculating and obtaining the total transmission delay according to the transmission delays corresponding to all the tested PCBs and the intermediate transmission delays.
As a preferred embodiment, the total delay calculation module may be specifically configured to obtain identification information of each connection cable and/or connector; and inquiring and obtaining the intermediate transmission delay of the corresponding connecting cable and/or connector from a preset database according to the identification information.
As a preferred embodiment, the delay detection device may further include a visual display module, configured to count detection process information and detection result information; generating a topological graph according to the detection process information and the detection result information; and sending the topological graph to a display interface for visual display.
As a preferred embodiment, the delay detection device may further include a report archiving module, configured to generate a detection report according to the detection process information and the detection result information; the detection report is archived.
For the description of the device provided by the present application, please refer to the above method embodiment, and the description of the present application is omitted herein.
In order to solve the above technical problems, the present application further provides a delay detection device, please refer to fig. 7, fig. 7 is a schematic structural diagram of the delay detection device provided by the present application, and the delay detection device may include:
a memory 10 for storing a computer program;
the processor 20 is configured to execute the computer program to implement the steps of any of the delay detection methods described above.
For the description of the system provided by the present application, please refer to the above method embodiment, and the description of the present application is omitted here.
In order to solve the above-mentioned problems, the present application also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, can implement the steps of any of the above-mentioned delay detection methods.
The computer readable storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
For the description of the computer-readable storage medium provided by the present application, refer to the above method embodiments, and the disclosure is not repeated here.
In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The technical scheme provided by the application is described in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that the present application may be modified and practiced without departing from the spirit of the present application.
Claims (7)
1. A method for latency detection, comprising:
acquiring signal line information and PCB lamination information;
calculating to obtain the length of the signal wire according to the signal wire information and the PCB lamination information;
calculating according to the length of the signal line and the signal propagation speed to obtain signal time delay;
calculating the time delay of each signal by using a transmission time delay formula to obtain the transmission time delay;
when the transmission delay does not exceed the standard, delaying, and outputting a detection passing prompt;
counting detection process information and detection result information;
generating a topological graph according to the detection process information and the detection result information;
sending the topological graph to a display interface for visual display;
when the number of the PCBs to be tested is greater than 1, the calculating the signal delays by using the transmission delay formula, after obtaining the transmission delays, further includes:
counting the transmission time delays corresponding to all the tested PCBs;
counting the intermediate transmission time delay of the connecting cables and/or connectors among the tested PCBs;
calculating to obtain total transmission delay according to the transmission delay corresponding to all the tested PCBs and each intermediate transmission delay;
the counting of the intermediate transmission delay of the connecting cable and/or the connector between the tested PCBs comprises the following steps:
acquiring identification information of each connecting cable and/or each connector;
inquiring and obtaining intermediate transmission delay of a corresponding connecting cable and/or connector from a preset database according to the identification information;
the transmission delay formula is as follows:
Transport Delay Delta ＝ Total Data Transport Delay - Total Sampling Transport Delay；
Total Data Transport Delay ＝ Ext_Tx_clk+Int_Tx_clk_data + Ext_Tx_data+Int_Rx_data；
Total Sampling Transport Delay ＝ Ext_Rx_clk + Int_Rx_clk；
wherein Transport Delay Delta is the transmission delay; the Total Data Transport Delay is the total delay of data transmission; the Total Sampling Transport Delay is the total delay of sampling transmission; the Ext_Tx_clk is the transmission delay of the CPU input clock; the Int_Tx_clk_data is the internal clock data transmission delay of the CPU; the Ext_Tx_data is the data transmission delay between the CPU and the PCIe device; the Int_Rx_data is the internal data transmission delay of PCIE equipment; the Ext_Rx_clk is PCIE equipment input clock transmission delay; the Int_Rx_clk is the internal clock transmission delay of the PCIe equipment.
2. The method of claim 1, wherein calculating a signal line length from the signal line information and the PCB stack information comprises:
determining coordinate information of each horizontal signal line segment in the corresponding signal line on the corresponding PCB layer according to the signal line information;
calculating and obtaining the horizontal total length of all horizontal signal line segments in the signal line according to the coordinate information;
calculating and obtaining the vertical total length of all vertical signal segments in the signal line according to the PCB lamination information;
and calculating according to the horizontal total length and the vertical total length to obtain the signal line length.
3. The method of claim 2, wherein before the calculating the signal delay according to the signal line length and the signal propagation speed, further comprises:
determining the dielectric constants of all PCB layers according to the PCB lamination information;
and calculating according to the light speed and each dielectric constant to obtain the signal propagation speed on the corresponding signal line segment.
4. The method of latency detection of claim 1, further comprising:
generating a detection report according to the detection process information and the detection result information;
archiving the detection report.
5. A time delay detection apparatus, comprising:
the information acquisition module is used for acquiring signal line information and PCB lamination information;
the length calculation module is used for calculating and obtaining the length of the signal wire according to the signal wire information and the PCB lamination information;
the signal delay calculation module is used for calculating and obtaining signal delay according to the length of the signal line and the signal propagation speed;
the transmission delay calculation module is used for calculating the signal delay by utilizing a transmission delay formula to obtain the transmission delay;
the detection result output module is used for delaying when the transmission delay does not exceed the standard, and outputting a detection passing prompt;
the visualization module is used for counting detection process information and detection result information; generating a topological graph according to the detection process information and the detection result information; sending the topological graph to a display interface for visual display;
the total time delay calculation module is used for calculating the time delay of each signal by using a transmission time delay formula when the number of the tested PCBs is larger than 1, and counting the transmission time delays corresponding to all the tested PCBs after the transmission time delay is obtained; counting the intermediate transmission time delay of the connecting cables and/or connectors among the tested PCBs; calculating to obtain total transmission delay according to the transmission delay corresponding to all the tested PCBs and each intermediate transmission delay;
the total time delay calculation module is specifically configured to obtain identification information of each connection cable and/or each connector; inquiring and obtaining intermediate transmission delay of a corresponding connecting cable and/or connector from a preset database according to the identification information;
the transmission delay formula is as follows:
Transport Delay Delta ＝ Total Data Transport Delay - Total Sampling Transport Delay；
Total Data Transport Delay ＝ Ext_Tx_clk+Int_Tx_clk_data + Ext_Tx_data+Int_Rx_data；
Total Sampling Transport Delay ＝ Ext_Rx_clk + Int_Rx_clk；
wherein Transport Delay Delta is the transmission delay; the Total Data Transport Delay is the total delay of data transmission; the Total Sampling Transport Delay is the total delay of sampling transmission; the Ext_Tx_clk is the transmission delay of the CPU input clock; the Int_Tx_clk_data is the internal clock data transmission delay of the CPU; the Ext_Tx_data is the data transmission delay between the CPU and the PCIe device; the Int_Rx_data is the internal data transmission delay of PCIE equipment; the Ext_Rx_clk is PCIE equipment input clock transmission delay; the Int_Rx_clk is the internal clock transmission delay of the PCIe equipment.
6. A time delay detection apparatus, comprising:
a memory for storing a computer program;
processor for implementing the steps of the delay detection method according to any one of claims 1 to 4 when executing said computer program.
7. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the delay detection method according to any of claims 1 to 4.
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