CN108809299A - signal frequency measuring system - Google Patents
signal frequency measuring system Download PDFInfo
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- CN108809299A CN108809299A CN201811005837.XA CN201811005837A CN108809299A CN 108809299 A CN108809299 A CN 108809299A CN 201811005837 A CN201811005837 A CN 201811005837A CN 108809299 A CN108809299 A CN 108809299A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
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Abstract
The present invention provides a kind of signal frequency measuring system, including microcontroller, the first timer that is connect respectively with microcontroller and second timer and internal clock source；Internal clock source is connect with second timer, and clock signal is provided for second timer；The first default heavily loaded value is equipped in first timer；Duration when being equipped with pre-designed in second timer；Measured signal is input to first timer and second timer；First timer starts counting up under the default hopping edge pulse-triggered of measured signal, and count value updates whenever detecting default hopping edge pulse；Second timer starts timing under the pulse-triggered of default hopping edge, whenever timing is updated to pre-designed constantly chronistor numerical value；Microcontroller reads the count value of second timer when the count value of first timer reaches the first default heavily loaded value, to determine the frequency of measured signal according to the count value of the first default heavily loaded value and second timer, realizes the efficient measurement of measured signal frequency.
Description
Technical field
The present invention relates to signal measurement technique field more particularly to a kind of signal frequency measuring systems.
Background technology
Frequency has the demand of measuring signal frequency as a kind of most basic physical quantity in many engineer applications, than
Such as, by measuring the frequency of certain signal, on the basis of learning the frequency of the signal, by carrying out certain control to the signal
Processing is to export the drive signal for driving certain equipment.
In order to realize that the measurement of signal frequency, usual way are to measure measured signal using the timer in microcontroller
Period, then converse the frequency of measured signal.It is understood that for a cycle signal, it is with rising edge
, the time span between adjacent rising edges is a cycle.Therefore, if timer is after rising edge reaches triggering, energy
Next rising edge is enough recognized accurately, and timing obtains the time span for reaching next rising edge, you can to obtain one
The time span in period, inverted is frequency.
Based on this, when using period of the timer to measure measured signal, first configuration timer is generally required
Counting time period, i.e., every how long counting primary, such as 1ms.To, it is assumed that timer is triggered when being reached with rising edge
It starts counting up, counts are updated to 1 after timing 1ms, and after every count once, the microcontroller needs in microcontroller are held
Row interrupt handling logic is mainly to judge whether that edge transition has occurred in the interrupt handling logic, and and so on, directly
It is counted to certain moment after adding one, determines the rising edge for detecting measured signal again, then think to have reached one at this time
In a period, the total degree of counting, which is multiplied by counting time period, at this time can obtain the time span in the period.
It follows that needing to execute an interrupt handling logic after every count once, this will occupy microcontroller
Excessive process resource, especially in the case where the frequency of measured signal is very high, because in order to ensure the frequency even if measured signal
Rate is very high also can accurately to measure its frequency, and the counting time period of setting is often smaller, this results in needing more frequent
Ground executes interrupt handling logic, this can not only reduce the efficiency of frequency measurement, can also occupy the processing money of more microcontrollers
Source makes the reduction of its working efficiency, and can influence its service life to influence the normal operation of microcontroller.
Invention content
In view of this, the present invention provides a kind of signal frequency measuring system, and to improve the measurement efficiency of signal frequency, drop
Low-signal frequencies measure the excessive occupancy to microcontroller process resource.
The embodiment of the present invention provides a kind of signal frequency measuring system, including：
Microcontroller, the first timer and second timer and internal clocking being connect respectively with the microcontroller
Source；
The internal clock source is connect with the second timer, to provide clock signal for the second timer；Institute
It states and is equipped with the first default heavily loaded value in first timer；Duration when being equipped with pre-designed in the second timer；
Measured signal inputs the first timer and the second timer；
The first timer, for being started counting up under the default hopping edge pulse-triggered of the measured signal, whenever
Count value updates when detecting the default hopping edge pulse；
The second timer, for starting timing under the default hopping edge pulse-triggered, whenever timing is described in
Pre-designed constantly chronistor numerical value update；
The microcontroller, for when the count value of the first timer reaches the described first default heavily loaded value, reading
The count value for taking the second timer, to be determined according to the count value of the described first default heavy duty value and the second timer
The frequency of the measured signal.
Signal frequency measuring system provided by the invention, the system include microcontroller, connect respectively with microcontroller
First timer and second timer and internal clock source.Internal clock source is connect with second timer, is second timer
Clock signal is provided, the first default heavily loaded value is equipped in first timer, when being equipped with pre-designed in second timer
Duration, measured signal are input to first timer and second timer.First timer measured signal default saltus step along the pulse
It is started counting up under punching triggering, count value updates whenever detecting default hopping edge pulse, until counting down to the first default heavy duty
Value.Second timer starts timing under the pulse-triggered of default hopping edge, whenever timing to pre-designed constantly chronistor numerical value more
Newly.Based on this, microcontroller reads the meter of second timer when the count value of first timer reaches the first default heavily loaded value
Numerical value, to determine the frequency of measured signal according to the count value of the first default heavily loaded value and second timer.
By this programme, first timer starts counting up under the default hopping edge pulse-triggered of measured signal, Mei Dangjian
Count value updates when measuring default hopping edge pulse, and default jump need to be detected until counting down to the first default heavily loaded value, during this
Become along and counted, without carrying out the processing of interrupt logic.Second timer starts to count under the pulse-triggered of default hopping edge
When, whenever timing is updated to pre-designed constantly chronistor numerical value, the when first timer count down to the first default heavily loaded value
Two timers stop counting, and are during which not necessarily to carry out the processing of interrupt logic.So in this way, reducing signal frequency survey
The number of processes of interrupt logic during amount, to improve the treatment effeciency of signal frequency measurement.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Some bright embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is a kind of structural schematic diagram of signal frequency measuring system provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another signal frequency measuring system provided in an embodiment of the present invention；
Fig. 3 is the waveform diagram provided in an embodiment of the present invention for carrying out scaling down processing to measured signal；
Fig. 4 is the structural schematic diagram of another signal frequency measuring system provided in an embodiment of the present invention.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
The every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
The term used in embodiments of the present invention is the purpose only merely for description specific embodiment, is not intended to be limiting
The present invention.In the embodiment of the present invention and "an" of singulative used in the attached claims, " described " and "the"
It is also intended to including most forms, unless context clearly shows that other meanings, " a variety of " generally comprise at least two.
It should be appreciated that term "and/or" used herein is only a kind of incidence relation of description affiliated partner, indicate
There may be three kinds of relationships, for example, A and/or B, can indicate：Individualism A, exists simultaneously A and B, individualism B these three
Situation.In addition, character "/" herein, it is a kind of relationship of "or" to typically represent forward-backward correlation object.
Depending on context, word as used in this " if ", " if " can be construed to " ... when " or
" when ... " or " in response to determination " or " in response to detection ".Similarly, context is depended on, phrase " if it is determined that " or " such as
Fruit detect (condition or event of statement) " can be construed to " when determining " or " in response to determination " or " when detection (statement
Condition or event) when " or " in response to detection (condition or event of statement) ".
It should also be noted that, the terms "include", "comprise" or its any other variant are intended to nonexcludability
Including so that commodity or system including a series of elements include not only those elements, but also include not clear
The other element listed, or further include for this commodity or the intrinsic element of system.In the feelings not limited more
Under condition, the element that is limited by sentence "including a ...", it is not excluded that including the element commodity or system in also
There are other identical elements.
Further it is worth noting that, the sequence in various embodiments of the present invention between each step is adjustable, and is not
It must be executed according to the sequence of following citing.
Fig. 1 is a kind of structural schematic diagram of signal frequency measuring system provided in an embodiment of the present invention, as shown in Figure 1, should
Signal frequency measuring system includes：Microcontroller 11, first timer 12, second timer 13, internal clock source 14.
Microcontroller 11, the first timer 12 and second timer 13 being connect respectively with microcontroller 11, and it is internal
Clock source 14.
Wherein, internal clock source 14 is connect with second timer 13, to provide clock signal for second timer 13.
Wherein, the first default heavily loaded value is equipped in first timer 12；It is equipped in second timer 13 default
Timing duration.
Measured signal inputs first timer 12 and second timer 13.
First timer 12, for being started counting up under the default hopping edge pulse-triggered of measured signal, whenever detecting
Count value updates when default hopping edge pulse.
Second timer 13, for starting timing under the pulse-triggered of default hopping edge, whenever timing to it is pre-designed constantly
Chronistor numerical value updates.
Microcontroller 11, for when the count value of first timer 12 reaches the first default heavily loaded value, it is fixed to read second
When device 13 count value, to determine the frequency of measured signal according to the count value of the first default heavily loaded value and second timer 13.
In the present embodiment, first timer 12 is equipped with the first default heavily loaded value, and is touched measured signal as it
It rises and clock source, is started counting up under the default hopping edge pulse-triggered of measured signal, whenever detecting default saltus step along the pulse
Count value updates when rushing, and when counting down to the first default heavily loaded value, can send down trigger letter to microcontroller 11 at this time
Number, to inform that 11 current first timer 12 of microcontroller has been counted by the first default heavily loaded value.
May include register corresponding with first timer 12 in practical application, in the signal frequency measuring system, from
And the above-mentioned first default heavily loaded value can be previously written in the register and be worth to the first timing with completing the first default heavy duty
The setting of device 12.
Duration when second timer 13 is equipped with pre-designed, and using measured signal as trigger source, internal clocking conduct
Clock source starts timing under the default hopping edge pulse-triggered of measured signal, in the control of the clock pulses of internal clocking output
Duration when the lower timing of system is pre-designed, whenever timing is updated to pre-designed constantly chronistor numerical value.In practical application, the signal frequency
May include register corresponding with second timer 13 in measuring system, so as to will be above-mentioned pre-designed when duration write in advance
Enter in the register with complete this it is pre-designed when setting of the duration to second timer 13.
Microcontroller 11 reads second timer T2 when the count value of first timer T1 reaches the first default heavily loaded value
Count value, to determine the frequency of measured signal according to the count value of the first default heavily loaded value and second timer T2.This implementation
In example, microcontroller 11 resets the count value of second timer 13 after the count value for reading second timer 13, so that
Second timer 13 restarts timing, counts.
System is tested based on signal frequency provided in this embodiment, measured signal is input in first timer 12, above
It is first rising edge pulse triggering of the first timer 12 in measured signal for rising edge pulse to state default hopping edge pulse
Under start counting up, count value updates whenever detecting a rising edge pulse, until count down to the first default heavily loaded value (assuming that
For N), when counting down to the first default heavy duty value N, first timer 12 can restart timing.
So the default heavily loaded practical number of cycles being had been subjected to for measured signal of value N of the first of first timer 12.?
That is first timer 12 is the equal of being started counting up under the triggering of first rising edge pulse of measured signal, counting waits for
The number of cycles N that signal has been subjected to is surveyed, N number of period is to correspond to the N number of rising edge pulse continuously received.
Second timer 13 starts timing under the rising edge pulse triggering of measured signal, it is assumed that pre-designed constantly a length of
1us, then count value adds one when timing is to 1us, until microcontroller 11 has been counted by N in discovery first timer 12
When, control second timer 13 is reset, and restarts timing.
It follows that second timer 13 is the equal of being started counting up from first timer 12 for timing, until meter
Count to the time span undergone when N, that is, the time span corresponding to N number of period of measured signal.When experience of N number of period
When time span determines, the measured signal corresponding frequency within N number of period can be calculated.
Calculation formula is as follows：The default heavy duty value of frequency=the first of measured signal/(the count value * of second timer T2 is pre-
Duration when design).
In practical application, small vibration may occur for the frequency of measured signal, therefore, when first timer 12
It count down to after the first default heavy duty value N counted N number of period, measured signal remains unchanged input, at this time can be according to front
The process of introduction continues the measurement for carrying out the frequency in N number of period next time to measured signal.
It is worth noting that by the timing effect of above-mentioned first timer 12 and second timer 13 it is found that first is fixed
When device 12 be mainly used for counting the number of cycles of measured signal having been subjected to, in practical application, the value of N can rationally be set
It is fixed, generally will not be too high, therefore, the requirement to the count range of first timer 12 is little, and therefore, 16 timers are general
It can meet demand.But in order to meet the accurate measurement to the frequency of the measured signal of different frequency, the frequency of internal clock source
Rate is often relatively high, and the requirement to the count range of second timer 13 can be relatively high, and therefore, second timer 13 generally may be used
To select 32 timers.
Further optionally, signal frequency measuring system provided in an embodiment of the present invention can be based on the monolithic of STM32 series
Machine is realized.
To sum up, by this programme, within N number of period, first timer 12 and second timer 13 not will produce interruption,
Hopping edge detection need not be continually carried out, interrupt logic processing need not be continually carried out, to improve signal frequency
The treatment effeciency of measurement.
Fig. 2 is the structural schematic diagram of another signal frequency measuring system provided in an embodiment of the present invention, as shown in Fig. 2,
On the basis of embodiment shown in Fig. 1, which can also include：
Third timer 15 is equipped with the second default heavily loaded value in this third timer 15.
May include register corresponding with third timer 15 in practical application, in the signal frequency measuring system, from
And the above-mentioned second default heavily loaded value can be previously written in the register and be worth to third timing with completing the second default heavy duty
The setting of device 15.
Wherein, one end of third timer 15 is connect with measured signal, and the other end of third timer 15 is respectively with first
Timer 12 and second timer 13 connect.
Third timer 15, for being started counting up under the default hopping edge pulse-triggered of measured signal, whenever detecting
Count value updates when default hopping edge pulse, when count value update is to the second default heavy duty value respectively to 12 He of first timer
Second timer 13 export the first pulse signal so that first timer 12 started counting up under the triggering of the first pulse signal with
And so that second timer 13 starts timing under the triggering of the first pulse signal.
Third timer 15 is additionally operable to restart to count after count value update to the second default heavily loaded value, again
When counting down to the second default heavily loaded value, the second pulse signal, the second pulse signal and the first pulse are exported to first timer 12
Signal level attribute is opposite.
In the present embodiment, third timer 15 provides division function, and the above-mentioned second default heavy duty value is frequency dividing times
Number.In practical application, in the case where third timer 15 is started counting up from 0, actual distribution multiple is the second default weight
Load value+1, description below is by for 0 starts counting up.
In the present embodiment, why be arranged provide frequency dividing effect third timer 15, be because practical application in, it is to be measured
The frequency of signal may be very high, if the frequency of measured signal is higher than the frequency of internal clock source, it is likely that lead to frequency
Rate measurement result is inaccurate, can will enter into first timer 12 by the division function of third timer 15 based on this
The frequency of signal reduces.
In practical application, optionally, signal frequency measuring system provided in this embodiment can be based on STM32 series monolithics
Machine is realized, at this point, the third timer 15 can be the timer for providing division function in the microcontroller.
The frequency dividing course of work of third timer 15 for ease of understanding provides frequency dividing work(in conjunction with Fig. 3 to third timer 15
The basic principle of energy is briefly described：
Assuming that the second default heavy duty value is 1, then it is 1+1=2 to divide multiple, and, it is assumed that triggering third timer 15 is opened
The default hopping edge pulse counted begin as rising edge pulse.Based on this, when third timer 15 receives measured signal for the first time
Triggering starts to be counted from 0 in rising edge pulse, and count value is 0 at this time.Later, on third timer 15 receives again
When rising along pulse, more new count value is 1, at this point, count value has reached the second default heavily loaded value 1, then at this point, third timer 15
The first pulse signal, such as rising edge pulse signal can be exported simultaneously to first timer 12 and second timer 13, this
Trigger signal of one pulse signal as first timer 12 and the flip-flop number simultaneously of second timer 13.
Based on the triggering of first pulse signal, first timer 12 starts counting up, for example, first timer 12 be also from
Initial value starts counting up for 0, then the count value of first timer 12 is initial value 0 at this time.Touching based on first pulse signal
Hair, second timer 13 are started to work, that is, the counting of duration such as 1us when starting pre-designed, and when each timing reaches 1us
Count value adds one.
After third timer 15 count down to the second default heavily loaded value, count value is updated to initial value 0, then restarts to count
Number, i.e., when receiving third rising edge pulse, count value is updated to 1, is preset at this point, count value has reached again second
Heavily loaded value 1, at this point, third timer 15 can export the second pulse signal, such as failing edge pulse signal.
Since in the example above, it is to rise along the pulse that first timer 12, which carries out the newer effective hopping edge pulse of count value,
Signal is rushed, therefore, the failing edge pulse signal that third timer 15 exports at this time can't cause the counting of first timer 12
The update of value.
The output of above-mentioned failing edge pulse signal is on the one hand to realize 2 frequency dividing purposes to measured signal, another party
Face, the clock source due to third timer 15 as first timer 12, if third timer 15 is in first time, output rises
Just stop exporting electric signal to first timer 12 after pulse signal, then first timer 12 will be unable to work, be based on this, such as
Shown in Fig. 3, third timer 15 keeps the output of corresponding high level signal after first time exports rising edge pulse signal, directly
Failing edge pulse signal is exported to after counting down to the second default heavily loaded value again, hereafter keeps the output of low level signal, until
It count down to the second default heavily loaded value again again, exports rising edge pulse signal, the rising edge pulse signal meeting again at this time
Cause the count value of first timer 12 to add a update, so repeats down.
To sum up, after introducing third timer 15, the output of third timer 15 is by the triggering as first timer 12
Source (triggering starts counting up) and clock source, and the trigger source as second timer 13.
The process that first timer 12 and second timer 13 are triggered after starting counting up, can be with real shown in reference chart 1
The description in example is applied, is repeated no more.
Based on the premise that above-mentioned count value is started counting up from 0, optionally, microcontroller 11 can be according to following formula meter
Calculate the frequency of measured signal：Measured signal frequency=(the first default heavily loaded value * (the second default heavy duty value+1))/(second is fixed
When device T2 count value * it is pre-designed when duration).
Fig. 4 is the structural schematic diagram of another signal frequency measuring system provided in an embodiment of the present invention.As shown in figure 4,
On the basis of embodiment shown in Fig. 1, which can also include：
Frequency divider 16, wherein frequency divider 16 is equipped with preset division multiple.
Wherein, one end of frequency divider 16 is connect with measured signal, the other end of frequency divider 16 respectively with first timer 12
It is connected with second timer 13.
Frequency divider 16, the scaling down processing for carrying out preset division multiple to measured signal, by the measured signal after frequency dividing
It exports to first timer 12 and second timer 13.
It is similar with the division function that third timer 15 is provided in Fig. 2, in the present embodiment, traditional frequency dividing can be passed through
Device 16 realizes frequency dividing to measured signal.
Be the equal of being carried out to measured signal first with frequency divider in the present embodiment unlike embodiment illustrated in fig. 2
Frequency dividing, the signal after being divided later export the signal after frequency dividing than the oscillogram after 2 frequency dividing as shown in Figure 3
To first timer 12 and second timer 13, at this point, compared to the scheme of embodiment illustrated in fig. 2, due to first to completely waiting for
It surveys signal and carries out scaling down processing, will take some time, therefore, be input to point of first timer 12 and second timer 13
Signal after frequency postpones with the regular hour.
In the present embodiment, the signal after frequency dividing can be considered as the measured signal in embodiment illustrated in fig. 1, to this point
Trigger source and clock source of the signal as first timer 12 after frequency, as the trigger source of second timer 13, after frequency dividing
First default hopping edge pulse ratio such as rising edge pulse in signal triggers first timer 12 and second timer 13 simultaneously
It starts counting up.
Details are not described herein for the course of work of first timer 12 and second timer 13.
In the present embodiment, microcontroller can calculate the frequency of measured signal according to following formula：
Measured signal frequency=(the first default heavily loaded value * preset divisions multiple)/(the count value * of second timer is default
Timing duration).
The apparatus embodiments described above are merely exemplary, wherein the unit illustrated as separating component can
It is physically separated with being or may not be, the component shown as unit may or may not be physics list
Member, you can be located at a place, or may be distributed over multiple network units.It can be selected according to the actual needs
In some or all of module achieve the purpose of the solution of this embodiment.Those of ordinary skill in the art are not paying creativeness
Labour in the case of, you can to understand and implement.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, it will be understood by those of ordinary skill in the art that：It still may be used
With technical scheme described in the above embodiments is modified or equivalent replacement of some of the technical features；
And these modifications or replacements, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (8)
1. a kind of signal frequency measuring system, which is characterized in that including：
Microcontroller, the first timer and second timer and internal clock source being connect respectively with the microcontroller；
The internal clock source is connect with the second timer, to provide clock signal for the second timer；Described
The first default heavily loaded value is equipped in one timer；Duration when being equipped with pre-designed in the second timer；
Measured signal inputs the first timer and the second timer；
The first timer, for being started counting up under the default hopping edge pulse-triggered of the measured signal, whenever detection
It is updated to count value when the default hopping edge pulse；
The second timer, for starting timing under the default hopping edge pulse-triggered, whenever timing is preset to described
Count value updates when timing duration；
The microcontroller, for when the count value of the first timer reaches the described first default heavily loaded value, reading institute
The count value for stating second timer, described in being determined according to the count value of the described first default heavy duty value and the second timer
The frequency of measured signal.
2. system according to claim 1, which is characterized in that the microcontroller is additionally operable to reading second timing
After the count value of device, the count value of the second timer is reset.
3. system according to claim 1, which is characterized in that the microcontroller, for determining the measured signal
Frequency is：Described first default heavy duty value/(duration when pre-designed described in the count value * of the second timer).
4. system according to claim 1, which is characterized in that further include：Third timer；
The second default heavily loaded value is equipped in the third timer；
One end of the third timer is connect with the measured signal, and the other end of the third timer is respectively with described
One timer is connected with the second timer；
The third timer, for being started counting up under the default hopping edge pulse-triggered of the measured signal, whenever detection
It is updated to count value when the default hopping edge pulse, when count value update is to the described second default heavy duty value respectively to described
First timer and the second timer export the first pulse signal, so that the first timer is believed in first pulse
Number triggering under start counting up and so that the second timer starts timing under the triggering of first pulse signal.
5. system according to claim 4, which is characterized in that the third timer is additionally operable to arrive in count value update
Restart to count after described second default heavily loaded value, when counting down to the described second default heavily loaded value again, to described first
Timer exports the second pulse signal, and second pulse signal is opposite with the first pulse signal level attribute.
6. system according to claim 4, which is characterized in that the microcontroller is additionally operable to determine the measured signal
Frequency be：(the described first default heavily loaded value * (the described second default heavy duty value+1))/(count value * of the second timer
Duration when described pre-designed).
7. system according to claim 1, which is characterized in that further include：Frequency divider；
The frequency divider is equipped with preset division multiple；
One end of the frequency divider is connect with the measured signal, the other end of the frequency divider respectively with the first timer
It is connected with the second timer；
The frequency divider, the scaling down processing for carrying out the preset division multiple to the measured signal, by waiting for after frequency dividing
Signal is surveyed to export to the first timer and the second timer.
8. system according to claim 7, which is characterized in that the microcontroller is additionally operable to determine the measured signal
Frequency be：(preset division multiple described in the described first default heavily loaded value *)/it is (pre- described in the count value * of the second timer
Duration when design).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110794573A (en) * | 2019-10-21 | 2020-02-14 | 歌尔股份有限公司 | MEMS galvanometer feedback signal acquisition method, driving method and system |
| CN113075720A (en) * | 2021-03-24 | 2021-07-06 | 福州智元仪器设备有限公司 | Alpha and beta ray discrimination system and method based on combined timer |
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| 赵浩 等: "基于 PSoC 芯片的两路高精度频率测量系统设计", 《电子设计工程》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110794573A (en) * | 2019-10-21 | 2020-02-14 | 歌尔股份有限公司 | MEMS galvanometer feedback signal acquisition method, driving method and system |
| CN113075720A (en) * | 2021-03-24 | 2021-07-06 | 福州智元仪器设备有限公司 | Alpha and beta ray discrimination system and method based on combined timer |
| CN113075720B (en) * | 2021-03-24 | 2024-05-31 | 福州智元仪器设备有限公司 | Alpha and beta ray discrimination system and method based on combined timer |
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| CN108809299B (en) | 2022-07-08 |
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