CN204539101U - Clock control device - Google Patents
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- CN204539101U CN204539101U CN201520304898.1U CN201520304898U CN204539101U CN 204539101 U CN204539101 U CN 204539101U CN 201520304898 U CN201520304898 U CN 201520304898U CN 204539101 U CN204539101 U CN 204539101U
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Abstract
The utility model discloses a kind of clock control device, clock control device comprises display module, clock module, zero passage detection module and control module.In electrical control module, clock signal uses for a long time and occurs severe deviations, is calibrated and precision adjustment, obtain clock source accurately by city's signal of telecommunication to clock signal in control module.By the utility model, stable and accurate clock source can be obtained, and control module internal clock is calibrated.
Description
Technical field
The utility model relates to field of household appliances, particularly a kind of clock control device.
Background technology
Existing household electrical appliance need the function with timing or timing usually, therefore need clock signal.Based on cost consideration, the clock that household electrical appliance generally adopt the controller of household electrical appliance built-in or external crystal oscillating circuit obtain clock signal.But easily there is error in built-in clock or the clock signal of crystal oscillating circuit, and accumulates in time, and error is increasing, affects household electrical appliance and normally work.Therefore to correct clock signal, but existing correcting scheme complex structure and cost is high.
Utility model content
The utility model is intended at least to solve one of technical problem existed in prior art.For this reason, the utility model needs to provide a kind of clock control device.
For achieving the above object, execution mode of the present utility model proposes a kind of clock control device, comprising:
Clock module, for providing the first clock signal;
Zero passage detection module, for detecting civil power and obtaining zero cross signal; And
Control module, described control module respectively with described clock module and described zero passage detection model calling, described control module for the treatment of described zero cross signal with obtain civil power second clock signal and according to described second clock signal calibration the first clock signal.
In some embodiments, described clock module is crystal oscillating circuit or Tao Zhen circuit.
In some embodiments, described zero passage detection module comprises:
Photoelectrical coupler, described photoelectrical coupler comprises first input end, the second input, the first output and the second output; Described first input end is connected with the live wire of civil power, and described second input is connected with the zero line of civil power, described first output head grounding;
First resistance, described second output exports described zero cross signal by described first resistance;
Second resistance, described second resistant series is arranged between described first input end and civil power live wire;
3rd resistance, described 3rd resistance is arranged between described second output and predeterminated voltage; And
First electric capacity, described first capacitances in series is arranged between described second output and ground.
In some embodiments, described photoelectrical coupler comprises:
Light-emitting diode, the anode of described light-emitting diode is described first input end, and the negative electrode of described Light-Emitting Diode is described second input; And
Phototriode, very described first output of transmitting of described phototriode, very described second output of current collection of described phototriode.
In some embodiments, described control module comprises:
Processing unit, described processing unit comprises chip port and timer;
Clock selecting portion, described clock selecting portion is used for selective system clock;
Clock filtering portion, described clock filtering portion is used for carrying out filtering process to described zero cross signal;
Clock alignment portion, described clock alignment portion is used for calibrating described clock signal; And
Clock accuracy handling part, described clock accuracy handling part is used for regulating the precision of described clock signal.
In some embodiments, described chip port and described timer are the input/output terminal of described processing unit, are connected with described clock selecting portion, described clock filtering portion, described clock alignment portion, described clock accuracy handling part.
In some embodiments, described clock control device also includes the display module be connected with described control module, and described display module is used for read clock information.
Additional aspect of the present utility model and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present utility model.
Accompanying drawing explanation
Above-mentioned and/or additional method of the present utility model and advantage will become obvious and easy understand from accompanying drawing below combining to the description of execution mode, wherein:
Fig. 1 is the high-level schematic functional block diagram of the clock control device according to the utility model execution mode;
Fig. 2 is the fundamental diagram of the crystal oscillator clock according to the utility model execution mode;
Fig. 3 is the circuit diagram of the zero passage detection module of clock control device according to the utility model execution mode;
Fig. 4 is the high-level schematic functional block diagram of the control module according to the utility model execution mode;
Fig. 5 is the waveform schematic diagram normally worked according to the zero passage detection module of the utility model execution mode;
Fig. 6 is the waveform schematic diagram of the zero passage detection module abnormal work according to the utility model execution mode;
Fig. 7 is the clock control method flow chart according to the utility model execution mode;
Fig. 8 is the filtering process chart according to the utility model execution mode;
Fig. 9 is the clock alignment flow chart according to the utility model execution mode;
Figure 10 regulates flow chart according to the clock accuracy of the utility model execution mode.
Embodiment
Be described below in detail execution mode of the present utility model, the example of described execution mode is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the execution mode be described with reference to the drawings, only for explaining the utility model, and can not being interpreted as restriction of the present utility model.
In description of the present utility model, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end ", " interior ", " outward ", " clockwise ", orientation or the position relationship of the instruction such as " counterclockwise " are based on orientation shown in the drawings or position relationship, only the utility model and simplified characterization for convenience of description, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore can not be interpreted as restriction of the present utility model.In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise one or more described features.In description of the present utility model, the implication of " multiple " is two or more, unless otherwise expressly limited specifically.
In description of the present utility model, it should be noted that, unless otherwise clearly defined and limited, term " installation ", " connection ", " connection " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or connect integratedly; Can be mechanical connection, also can be electrical connection or can communication mutually; Can be direct connection, also indirectly can be connected by intermediary, can be the connection of two element internals or the interaction relationship of two elements.For the ordinary skill in the art, the concrete meaning of above-mentioned term in the utility model can be understood as the case may be.
In the utility model, unless otherwise clearly defined and limited, fisrt feature second feature it " on " or D score can comprise the first and second features and directly contact, also can comprise the first and second features and not be directly contact but by the other characterisation contact between them.And, fisrt feature second feature " on ", " top " and " above " comprise fisrt feature directly over second feature and oblique upper, or only represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " below " and " below " comprise fisrt feature directly over second feature and oblique upper, or only represent that fisrt feature level height is less than second feature.
Disclosing hereafter provides many different execution modes or example is used for realizing different structure of the present utility model.Of the present utility model open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the utility model.In addition, the utility model can in different example repeat reference numerals and/or reference letter, this repetition is to simplify and clearly object, itself does not indicate the relation between discussed various execution mode and/or setting.In addition, the various specific technique that the utility model provides and the example of material, but those of ordinary skill in the art can recognize the application of other techniques and/or the use of other materials.
Fig. 1 is the high-level schematic functional block diagram of the clock control device according to the utility model execution mode.
The clock control device 10 of execution mode of the present utility model comprises clock module 100, zero passage detection module 200, control module 300 and display module 400.
Clock module 100 is for providing the first clock signal.Zero passage detection module 200 exports zero cross signal ZERO for detecting civil power.Particularly, zero passage detection module 200, for judging the forward and reverse of city's signal of telecommunication, then exports zero cross signal ZERO.Control module 300 is connected with clock module 100 and zero passage detection module 200 respectively, control module 300 for the treatment of zero cross signal ZERO with obtain civil power second clock signal and according to second clock signal calibration first clock signal.Display module 400 is connected with control module 300, display module 400 for accurate clock information after showing calibration, such as, time, minute, second.
The clock control device of execution mode of the present utility model utilizes the civil power be connected with household electrical appliance to correct the first clock signal, because the cycle of civil power is by department of State Grid timing alignment, accuracy is high, and can not accumulate, that is to say that second clock new signal accuracy is high, and can not accumulate.And be connected with household electrical appliance due to civil power, zero cross signal ZERO easily obtains, convenient and cost is lower.
General, based on cost consideration, clock module 100 can be crystal oscillating circuit or Tao Zhen circuit.Namely the clock signal for crystal oscillator or Tao Zhen circuit provide believed by the first clock.
Fig. 2 is the fundamental diagram of the crystal oscillator clock according to the utility model execution mode.
General, the actual frequency f of crystal oscillating circuit
0error delta f=|f is there is with standard frequency f
0-f|, and error can build up.Usual error is 20PPM (Part Per Million hundred very much), i.e. the frequency of 10MHz, exists 200Hz error.In one-period T, error delta f=|f
0-f|, N number of all after dates, T=N/f, T
0=N/f
0, Δ T=|T-T
0|=(N*f
0-N*f)/(f*f
0)=(N* Δ f)/(f*f
0).Such as, f=10MHz, error is 20PPM, then f
0=9.9998MHz.As N=1M, T=0.1s, Δ T ≈ 0.2 μ s, as N=1000M, T=100s, Δ T=2ms; In other words every 100s just has 2ms error, accumulates and within one hour, has 36*2=72ms error, have the error of 24*72=1728ms=1.728s every day, needs to correct.
Fig. 3 is the circuit diagram of the zero passage detection module 200 according to the utility model execution mode.
Zero passage detection module 200 comprises photoelectrical coupler 210 and the first resistance R1.Photoelectrical coupler 210 comprises first input end, the second input, the first output and the second output.The first input end of photoelectrical coupler 210 is connected with the live wire of civil power, and the second input of photoelectrical coupler 210 is connected with the zero line of civil power, and the first output head grounding of photoelectrical coupler 210, photoelectrical coupler 210 can realize the isolation of forceful electric power and light current.One end of first resistance R1 is connected with the second output of photoelectrical coupler 210, and the other end of the first resistance R1 is output, and output is connected to export zero cross signal ZERO to control module 300 with control module 300, and the first resistance R1 is used for carrying out output current limiting.
Photoelectrical coupler 210 comprises light-emitting diode D and photosensitive triode Q.The anode of light-emitting diode D is the first input end of photoelectrical coupler 210, and the negative electrode of light-emitting diode D is the second input of photoelectrical coupler 210.The emitter E of phototriode Q is the first output of photoelectrical coupler 210, and the collector electrode C of phototriode Q is the second output of photoelectrical coupler 210.
Zero passage detection module 200 also comprises the first electric capacity C1.First electric capacity C1 is arranged in series between photoelectrical coupler 210 first output and the second output.One end of first electric capacity C1 is connected with the other end of the first resistance R1, the other end ground connection of the first electric capacity C1, and the signal that the first electric capacity C1 is used for output exports carries out filtering.
Zero passage detection module 200 also comprises the second resistance R2.Second resistance R2 is connected between photoelectrical coupler first input end and the live wire of civil power, and the second resistance R2 is used for carrying out for inputting current limliting.
Zero passage detection module 200 also comprises the 3rd resistance R3.One end of 3rd resistance R3 is connected with the second output of photoelectrical coupler 210, and the other end of the 3rd resistance R3 is connected with default power supply such as 5V DC power supply, and the 3rd resistance R3 is pull-up resistor.For drawing high level signal.
In other words, zero passage detection module 200 is made up of an optocoupler, three resistance and an electric capacity, for detecting the cycle of input civil power, and judges the positive direction of input civil power.Particularly, when city's signal of telecommunication is from the first input end of photoelectrical coupler 210 and the input of the second input, if the voltage of city's signal of telecommunication is in positive half period, light-emitting diode D conducting is luminous, the conducting of photosensitive triode Q light, thus the zero cross signal ZERO of output output low level; If the voltage of city's signal of telecommunication is in negative half-cycle, light-emitting diode D ends not luminous, and photosensitive triode Q ends, thus output exports the zero cross signal ZERO of high level.Thus, control module 300 can judge the forward and reverse of input civil power according to zero cross signal ZERO, and zero passage detection module 200 internal circuit configuration is simple, low price.
Fig. 4 is the high-level schematic functional block diagram of the control module 300 according to the utility model execution mode.
In the clock control device 10 of execution mode of the present utility model, control module 300 includes processing unit 310, clock selecting portion 320, clock filtering portion 330, clock alignment portion 340 and clock accuracy handling part 350.Processing unit 310 comprises chip port 311 and timer 312.
Chip port 311 and timer 312 are the input/output terminal of processing unit 310, correspondingly with clock selecting portion 320, clock filtering portion 330, clock alignment portion 340 and precision handling part 350 connect.Chip port 311 for inputing to processing unit 310 by above-mentioned each portion clock signal, and exports the clock signal after process to display module 400.Timer 312 is connected with clock selecting portion 320, and timer 312 for inputting the first clock signal, and exports the first clock signal to clock filtering portion 330, clock alignment portion 340 and precision handling part 350 via chip port.
Clock selecting portion 320 is for the first clock signal of selecting clock module 100 to provide after clock control device 10 powers on system clock as processing unit 10, and exporting the first clock signal to timer 312 place, system clock can provide the function such as timing and timing.
Under normal circumstances, the accuracy of zero passage detection module 200 may be deteriorated along with service time, causes civil power Signal Fail, can not directly be used for calibrating.
Concrete, Fig. 5 is the waveform schematic diagram normally worked according to the zero passage detection module 200 of the utility model execution mode.Mains frequency is converted to the frequency of zero cross signal ZERO by zero passage detection module 200: when civil power is positive voltage, and zero cross signal ZERO is low level, and when civil power is negative voltage, zero cross signal ZERO is high level.When zero passage detection module 200 normally works, TZERO normal period of zero cross signal ZERO equals the cycle T POWER of mains waveform substantially.But when in zero passage detection module 200, photoelectrical coupler 210 breaks down, zero cross signal cycle and normal period there is larger difference in TZERO.
Waveform schematic diagram when Fig. 6 is abnormal according to the zero passage detection module of an execution mode of the present utility model.When photoelectrical coupler 210 drives bad, there is B point in figure, cause TERR0 to be less than TPOWER.When photoelectrical coupler 210 breaks down, zero cross signal ZERO keeps high level or low level always, occurs D point in figure.When the temperature increases, the resistance R1 playing metering function becomes large, and zero cross signal ZERO rises slowly, occurs C point in figure, causes TERR1 to be greater than TPOWER.
Therefore, before to the first clock signal calibration, filtering process should be carried out to zero cross signal ZERO.Filtering process is realized by clock filtering portion 330.
The zero cross signal ZERO that 330 pairs, clock filtering portion zero passage detection module 200 is collected carries out filtering process.After filtering process, obtain the second clock signal of civil power, second clock signal enters clock alignment portion 340, and calibrates the first clock signal in timer 312 as benchmark.After calibration, the secondary signal of civil power and the clock signal of timer 312, by clock accuracy handling part 350, carry out the adjustment of clock accuracy, after adjustment by display module 400 by clock time, minute, second shows.
So, according to the clock control device 10 of execution mode of the present utility model by resources such as civil powers, stable clock source is obtained, and timer 312 is calibrated, when losing efficacy in outside stabilizing clock source, time clock feature still can normally be run, and precision meets the demands.
Fig. 7 is the clock control method flow chart according to the utility model execution mode, and in the present embodiment, the step of clock control method comprises:
S1, selects the first clock signal;
S2, collects the zero cross signal ZERO of civil power;
S3, to zero cross signal ZERO process, obtains the second clock signal of civil power; And
S4, calibrates the first clock signal according to second clock signal, obtains the 3rd clock signal;
After electrical equipment powers on, clock selecting portion 320 the first clock signal of selecting crystal oscillating circuit to provide exports timer 312 to as the internal clock signal of control module 300.Zero passage detection module 200 collects the zero cross signal ZERO of civil power, because zero passage detection module 200 may exist fault, therefore will carry out to the zero cross signal ZERO collected the second clock signal that filtering process obtains civil power by clock filtering portion 330.When city's signal of telecommunication is normal, second clock signal is calibrated via the first clock signal in 340 pairs, clock alignment portion timer 312 as benchmark, obtains the 3rd clock signal.Second clock signal and the 3rd clock signal carry out precision adjustment through clock accuracy handling part 350, to obtain accurate clock information.Clock information is exported by display module 400.When city's signal of telecommunication is normal, second clock signal output clock information can be used.During civil power abnormal signal, the 3rd clock signal output clock information can be used.
So, by easily obtain and city's signal of telecommunication that accuracy is high, obtain stable clock source, and controller internal clock signal calibrated, make the clock apparatus of electrical equipment can ensure high accuracy all the time.
Fig. 8 is the filtering process chart according to the utility model execution mode, i.e. step S3, comprises following sub-step:
S31, carries out filtering process to described zero cross signal, and filtering variable adds up; And
S32, judging that whether city's signal of telecommunication is normal according to filtering variable accumulated value, and to city's signal of telecommunication effective marker assignment, be normally 1, is 0 extremely.
The output port of zero passage detection module 200 is connected with chip port 311.Before filtering process, first carry out Initialize installation to chip port 311, concrete, chip port 311 is set to input state, and external interrupt is opened.And Initialize installation is carried out to timer 312, and concrete, timing base is set, and timer 312 is interrupted opening.Such as, timing base is set to 0.5ms, and the every 0.5ms of timer 312 interrupts once, then filtering variable adds 1.When external interrupt condition meets, such as zero cross signal ZERO is rising edge, and filtering variable adds up.Judge that whether filtering variable accumulated value is eligible, be namely greater than M, be less than N, when satisfying condition, filtering variable resets, and civil power clock effective marker position Q assignment 1, illustrates that city's signal of telecommunication is normal.If filtering variable is ineligible, then anomalous counts variable adds 1, and when anomalous counts variable is greater than predetermined value, anomalous counts variable resets, and civil power clock effective marker position Q assignment 0, illustrates civil power abnormal signal.The selection gist normal civil power periodical filtering variable of lower limit M and higher limit N ± 20%.Such as, if civil power is the frequency of 50Hz, timing base is 0.5ms, then normal civil power periodical filtering variable is 0.02/0.0005=40, its ± 20%, then can show that lower limit M be 32, higher limit N is 48.
So, the filtering process to city's signal of telecommunication can be completed, be easy to judge whether city's signal of telecommunication occurs exception, and do basis for the calibration carried out subsequently and precision regulate.
Fig. 9 is the clock alignment flow chart according to the utility model execution mode, i.e. step S4, comprises following sub-step:
According to city signal of telecommunication effective marker Q, S41, judges that whether city's signal of telecommunication is normal, if so, enters step S42, if not, return;
S42, calibrates, and calibration variables adds up; And
S43, when calibration variables is added to predetermined value, calibration terminates.
Before the input clock calibration of 330 pairs, clock alignment portion, the civil power effective marker Q that first will generate after clock filtering portion 330 filtering process according to zero cross signal ZERO judges that whether city's signal of telecommunication is normal.If city's signal of telecommunication is normal, then effective marker Q is 1, if civil power invalidating signal, then effective marker is 0.When city's signal of telecommunication is normal, carry out clock signal calibration, calibration marker P assignment 1.If city's signal of telecommunication is abnormal, then stops calibration, return to clock filtering portion 330.After calibration starts when zero cross signal ZERO becomes low level from high level, calibration variables M adds 1, if when city's frequency is 50Hz, each civil power cycle is 20ms, then cross signal ZERO level and become low level once every 20ms from high level.Initialize installation is carried out to timer 312, setting timing base and calibration duration.Such as timing base is set to 1ms, and the every 1ms of timer 312 interrupts once, and calibration variables N adds 1.Judge that whether calibration variables is eligible, as calibration variables M >=T, stop calibration, calibration marker P assignment becomes 0, and calibration value is the accumulated value of calibration variables N, and calibration variables N resets, and clock alignment terminates.T is the number of times of required counting in calibration duration, and length is 1 hour when calibrated, and when mains frequency is 50Hz, each civil power cycle is 20ms, then 1 hour needs counting 3600/0.02=180,000, i.e. T=180,000, and now N=3,600,000; If civil power is 60Hz, then T=3600*60=216,000.
So, can complete the calibration to timer clock signal in the normal situation of city's signal of telecommunication, accuracy is high.
Figure 10 regulates flow chart according to the clock accuracy of the utility model execution mode, and step also comprises following sub-step after step S4:
According to city signal of telecommunication effective marker Q, S51, judges that whether city's signal of telecommunication is normal, if so, enters step S52, if not, enter step S53;
S52, the civil power signal-count after using filtering to detect, the first timing variable adds up; And
S53, use the crystal oscillating circuit clock signal counting calibrated, the second timing variable adds up.
The second clock signal exported by clock filtering portion 330 filtering process and the 3rd clock signal exported through clock alignment portion 340, enter clock accuracy handling part 350.Before carrying out precision adjustment, whether normally again detect city's signal of telecommunication according to city signal of telecommunication effective marker Q.City's signal of telecommunication is then directly utilized to carry out clock count time normal.Carry out Initialize installation to chip port 311, concrete, chip port is set to input state, and external interrupt is opened, when external interrupt satisfies condition, such as zero cross signal ZERO is rising edge, and the first counting variable adds 1.When timing variable reaches predetermined value, the first counting variable resets, and the second of clock adds 1.When reaching 60 the second of clock, the second of clock resets, and dividing of clock adds 1.When clock point reach 60 time, point resetting of clock, clock time add 1, until counting process terminates.First counting variable is determined by mains frequency, and such as, if mains frequency is 50Hz, being then exactly 1s when the first counting variable equals 50, if civil power is 60Hz, is then exactly 1s when the first counting variable equals 60.If city's signal of telecommunication is abnormal, then the first clock signal of the timer 312 calibrated is utilized to carry out timing.Initialize installation is carried out to timer 312, concrete, timing base is set.Such as timing base is set to 1ms, and every 1ms second counting variable adds 1, and when the second counting variable reaches 1000, the second counting variable resets, and the second of clock adds 1.When reaching 60 the second of clock, the second of clock resets, and dividing of clock adds 1.When clock point reach 60 time, point resetting of clock, clock time add 1.The duration utilizing calibrated timer 312 clock signal to carry out counting can only be the setting calibration duration of timer 312, and the concrete time span that namely calibration value N is corresponding, time clock feature is only accurately within this time period.
So, the adjustment to clock accuracy can be completed.When city's signal frequency is normal, use city's signal of telecommunication timing, when civil power abnormal signal, use calibrated timer in controller to carry out timing, still can ensure the accuracy of clock.
An execution mode of the present utility model provides a kind of clock apparatus and control method, use existing computer board and hardware, and the resource such as civil power, obtain stable clock source, by means of the accuracy of city's signal of telecommunication, when its frequency is normal, the clock of main control chip is calibrated and precision adjustment, when external stabilization clock source lost efficacy, time clock feature still can normally be run, and precision meets the demands.
In the description of this specification, specific features, structure, material or feature that the description of reference term " execution mode ", " some execution modes ", " exemplary embodiment ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with described execution mode or example are contained at least one execution mode of the present utility model or example.In this manual, identical execution mode or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more execution mode or example.
Although illustrate and described execution mode of the present utility model, those having ordinary skill in the art will appreciate that: can carry out multiple change, amendment, replacement and modification to these execution modes when not departing from principle of the present utility model and aim, scope of the present utility model is by claim and equivalents thereof.
Claims (7)
1. a clock control device, is characterized in that, comprising:
Clock module, for providing the first clock signal;
Zero passage detection module, for detecting city's signal of telecommunication and obtaining zero cross signal; And
Control module, described control module respectively with described clock module and described zero passage detection model calling, described control module for the treatment of described zero cross signal with obtain civil power second clock signal and according to described second clock signal calibration the first clock signal.
2. clock control device as claimed in claim 1, it is characterized in that, described clock module is crystal oscillating circuit or Tao Zhen circuit.
3. clock control device as claimed in claim 1, it is characterized in that, described zero passage detection module comprises:
Photoelectrical coupler, described photoelectrical coupler comprises first input end, the second input, the first output and the second output; Described first input end is connected with the live wire of civil power, and described second input is connected with the zero line of civil power, described first output head grounding;
First resistance, described second output exports described zero cross signal by described first resistance;
Second resistance, described second resistant series is arranged between described first input end and civil power live wire;
3rd resistance, described 3rd resistance is arranged between described second output and predeterminated voltage; And
First electric capacity, described first capacitances in series is arranged between described second output and ground.
4. clock control device as claimed in claim 3, it is characterized in that, described photoelectrical coupler comprises:
Light-emitting diode, the anode of described light-emitting diode is described first input end, and the negative electrode of described Light-Emitting Diode is described second input; And
Phototriode, very described first output of transmitting of described phototriode, very described second output of current collection of described phototriode.
5. clock control device as claimed in claim 1, it is characterized in that, described control module comprises:
Processing unit, described processing unit comprises chip port and timer;
Clock selecting portion, described clock selecting portion is used for selective system clock;
Clock filtering portion, described clock filtering portion is used for carrying out filtering process to described zero cross signal;
Clock alignment portion, described clock alignment portion is used for calibrating described clock signal; And
Clock accuracy handling part, described clock accuracy handling part is used for regulating the precision of described clock signal.
6. clock control device as claimed in claim 5, it is characterized in that, described chip port and described timer are the input/output terminal of described processing unit, are connected with described clock selecting portion, described clock filtering portion, described clock alignment portion, described clock accuracy handling part.
7. clock control device as claimed in claim 1, it is characterized in that, described clock control device also includes the display module be connected with described control module, and described display module is used for read clock information.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520304898.1U CN204539101U (en) | 2015-05-12 | 2015-05-12 | Clock control device |
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|---|---|---|---|
| CN201520304898.1U CN204539101U (en) | 2015-05-12 | 2015-05-12 | Clock control device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104821806A (en) * | 2015-05-12 | 2015-08-05 | 广东美的厨房电器制造有限公司 | Clock control device and control method thereof |
| CN112099562A (en) * | 2020-08-27 | 2020-12-18 | 江苏美的清洁电器股份有限公司 | Power compensation control method and device, electric appliance, electronic equipment and storage medium |
-
2015
- 2015-05-12 CN CN201520304898.1U patent/CN204539101U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104821806A (en) * | 2015-05-12 | 2015-08-05 | 广东美的厨房电器制造有限公司 | Clock control device and control method thereof |
| CN104821806B (en) * | 2015-05-12 | 2018-01-02 | 广东美的厨房电器制造有限公司 | Clock control device and its control method |
| CN112099562A (en) * | 2020-08-27 | 2020-12-18 | 江苏美的清洁电器股份有限公司 | Power compensation control method and device, electric appliance, electronic equipment and storage medium |
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