CN104821806B - Clock control device and its control method - Google Patents
Clock control device and its control method Download PDFInfo
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- CN104821806B CN104821806B CN201510240857.5A CN201510240857A CN104821806B CN 104821806 B CN104821806 B CN 104821806B CN 201510240857 A CN201510240857 A CN 201510240857A CN 104821806 B CN104821806 B CN 104821806B
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Abstract
The invention discloses a kind of clock control device and its control method, clock control device includes display module, clock module, zero passage detection module and control module.Present invention also offers a kind of clock control method.There are severe deviations in clock signal use for a long time in electrical control module, and clock signal in control module is calibrated by city's electric signal and precision is adjusted, obtains accurately clock source.By the invention it is possible to obtain stable and accurate clock source, and control module internal clock is calibrated.
Description
Technical field
The present invention relates to field of household appliances, more particularly to a kind of clock control device and its control method.
Background technology
Existing household electrical appliance usually require the function with timing or timing, it is therefore desirable to clock signal.Based on cost
Consider, household electrical appliance typically obtain clock signal using the clock built in the controller of household electrical appliance or external crystal oscillating circuit.
However, error easily occur in built-in clock or the clock signal of crystal oscillating circuit, and with accumulated time, error is increasing,
Influence household electrical appliance normal work.Therefore clock signal is corrected, but existing correcting scheme it is complicated and into
This height.
The content of the invention
It is contemplated that at least solves one of technical problem present in prior art.Therefore, the present invention needs offer one
Kind clock control device and a kind of clock control method.
To reach above-mentioned purpose, the embodiment of first aspect present invention proposes a kind of clock control device, including：
Clock module, for providing the first clock signal；
Zero passage detection module, for detecting civil power and obtaining zero cross signal；And
Control module, the control module are connected with the clock module and the zero passage detection module respectively, the control
Molding block is used to handle the zero cross signal to obtain the second clock signal of civil power and according to the second clock signal calibration
First clock signal is to obtain the 3rd clock signal；
The control module includes：
Processing unit, the processing unit include chip port and timer；
Clock selecting portion, the clock selecting portion are used to select system clock；
Clock filtering portion, the clock filtering portion are used to be filtered processing to the zero cross signal；
Clock alignment portion, the clock alignment portion are used to calibrate first clock signal；And
Clock accuracy processing unit, the clock accuracy processing unit are used to adjust the precision of the 3rd clock signal
Section.
In some embodiments, the clock module is crystal oscillating circuit or Tao Zhen circuits.
In some embodiments, the zero passage detection module includes：
Photoelectrical coupler, it is defeated that the photoelectrical coupler includes first input end, the second input, the first output end and second
Go out end；The live wire connection of the first input end and civil power, the zero line connection of second input and civil power, described first is defeated
Go out end ground connection；
First resistor, second output end export the zero cross signal by the first resistor；
Second resistance, the second resistance are arranged in series between first input end and the civil power live wire；
3rd resistor, the 3rd resistor are arranged between second output end and predeterminated voltage；And
First electric capacity, first electric capacity are arranged in series between second output end and ground.
In some embodiments, the photoelectrical coupler includes：
Light emitting diode, the anode of the light emitting diode are the first input end, the negative electrode of the Light-Emitting Diode
For second input；And
Phototriode, extremely described first output end of transmitting of the phototriode, the collection of the phototriode
Electrode is second output end.
In some embodiments, the chip port and the input/output terminal that the timer is the processing unit,
It is connected with the clock selecting portion, the clock filtering portion, the clock alignment portion, the clock accuracy processing unit.
In some embodiments, the clock control device also includes the display mould being connected with the control module
Block, the display module be used for read clock when, minute, second.
To reach above-mentioned purpose, the embodiment of second aspect of the present invention proposes a kind of clock control method, including with
Lower step：
S1, select the first clock signal；
S2, collect the zero cross signal of civil power；
S3, processing is filtered to the zero cross signal, obtains the second clock signal of civil power；
The step S3 includes following sub-step：
S31, processing is filtered to the zero cross signal, and filtering variable adds up；And
S32, judge whether city's electric signal is normal according to the filtering variable accumulated value, and city's electric signal is effectively marked
Will assignment, it is normally 1, abnormal is 0；
S4, first clock signal is calibrated according to the second clock signal, obtains the 3rd clock signal；And
S5, the precision of the second clock signal or the 3rd clock signal is adjusted.
In some embodiments, the step S4 includes sub-step：
S41, judge whether city's electric signal is normal according to city's electric signal effective marker, if so, into step
S42, if it is not, returning；
S42, calibrated, calibration variables add up；And
S43, when the calibration variables are added to predetermined value, calibration terminates.
In some embodiments, the step S5 includes sub-step：
S51, judge whether city's electric signal is normal according to city's electric signal effective marker, if so, into step
S52, if it is not, into step S53；
S52, the second clock signal carry out clock count, and the first timing variable adds up；And
S53, the 3rd clock signal carry out clock count, and the second timing variable adds up.
The additional aspect and advantage of the present invention will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
The above-mentioned and/or additional method and advantage of the present invention is from combining in description of the accompanying drawings below to embodiment by change
Obtain substantially and be readily appreciated that, wherein：
Fig. 1 is the high-level schematic functional block diagram according to the clock control device of one embodiment of the present invention；
Fig. 2 is the fundamental diagram according to the crystal oscillator clock of one embodiment of the present invention；
Fig. 3 is the circuit diagram according to the zero passage detection module of the clock control device of one embodiment of the present invention；
Fig. 4 is the high-level schematic functional block diagram according to the control module of one embodiment of the present invention；
Fig. 5 is the waveform diagram according to the zero passage detection module normal work of one embodiment of the present invention；
Fig. 6 is the waveform diagram according to the zero passage detection module abnormal work of one embodiment of the present invention；
Fig. 7 is the clock control method flow chart according to one embodiment of the present invention；
Fig. 8 is the filtering process flow chart according to one embodiment of the present invention；
Fig. 9 is the clock alignment flow chart according to one embodiment of the present invention；
Figure 10 is the clock accuracy regulation flow process figure according to one embodiment of the present invention.
Embodiment
Embodiments of the present invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning
Same or similar element is represented to same or similar label eventually or there is the element of same or like function.Below by ginseng
The embodiment for examining accompanying drawing description is exemplary, is only used for explaining the present invention, and is not considered as limiting the invention.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", " on ", " under ", "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer ", " up time
The orientation or position relationship of the instruction such as pin ", " counterclockwise " are based on orientation shown in the drawings or position relationship, are for only for ease of
Description is of the invention to be described with simplified, rather than the device or element of instruction or hint meaning must be with specific orientation, Yi Te
Fixed azimuth configuration and operation, therefore be not considered as limiting the invention.In addition, term " first ", " second " are only used for
Purpose is described, and it is not intended that instruction or hint relative importance or the implicit quantity for indicating indicated technical characteristic.
Thus, " first " is defined, the feature of " second " can be expressed or implicitly includes one or more feature.
In description of the invention, " multiple " are meant that two or more, unless otherwise specifically defined.
In the description of the invention, it is necessary to which explanation, unless otherwise clearly defined and limited, term " installation ", " connects
Connect ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection or can mutually communicate；Can be directly connected to, can also be by between intermediary
Connect in succession, can be connection or the interaction relationship of two elements of two element internals.For the ordinary skill of this area
For personnel, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature it " on " or it " under "
Can directly it be contacted including the first and second features, it is not directly to contact but pass through it that can also include the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " top " and " above " to include first special
Sign is directly over second feature and oblique upper, or is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature exists
Second feature " under ", " lower section " and " following " fisrt feature that includes are directly over second feature and oblique upper, or be merely representative of
Fisrt feature level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the part and setting of specific examples are described.Certainly, they are only example, and
And purpose does not lie in the limitation present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, between itself not indicating discussed various embodiments and/or setting
Relation.In addition, the invention provides various specific techniques and material examples, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
Fig. 1 is the high-level schematic functional block diagram according to the clock control device of one embodiment of the present invention.
The clock control device 10 of embodiments of the present invention includes clock module 100, zero passage detection module 200, control
Module 300 and display module 400.
Clock module 100 is used to provide the first clock signal.Zero passage detection module 200 is used to detect with defeated civil power
Go out zero cross signal ZERO.Specifically, zero passage detection module 200 is used to judge the forward and reverse of city's electric signal, then exports zero passage letter
Number ZERO.Control module 300 is connected with clock module 100 and zero passage detection module 200 respectively, and control module 300 is used to handle
Zero cross signal ZERO is to obtain the second clock signal of civil power and according to the clock signal of second clock signal calibration first.Show mould
Block 400 is connected with control module 300, display module 400 be used for show calibration after accurate clock information, such as when, minute, second.
The clock control device of embodiments of the present invention corrects the first clock using the civil power being connected with household electrical appliance
Signal, because the cycle of civil power is by department of State Grid timing alignment, accuracy is high, and will not accumulate, when that is to say second
Clock new signal accuracy is high, and will not accumulate.And because civil power is connected with household electrical appliance, zero cross signal ZERO is easily obtained
, convenient and cost is relatively low.
In general, based on cost consideration, clock module 100 can be crystal oscillating circuit or Tao Zhen circuits.That is the first clock is believed
The clock signal provided for crystal oscillator or Tao Zhen circuits.
Fig. 2 is the fundamental diagram according to the crystal oscillator clock of one embodiment of the present invention.
In general, the actual frequency f of crystal oscillating circuit0Error delta f=be present with standard frequency f | f0- f |, and error can be by
Gradually accumulate.Usual error is 20PPM (Part Per Million million divide), i.e. 10MHz frequency, 200Hz errors be present.One
In individual cycle T, error delta f=| f0- f |, after N number of cycle, T=N/f, T0=N/f0, Δ T=| T-T0|=(N*f0-N*f)/(f*
f0)=(N* Δ f)/(f*f0).For example, f=10MHz, error 20PPM, then f0=9.9998MHz.As N=1M, T=
The μ s of 0.1s, Δ T ≈ 0.2, as N=1000M, T=100s, Δ T=2ms；In other words just there are 2ms errors per 100s, accumulate
There are 36*2=72ms errors one hour, has 24*72=1728ms=1.728s error daily, it is necessary to correct.
Fig. 3 is the circuit diagram according to the zero passage detection module 200 of one embodiment of the present invention.
Zero passage detection module 200 includes photoelectrical coupler 210 and first resistor R1.It is defeated that photoelectrical coupler 210 includes first
Enter end, the second input, the first output end and the second output end.The first input end of photoelectrical coupler 210 and the live wire of civil power
Connection, the second input of photoelectrical coupler 210 and the zero line of civil power connect, the first output head grounding of photoelectrical coupler 210,
Photoelectrical coupler 210 can realize the isolation of forceful electric power and light current.First resistor R1 one end and the second output of photoelectrical coupler 210
End connection, the first resistor R1 other end is output end, and output end is connected with control module 300 to be exported to control module 300
Zero cross signal ZERO, first resistor R1 are used to carry out output current limiting.
Photoelectrical coupler 210 includes light emitting diode D and photosensitive triode Q.Light emitting diode D anode is photoelectric coupling
The first input end of device 210, light emitting diode D negative electrode are the second input of photoelectrical coupler 210.Phototriode Q's
Emitter E is the first output end of photoelectrical coupler 210, and phototriode Q colelctor electrode C is the second of photoelectrical coupler 210
Output end.
Zero passage detection module 200 also includes the first electric capacity C1.First electric capacity C1 is arranged in series in photoelectrical coupler 210 first
Between output end and the second output end.First electric capacity C1 one end is connected with the first resistor R1 other end, the first electric capacity C1's
The other end is grounded, and the first electric capacity C1 is used to be filtered the signal of output end output.
Zero passage detection module 200 also includes second resistance R2.Second resistance R2 is connected to photoelectrical coupler first input end
Between the live wire of civil power, second resistance R2 is used to carry out being used to input current limliting.
Zero passage detection module 200 also includes 3rd resistor R3.3rd resistor R3 one end and the second of photoelectrical coupler 210
Output end is connected, and the 3rd resistor R3 other end is connected with default power supply such as 5V dc sources, and 3rd resistor R3 is pull-up electricity
Resistance.For drawing high level signal.
In other words, zero passage detection module 200 is made up of an optocoupler, three resistance and an electric capacity, defeated for detecting
Enter the cycle of civil power, and judge to input the positive direction of civil power.Specifically, when city's electric signal is defeated from the first of photoelectrical coupler 210
When entering end and the input of the second input, if the voltage of city's electric signal is in positive half period, light emitting diode D conductings are luminous, light
Quick triode Q is by light conduction, so as to which output end exports low level zero cross signal ZERO；If the voltage of city's electric signal is in negative
Half period, light emitting diode D cut-offs do not light, photosensitive triode Q cut-offs, so as to which output end exports the zero cross signal of high level
ZERO.Thus, control module 300 can judge the forward and reverse of input civil power, and zero passage detection module according to zero cross signal ZERO
200 internal circuit configurations are simple, cheap.
Fig. 4 is the high-level schematic functional block diagram according to the control module 300 of one embodiment of the present invention.
In the clock control device 10 of embodiments of the present invention, control module 300 includes processing unit 310, clock
Selector 320, clock filtering portion 330, clock alignment portion 340 and clock accuracy processing unit 350.Processing unit 310 includes chip
Port 311 and timer 312.
Chip port 311 and the input/output terminal that timer 312 is processing unit 310, with clock selecting portion 320, clock
Filtering part 330, clock alignment portion 340 and precision processing unit 350 are corresponding to be connected.Chip port 311 is used for will be defeated by above-mentioned each portion
Go out at clock signal input to processing unit 310, and the clock signal after processing is exported to display module 400.Timer 312
It is connected with clock selecting portion 320, timer 312 is used to input the first clock signal, and believes the first clock via chip port
Number output is to clock filtering portion 330, clock alignment portion 340 and precision processing unit 350.
Clock selecting portion 320 is used for the first clock for selecting clock module 100 to provide after electricity on clock control device 10
System clock of the signal as processing unit 10, and the first clock signal is exported to timer 312, system clock can carry
For the function such as timing and timing.
Under normal circumstances, the accuracy of zero passage detection module 200 is deteriorated such as usage time, causes city's electric signal to lose
Effect, it is impossible to be used directly to calibrate.
Specifically, Fig. 5 is illustrated according to the waveform of the normal work of zero passage detection module 200 of one embodiment of the present invention
Figure.Zero passage detection module 200 is converted to mains frequency zero cross signal ZERO frequency：When civil power is positive voltage, zero passage letter
Number ZERO is low level, and when civil power is negative voltage, zero cross signal ZERO is high level.The normal work of zero passage detection module 200
When, zero cross signal ZERO TZERO normal period is substantially equal to the cycle T POWER of mains waveform.But work as zero passage detection module
When photoelectrical coupler 210 breaks down in 200, there is larger difference with TZERO normal period in the zero cross signal cycle.
Waveform diagram when Fig. 6 is the zero passage detection module exception according to an embodiment of the invention.Work as photoelectricity
When coupler 210 drives bad, there are B points in figure, cause TERR0 to be less than TPOWER.When photoelectrical coupler 210 breaks down, mistake
Zero-signal ZERO is always maintained at high level or low level, D points in figure occurs.When the temperature increases, the resistance R1 of metering function is played
Become big, zero cross signal ZERO rises slowly, C points in figure occurs, causes TERR1 to be more than TPOWER.
Therefore, before being calibrated to the first clock signal, processing should be filtered to zero cross signal ZERO.Filtering process by
Realize in clock filtering portion 330.
The zero cross signal ZERO that clock filtering portion 330 is collected to zero passage detection module 200 is filtered processing.Filtering process
Afterwards, the second clock signal of civil power is obtained, second clock signal enters clock alignment portion 340, and as benchmark to timer 312
In the first clock signal calibrated.After calibration, when the secondary signal of civil power and the clock signal of timer 312 pass through
Clock precision processing unit 350, carries out the regulation of clock accuracy, after regulation by display module 400 by clock when, minute, second shows
Out.
In this way, when clock control device 10 according to the embodiment of the present invention by resources such as civil powers, obtains stable
Zhong Yuan, and being calibrated to timer 312, when being failed in outside stabilizing clock source, time clock feature still can with normal operation, and
And precision meets to require.
Fig. 7 is the clock control method flow chart according to one embodiment of the present invention, in the present embodiment, when clock
The step of method processed, includes：
S1, select the first clock signal；
S2, collect the zero cross signal ZERO of civil power；
S3, to zero cross signal ZERO processing, obtain the second clock signal of civil power；And
S4, the first clock signal is calibrated according to second clock signal, obtains the 3rd clock signal；
On electrical equipment after electricity, clock selecting portion 320 selects the first clock signal that crystal oscillating circuit provides as control module 300
Internal clock signal export to timer 312.Zero passage detection module 200 collects the zero cross signal ZERO of civil power, due to zero passage
Detection module 200 may have failure, therefore the zero cross signal ZERO being collected into be filtered by clock filtering portion 330
Ripple handles to obtain the second clock signal of civil power.When in city, electric signal is normal, second clock signal is as benchmark via clock school
Quasi- portion 340 is calibrated to the first clock signal in timer 312, obtains the 3rd clock signal.Second clock signal and
Three clock signals carry out precision regulation by clock accuracy processing unit 350, to obtain accurate clock information.Clock information passes through
Display module 400 exports.When city's electric signal is normal, second clock signal output clock information can be used.During civil power abnormal signal,
The 3rd clock signal can be used to export clock information.
In this way, by city's electric signal easily obtain and high accuracy, stable clock source is obtained, and in controller
Portion's clock signal is calibrated so that the clock apparatus of electrical equipment can ensure high accuracy all the time.
Fig. 8 is the filtering process flow chart according to one embodiment of the present invention, i.e. step S3, including following sub-step：
S31, processing is filtered to the zero cross signal, and filtering variable adds up；And
S32, judge whether city's electric signal is normal according to filtering variable accumulated value, and to city's electric signal effective marker assignment,
Normal is 1, and abnormal is 0.
The output port of zero passage detection module 200 is connected with chip port 311.Before filtering process, first to die terminals
Mouth 311 carries out Initialize installations, specifically, chip port 311 is set into input state, and external interrupt is opened.And to fixed
When device 312 carry out Initialize installation, specifically, setting timing base, and timer 312 is interrupted into opening.For example, timing base
0.5ms is arranged to, timer 312 interrupts once per 0.5ms, then filters variable and add 1.When external interrupt condition meets, such as
Zero cross signal ZERO is rising edge, and filtering variable adds up.Judge whether filtering variable accumulated value is eligible, i.e., more than M, is less than
N, when meeting condition, filtering variable is reset, and civil power clock effective marker position Q assignment 1, illustrates that city's electric signal is normal.If filtering becomes
Measure ineligible, then anomalous counts variable adds 1, and when anomalous counts variable is more than predetermined value, anomalous counts variable is reset, city
Electric clock effective marker position Q assignment 0, illustrates civil power abnormal signal.Lower limit M and higher limit N selection gist normal civil power week
± the 20% of phase filtering variable.For example, if civil power is 50Hz frequency, timing base 0.5ms, then normal civil power periodical filtering
Variable is 0.02/0.0005=40, its ± 20%, then can draw lower limit M be 32, higher limit N be 48.
In this way, the filtering process to city's electric signal can be completed, it is easy to judge whether city's electric signal exception occurs, and is subsequent
Basis is done in the calibration of progress and precision regulation.
Fig. 9 is the clock alignment flow chart according to one embodiment of the present invention, i.e. step S4, including following sub-step：
S41, judge whether city's electric signal is normal according to city electric signal effective marker Q, if so, into step S42, if it is not,
Return；
S42, calibrated, calibration variables add up；And
S43, when calibration variables are added to predetermined value, calibration terminates.
Before calibrating input clock in clock alignment portion 330, first have to pass through clock filtering portion according to zero cross signal ZERO
The civil power effective marker Q generated after 330 filtering process judges whether city's electric signal is normal.If city's electric signal is normal, there is criterion
Will Q is 1, if civil power invalidating signal, effective marker 0.When electric signal is normal in city, enter row clock signal calibration, calibration mark
Will P assignment 1.If city's electric signal is abnormal, stop calibration, return to clock filtering portion 330.Calibrate after starting whenever zero cross signal
When ZERO is changed into low level from high level, calibration variables M adds 1, if city's frequency is 50Hz, each civil power cycle is 20ms, then
Cross signal ZERO level and low level is changed into once from high level every 20ms.Initialize installation is carried out to timer 312, setting is fixed
When benchmark and calibration duration.Such as timing base is set to 1ms, timer 312 interrupts once per 1ms, and calibration variables N adds 1.Judge
Whether calibration variables are eligible, as calibration variables M >=T, stop calibration, calibration marker P assignment is changed into 0, and calibration value is school
Quasivariable N accumulated value, calibration variables N are reset, and clock alignment terminates.T is the number of required counting in calibration duration, works as calibration
Shi Changwei 1 hour, when mains frequency is 50Hz, each civil power cycle is 20ms, then needs within 1 hour to count 3600/0.02=
180,000, i.e. T=180,000, now N=3,600,000；If civil power is 60Hz, T=3600*60=216,000.
In this way, the calibration to timer clock signal can be completed in the case of city's electric signal is normal, accuracy is high.
Figure 10 is the clock accuracy regulation flow process figure according to one embodiment of the present invention, and step also includes after step S4
Following sub-step：
S51, judge whether city's electric signal is normal according to city electric signal effective marker Q, if so, into step S52, if it is not,
Into step S53；
S52, the civil power signal-count after being detected using filtering, the first timing variable are added up；And
S53, is counted using the crystal oscillating circuit clock signal calibrated, and the second timing variable adds up.
The second clock signal exported by the filtering process of clock filtering portion 330 and exported through clock alignment portion 340 the
Three clock signals, into clock accuracy processing unit 350.Before carrying out precision regulation, detected again according to city electric signal effective marker Q
Whether city's electric signal is normal.Then directly clock count is carried out when normal using city's electric signal.Chip port 311 is initialized
Set, specifically, chip port is set into input state, and external interrupt is opened, when external interrupt meets condition, such as
Zero cross signal ZERO is rising edge, and the first counting variable adds 1.When timing variable reaches predetermined value, the first counting variable is clear
Zero, the second of clock adds 1.When the second of clock reaching 60, the second of clock resets, and dividing for clock adds 1.Reach 60 when dividing for clock
When, clock distinguishes zero, clock when add 1, until counting process terminates.First counting variable determines by mains frequency, for example,
It is exactly 1s when the first counting variable is equal to 50, if civil power is 60Hz, the first counting variable is equal to if mains frequency is 50Hz
It is exactly 1s when 60.If city's electric signal is abnormal, using the first clock signal of calibrated timer 312 come timing.It is right
Timer 312 carries out Initialize installation, specifically, setting timing base.Such as timing base is set to 1ms, counted per 1ms second
Variable adds 1, and when the second counting variable reaches 1000, the second counting variable is reset, and the second of clock adds 1.Reach when the second of clock
When 60, the second of clock resets, and dividing for clock adds 1.When clock is when point reaching 60, clock distinguishes zero, clock when add 1.Profit
The duration counted with the calibrated clock signal of timer 312 can only be the setting calibration duration of timer 312, that is, calibrate
Specific time span corresponding to value N, time clock feature are only accurate within the period.
In this way, the regulation to clock accuracy can be completed.When in city, signal frequency is normal, using city's electric signal timing,
During civil power abnormal signal, timing is carried out using timer calibrated in controller, still ensures that the accuracy of clock.
An embodiment of the invention provides a kind of clock apparatus and control method, borrows existing computer board and hard
Part, and the resource such as civil power, stable clock source is obtained, by the accuracy of city's electric signal, when its frequency is normal to master control
The clock of chip calibrated and precision regulation, when external stabilization clock source fails, time clock feature still can with normal operation,
And precision meets to require.
In the description of this specification, reference term " embodiment ", " some embodiments ", " schematically implementation
The description of mode ", " example ", " specific example " or " some examples " etc. means with reference to the embodiment or example description
Specific features, structure, material or feature are contained at least one embodiment or example of the present invention.In this specification
In, identical embodiment or example are not necessarily referring to the schematic representation of above-mentioned term.Moreover, the specific spy of description
Sign, structure, material or feature can combine in an appropriate manner in any one or more embodiments or example.
While embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that：
These embodiments can be carried out with a variety of changes, modification in the case of not departing from the principle and objective of the present invention, replace and become
Type, the scope of the present invention are limited by claim and its equivalent.
Claims (9)
- A kind of 1. clock control device, it is characterised in that including：Clock module, for providing the first clock signal；Zero passage detection module, for detecting city's electric signal and obtaining zero cross signal；AndControl module, the control module are connected with the clock module and the zero passage detection module respectively, the control mould Block is used to handle the zero cross signal to obtain the second clock signal of civil power and according to the second clock signal calibration First clock signal is to obtain the 3rd clock signal；The control module includes：Processing unit, the processing unit include chip port and timer；Clock selecting portion, the clock selecting portion are used to select system clock；Clock filtering portion, the clock filtering portion are used to be filtered processing to the zero cross signal；Clock alignment portion, the clock alignment portion are used to calibrate first clock signal；AndClock accuracy processing unit, the clock accuracy processing unit are used for the second clock signal or the 3rd clock signal Precision be adjusted.
- 2. clock control device as claimed in claim 1, it is characterised in that the clock module is crystal oscillating circuit or Tao Zhen electricity Road.
- 3. clock control device as claimed in claim 1, it is characterised in that the zero passage detection module includes：Photoelectrical coupler, the photoelectrical coupler include first input end, the second input, the first output end and the second output End；The live wire connection of the first input end and civil power, the zero line connection of second input and civil power, first output End ground connection；First resistor, second output end export the zero cross signal by the first resistor；Second resistance, the second resistance are arranged in series between first input end and the civil power live wire；3rd resistor, the 3rd resistor are arranged between second output end and predeterminated voltage；AndFirst electric capacity, first electric capacity are arranged in series between second output end and ground.
- 4. clock control device as claimed in claim 3, it is characterised in that the photoelectrical coupler includes：Light emitting diode, the anode of the light emitting diode is the first input end, and the negative electrode of the Light-Emitting Diode is institute State the second input；AndPhototriode, extremely described first output end of transmitting of the phototriode, the colelctor electrode of the phototriode For second output end.
- 5. clock control device as claimed in claim 1, it is characterised in that the chip port and the timer are described The input/output terminal of processing unit, with the clock selecting portion, the clock filtering portion, the clock alignment portion, the clock Precision processing unit connects.
- 6. clock control device as claimed in claim 1, it is characterised in that the clock control device also include with it is described The display module of control module connection, the display module are used for read clock information.
- 7. a kind of clock control method, it is characterised in that comprise the following steps：S1, select the first clock signal；S2, collect the zero cross signal of civil power；S3, the zero cross signal is handled, obtain second clock signal；The step S3 includes following sub-step：S31, processing is filtered to the zero cross signal, and filtering variable adds up；AndS32, judge whether city's electric signal is normal according to the filtering variable accumulated value, and city's electric signal effective marker is assigned Value, is normally 1, and abnormal is 0；S4, the clock signal of clock first is calibrated according to the second clock signal, obtains the 3rd clock signal；AndS5, the precision of the second clock signal or the 3rd clock signal is adjusted.
- 8. clock control method as claimed in claim 7, it is characterised in that the step S4 includes sub-step：S41, judge whether city's electric signal is normal according to city's electric signal effective marker, if so, into step S42, if It is no, return；S42, calibrated, calibration variables add up；AndS43, when the calibration variables are added to predetermined value, calibration terminates.
- 9. clock control method as claimed in claim 7, it is characterised in that the step also includes son after the step S4 Step：S51, judge whether city's electric signal is normal according to city's electric signal effective marker, if so, into step S52；If It is no, into step S53；S52, the second clock signal carry out clock count, and the first timing variable adds up；AndS53, the 3rd clock signal carry out clock count, and the second timing variable adds up.
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