WO2020143521A1

WO2020143521A1 - Digital audio signal sampling frequency detection method and device

Info

Publication number: WO2020143521A1
Application number: PCT/CN2020/070061
Authority: WO
Inventors: 蒋松鹰; 姚炜; 管少钧
Original assignee: 上海艾为电子技术股份有限公司
Priority date: 2019-01-09
Filing date: 2020-01-02
Publication date: 2020-07-16
Also published as: CN109459612A

Abstract

A digital audio signal sampling frequency detection method and device. The method comprises: by means of a reference clock signal and a sampling rate clock signal of a digital audio signal, detecting the sampling frequency of the digital audio signal; when it is detected that the sampling frequency of the digital audio signal is not matched with a preset theoretical sampling frequency, outputting a detection result, so that software can adjust the sampling frequency of the digital audio signal timely or adjust the theoretical sampling frequency, thereby realizing the effect of preventing the phenomenon that an audio amplifier chip is damaged when the software configures the sampling frequency incorrectly.

Description

Method and device for detecting sampling frequency of digital audio signal

This application requires the priority of the Chinese patent application submitted to the China Patent Office on January 09, 2019, with the application number 201910020489.1 and the application name "Sampling Frequency Detection Method and Device for Digital Audio Signals", the entire contents of which are incorporated by reference In this application.

Technical field

The invention relates to the technical field of integrated circuits, in particular to a method and device for detecting the sampling frequency of digital audio signals.

Background technique

With the popularity of personal computers, more and more users use music software on computers and peripheral audio playback devices to play music. As an important part of the playback device, the audio amplifier chip plays the role of receiving digital audio signals sent by music software and controlling the speakers to play the corresponding audio.

Music software usually supports multiple audio formats, and the sampling frequencies of audio signals corresponding to different audio formats are also different. When the audio amplifier chip is working, the software needs to configure a theoretical sampling frequency matching the sampling frequency of the actually transmitted audio signal. When the software configuration is wrong, the theoretical sampling frequency does not match the sampling frequency of the actually transmitted audio signal At this time, the audio amplifier chip is prone to damage.

Application content

Based on the above deficiencies of the prior art, the present invention proposes a method and device for detecting the sampling frequency of digital audio signals to prevent the audio amplifier chip from being damaged when the sampling frequency of the software configuration is wrong.

In order to solve the above problems, the proposed solutions are as follows:

The first aspect of the present application provides a method for detecting a sampling frequency of a digital audio signal, including:

Obtain reference clock signal and sampling rate clock signal;

Calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal;

Calculating the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal;

Judging whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain a judgment result;

If the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.

Optionally, before calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal, the method further includes:

Frequency-dividing the reference clock signal to obtain a reference clock signal whose frequency is less than the frequency of the sampling rate clock signal.

Adjusting the reference clock signal to obtain a reference clock signal synchronized with the sampling rate clock signal.

Optionally, the calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal includes:

Calculating the total pulse number of the sampling rate clock signal in N cycles of the reference clock signal, where N is a preset positive integer;

Divide the total number of pulses by N to obtain the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal.

Optionally, the judging whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain a judgment result includes:

Calculating the difference between the sampling frequency of the digital audio signal and the theoretical sampling frequency;

Determine whether the absolute value of the difference is less than a preset threshold;

Wherein, if the absolute value of the difference is greater than or equal to the threshold, it is determined that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency; if the absolute value of the difference is less than the threshold, then It is determined that the sampling frequency of the digital audio signal matches the theoretical sampling frequency.

The second aspect of the present application provides a detection device for a sampling frequency of a digital audio signal, including:

A calculation unit, configured to acquire a reference clock signal and a sampling rate clock signal, and calculate the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal;

The comparison unit is used to calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal, and determine whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain a judgment As a result, if the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.

Optionally, the calculation unit includes:

The counting unit is used to obtain the reference clock signal and the sampling rate clock signal, and calculate the pulse number of the sampling rate clock signal within one cycle of the reference clock signal;

The latch unit is used to store the calculated pulse number.

Optionally, the calculation unit includes:

The counting unit is used to obtain a reference clock signal and a sampling rate clock signal, and calculate the total number of pulses of the sampling rate clock signal in N cycles of the reference clock signal, where N is a preset positive integer;

Latch unit, used to save the calculated total pulse number;

A counting and averaging unit is used to obtain the total number of pulses, and divide the total number of pulses by N to obtain the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal.

Optionally, the device further includes:

A frequency divider, configured to obtain the reference clock signal and divide the reference clock signal to obtain a reference clock signal whose frequency is less than the frequency of the sampling rate clock signal;

Wherein, the reference clock signal acquired by the calculation unit is: a reference clock signal whose frequency is less than the frequency of the sampling rate clock signal obtained by the frequency divider.

Optionally, the device further includes:

A synchronization unit, configured to obtain a reference clock signal and a sampling rate clock signal, and adjust the reference clock signal to obtain a reference clock signal synchronized with the sampling rate clock signal;

Wherein, the reference clock signal acquired by the calculation unit is: a reference clock signal synchronized with the sampling rate clock signal.

The invention provides a method and a device for detecting the sampling frequency of a digital audio signal, which uses a reference clock signal and a sampling rate clock signal of a digital audio signal to detect the sampling frequency of the digital audio signal. When the sampling frequency of the digital audio signal does not match the preset theoretical sampling frequency, the output of the detection result can enable the software to adjust the sampling frequency of the digital audio signal in time or adjust the theoretical sampling frequency, which can prevent the audio amplification chip The damage occurs when the sampling frequency of the software configuration is wrong.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only This is an embodiment of the present application. For a person of ordinary skill in the art, without paying any creative work, other drawings may be obtained according to the provided drawings.

1 is a schematic flowchart of a method for detecting a sampling frequency of a digital audio signal disclosed in an embodiment of the present invention;

2 is a schematic flowchart of a method for detecting a sampling frequency of a digital audio signal disclosed in another embodiment of the present invention;

3 is a schematic diagram of a device for detecting a sampling frequency of a digital audio signal disclosed in an embodiment of the present invention;

4 is a schematic diagram of a device for detecting a sampling frequency of a digital audio signal disclosed in another embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

For the method for detecting the sampling frequency of the digital audio signal provided by the embodiment of the present application, please refer to FIG.

S101. Obtain a reference clock signal and a sampling rate clock signal.

It should be noted that, in an alternative solution, the reference clock signal is a clock signal whose frequency is known and stable. In order to implement the detection method provided by the embodiment of the present application, the reference clock signal should be a clock signal whose frequency is less than the frequency of the sampling rate clock signal, or should be a slow clock signal relative to the sampling rate clock signal . And, the reference clock signal is a clock signal synchronized with the sampling rate clock signal. Specifically, the sampling frequency of the digital audio signal is generally between 8KHz and 48KHz, therefore, the reference clock signal may be a 1KHz clock signal.

It should be noted that the sampling rate clock signal is a clock signal transmitted to the audio amplification chip together with the digital audio signal, and the frequency of the sampling rate clock signal is the sampling frequency of the digital audio signal, or, The frequency of the sampling rate clock signal is always equal to the sampling frequency of the digital audio signal.

In this embodiment, the synchronization of the reference clock signal and the sampling rate clock signal means that one rising edge of each reference clock corresponds exactly to the rising edge of one sampling rate clock. It is not difficult to understand that the frequency of the reference clock signal and the sampling rate clock signal may be different.

S102. Calculate the number of pulses of the sampling rate clock signal in one cycle of the reference clock signal.

It should be noted that the calculated pulse number of the sampling rate clock signal in one cycle of the reference clock signal may be regarded as a ratio of the frequency of the sampling rate clock signal to the frequency of the reference clock signal.

S103. Calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal.

It should be noted that, since the frequency of the sampling rate clock signal is always equal to the sampling frequency of the digital audio signal, calculating the sampling frequency of the digital audio signal in step S103 actually calculates the sampling rate clock signal frequency.

S104. Determine whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain a judgment result.

It should be noted that the theoretical sampling frequency is the sampling frequency configured by the software.

It should be noted that the judgment whether the sampling frequency of the digital audio signal (which can also be understood as the actual sampling frequency) matches the pre-configured theoretical sampling frequency can be strictly judged whether the actual sampling frequency is equal to the theoretical sampling frequency, if If they are not equal, it is considered that the two frequencies do not match, or an error range can be set. If the error between the actual sampling frequency and the theoretical sampling frequency is within the range, the two frequencies are considered to match. Frequencies do not match.

S105. If the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, output the judgment result.

It should be noted that the output of the sampling result when the judgment result indicates that the actual sampling frequency does not match the theoretical sampling frequency can be implemented in the following manner, of course, there may be multiple specific implementation manners, including all of the following implementation manners The specific implementation methods that can achieve the effect described in step S105 are within the scope of protection of this application:

In the first way, if the actual sampling frequency matches the theoretical sampling frequency, no signal is output, and when the actual sampling frequency does not match the theoretical sampling frequency, an alarm signal is output to the software.

In the second way, when the actual sampling frequency matches the theoretical sampling frequency, a signal 1 is output to the software, and when the actual sampling frequency does not match the theoretical sampling frequency, a signal 0 is output to the software, thereby The software indicates that the currently configured theoretical sampling frequency does not match the actual sampling frequency. Of course, it is also possible to output 0 when matching and 1 when not matching.

The method for detecting the sampling frequency of a digital audio signal provided by an embodiment of the present application calculates the sampling frequency of the digital audio signal using a reference clock signal and a sampling rate clock signal of the digital audio signal, thereby realizing the sampling frequency of the digital audio signal Real-time detection of, when the detected sampling frequency of the digital audio signal does not match the preset theoretical sampling frequency, the detection result is output, so that the control software can timely adjust the sampling frequency of the digital audio signal or adjust the theory Sampling frequency. Therefore, the method provided by the embodiments of the present application can output the detection result when the sampling frequency of the digital audio signal does not match the pre-configured theoretical sampling frequency, thereby preventing the audio amplifier chip from being damaged when the sampling frequency of the software configuration is wrong effect.

Another embodiment of the present application also provides a method for detecting the sampling frequency of a digital audio signal, please refer to FIG. 2, the method includes the following steps:

S201. Acquire an initial reference clock signal and a sampling rate clock signal.

It should be noted that, unlike the above-mentioned embodiment, the embodiment of the present application does not require an initial reference clock signal to be acquired, that is to say, the initial reference clock signal acquired in step S201 of the embodiment of the present application may be relative to all The fast clock signal of the sampling rate clock signal, that is, the clock signal having a frequency greater than the frequency of the sampling rate clock signal, may not be synchronized with the sampling rate clock signal.

In fact, the initial reference clock signal obtained in this embodiment of the present application is usually a standard clock signal of an audio playback device integrated with the digital audio amplifier chip, and the frequency of the standard clock signal is relatively high, usually 1 MHz, which is much higher than The common sampling frequency range of digital audio signals (ie 8KHz to 48KHz), and the phase of the standard clock signal is fixed after the audio playback device is started, so it is usually not synchronized with the sampling rate clock signal of the digital audio signal .

S202. Perform frequency division processing on the initial reference clock signal to obtain a first reference clock signal.

The first reference clock signal is a reference clock signal obtained by dividing the initial reference clock signal and having a frequency less than the frequency of the sampling rate clock signal.

It should be noted that the frequency division processing of the initial reference clock signal is implemented by a frequency divider, that is, the initial reference clock signal is input to the frequency divider, and after the frequency divider processing, the first Reference clock signal.

The structure and working principle of the frequency divider belong to the prior art, and will not be repeated here.

It should be noted that the frequency division processing of the initial reference clock signal to obtain a reference clock signal whose frequency is less than the frequency of the sampling rate clock signal may be considered to be a frequency higher than a preset frequency (or a preset threshold) The reference clock signal is divided by frequency to obtain a reference clock signal whose frequency is a preset frequency (ie, the first reference clock signal), where the preset frequency is less than the frequency of the sampling rate clock signal.

Specifically, the initial reference clock signal with a frequency greater than 1 KHz may be divided to obtain a first reference clock signal with a frequency of 1 KHz. When the frequency of the input initial reference clock signal is less than or equal to 1 KHz, no frequency division processing is performed. The above step of determining whether the input initial reference clock signal is less than the preset frequency is actually realized automatically by the frequency divider, or in other words, when the frequency divider is working, the input signal will be automatically performed according to the preset frequency For screening, only the signal with a frequency greater than the preset frequency is subjected to frequency division processing.

It should be noted that the above-mentioned preset frequency may also be other values greater than 1 KHz or less than 1 KHz, as long as the preset frequency is lower than or equal to the lower limit of the sampling frequency range of the digital audio signal to be detected. For example, for a common digital audio signal, the sampling frequency is usually between 8KHz and 48KHz, so the preset sampling frequency may be less than or equal to 8KHz. However, in order to avoid fluctuations in the sampling frequency and more accurately calculate the number of pulses of the sampling rate clock signal in one cycle of the reference clock signal, it is recommended to set the preset frequency to the sampling frequency range The lower limit of is kept at a certain difference. For example, for a sampling frequency in the range of 8KHz to 48KHz, it is recommended to make the preset frequency less than or equal to 5KHz.

S203. Adjust the first reference clock signal to obtain a second reference clock signal.

The second reference clock signal is a reference clock signal synchronized with the sampling rate clock signal.

It should be noted that the synchronization of the second reference clock signal and the sampling rate clock signal means that when the second reference clock signal transitions from low level to high level, the sampling rate clock signal also changes from low level Jump to a high level, or each rising edge of the second reference clock signal simultaneously corresponds to a rising edge of the sampling rate clock signal.

It should be noted that steps S202 and S203 are not necessary for implementing the detection method provided by the present invention. As described in the previous embodiment provided by the present application, when the acquired initial reference clock signal is a slow clock signal with respect to the sampling rate clock signal and is synchronized with the sampling rate clock signal, steps S202 and S203 may not Execution, and the initial reference clock signal is directly used as the second reference clock signal. Of course, it is also possible to perform only one step in S202 or S203 without performing another step, and then use the processed reference clock signal as the second reference clock signal, as long as the acquired initial reference clock signal is a reference clock signal that meets the corresponding needs That's it.

By adding step S202 and step S203, the scope of application of the frequency detection method provided by the embodiment of the present application can be expanded, so that the reference clock signal with a sufficiently low frequency and synchronized with the sampling rate clock signal cannot be obtained in the embodiment of the present application It can also work normally when the real-time detection of the sampling frequency of digital audio signals is completed.

S204. Count the total pulses of the sampling rate clock signal in N cycles of the second reference clock signal.

The N is a preset positive integer.

Optionally, the N may be set to 32 or 64, or may be set to other positive integers.

S205. Divide the total pulse number by N to obtain the pulse number of the sampling rate clock signal within one cycle of the second reference clock signal.

Steps S204 and S205 can be understood as averaging the total number of pulses of the sampling rate clock signal in multiple cycles of the second reference clock signal, and using the obtained average value as the sampling rate clock signal in the first The number of pulses in one cycle of the reference clock signal.

It should be noted that step S204 and step S205 are optional. Steps S204 and S205 are performed because there is a certain error in the second reference clock signal, or there may be fluctuations, so the total number of pulses in multiple cycles is averaged to calculate the number of pulses in one cycle to Avoid misjudgment due to fluctuations in the second reference clock signal. If the second reference clock signal fluctuates to a low degree, does not generate or does not generate misjudgments frequently, or allows misjudgments to occur during the execution of the method, then step S204 and step S205 may not be performed and a sample rate clock signal may be directly counted The number of pulses in a cycle is sufficient, instead of averaging the total number of pulses in multiple cycles.

It should be noted that the calculation of the pulse number of the sampling rate clock signal within one cycle of the second reference clock signal can also be considered as the calculation of the sampling rate after the second reference clock signal has passed one cycle The number of cycles elapsed by the clock signal, that is, the calculated pulse number of the sampling rate clock signal within one cycle of the second reference clock signal can be considered as the frequency of the sampling rate clock signal and the second reference The ratio of the frequency of the clock signal.

S206. Calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the second reference clock signal.

It should be noted that the specific implementation of step S206 may be: multiplying the number of pulses by the frequency of the second reference clock signal, and the result obtained is the frequency of the sampling rate clock signal, that is, the number The sampling frequency of the audio signal (or the actual sampling frequency).

S207. Calculate the difference between the sampling frequency of the digital audio signal and the theoretical sampling frequency.

It should be noted that the theoretical sampling frequency is a sampling frequency obtained after the sampling rate decoding unit decodes the sampling rate code, and the sampling rate code is pre-configured by software through a register.

S208. Determine whether the absolute value of the difference is less than a preset threshold to obtain a judgment result.

Optionally, the threshold may be set to 50 Hz or other values, and the recommended value range is 0 Hz to 100 Hz.

S209. If the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.

The method provided by the embodiment of the present application, on the basis of real-time detection of the sampling frequency of the digital audio signal, extends the scope of application of the method provided by the embodiment of the present application by adding steps S202 and S203, and utilizes the statistical reference The method of sampling the total pulse number of the clock signal in multiple cycles of the clock signal and then averaging effectively avoids the misjudgment caused by the fluctuation of the reference clock signal.

Based on the method for detecting the sampling frequency of the digital audio signal, another embodiment of the present application provides a sampling device for the sampling frequency of a digital audio signal, please refer to FIG. 3, the device includes:

The calculating unit 301 is configured to acquire a reference clock signal and a sampling rate clock signal, and calculate the pulse number of the sampling rate clock signal within one cycle of the reference clock signal.

It should be noted that the frequency of the reference clock signal is less than the frequency of the sampling rate clock signal, and the reference clock signal and the sampling rate clock signal are synchronized.

The comparing unit 302 is used to calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal, and determine whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain Judgment result, if the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.

The working principle of the device provided by the embodiment of the present application is consistent with the frequency detection method provided by the above-mentioned first embodiment of the present application, and will not be repeated here.

In the detection device provided in the embodiment of the present application, the calculation unit 301 and the comparison unit 302 calculate the sampling rate of the digital audio signal according to the frequency of the reference clock signal, that is, the sampling frequency of the digital audio signal, and then the comparison unit 302 determines Whether the sampling frequency of the digital audio signal matches the theoretical sampling frequency pre-configured by the software, and outputs a judgment result when the two frequencies do not match, so that the software can adjust the sampling frequency of the digital audio signal in time, or modify the theoretical sampling frequency, Thereby, real-time detection of the sampling frequency of the digital audio signal is realized, and the damage of the audio amplification chip caused by the mismatch of the sampling frequency of the digital audio signal and the theoretical sampling frequency is effectively avoided.

An embodiment of the present application further provides a device for detecting the sampling frequency of a digital audio signal, please refer to FIG. 4, the device includes:

The frequency divider 401 is used to obtain the reference clock signal OSC, and divide the reference clock signal OSC to obtain a reference clock signal CLK_REF (denoted as a first reference signal) whose frequency is less than the frequency of the sampling rate clock signal.

The synchronization unit 402 is used to obtain the reference clock signal CLK_REF and the sampling rate clock signal WCK whose frequency output from the frequency divider 401 is less than the sampling rate clock signal, and adjust the reference clock signal CLK_REF to obtain a reference synchronized with the sampling rate clock signal WCK Clock signal CLK_REF_SYNC (denoted as synchronization reference signal).

The synchronization unit 402 can be implemented by flip-flops, such as T flip-flops and D flip-flops.

It should be noted that the frequency divider 401 and the synchronization unit 402 are optional. If the frequency of the reference clock signal OSC is less than the sampling rate clock signal WCK, and the reference clock signal OSC is a signal synchronized with the sampling rate clock signal WCK, the reference clock signal OSC can be directly input without being processed by the frequency divider 401 and the synchronization unit 402 Calculation unit 403.

The calculation unit 403 is configured to acquire the reference clock signal CLK_REF_SYNC and the sampling rate clock signal WCK output by the synchronization unit 402, and calculate the number of pulses of the sampling rate clock signal WCK within one cycle of the reference clock signal CLK_REF_SYNC.

The calculation unit 403 may use a counter with synchronization enabling and latching functions, and may also use a shift register and a device with latching functions.

Optionally, in another embodiment of the present application, the calculation unit 403 includes:

The counting unit is used to acquire the reference clock signal and the sampling rate clock signal, and calculate the pulse number of the sampling rate clock signal within one cycle of the reference clock signal.

The latch unit is used to store the calculated pulse number.

The counting unit is used to obtain a reference clock signal and a sampling rate clock signal, and to count the total number of pulses of the sampling rate clock signal in N cycles of the reference clock signal, where N is a preset positive integer.

The latch unit is used to store the calculated pulse number.

The counting and averaging unit is used to obtain the total pulse number and divide the total pulse number by N to obtain the pulse number of the sampling rate clock signal within one cycle of the reference clock signal WCK_AVG[5:0]( Recorded as the average number of pulses).

Among them, the counting and averaging unit is generally implemented by a shifted adder.

The comparing unit 404 is used to calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal, and determine whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain Judgment result, if the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.

The comparison unit 404 can basically be implemented by a comparator with a calculation function, or a combination of a calculator and an XOR gate array.

Optionally, in another embodiment of the present application, the working principle of the comparison unit 404 is to calculate the sampling frequency of the digital audio signal according to the frequency of the reference clock signal and the number of pulses input by the calculation unit 403, and then calculate the digital audio signal The difference between the sampling frequency and the theoretical sampling frequency, and comparing the absolute value of the difference with a preset threshold, if the absolute value of the difference is less than or equal to the threshold, the sampling frequency of the digital audio signal is determined Matches the theoretical frequency, otherwise, it is determined that the sampling frequency of the digital audio signal does not match the theoretical frequency, and if it is determined that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment is output result.

Optionally, in another embodiment of the present application, also referring to FIG. 4, the device further includes:

The sampling rate decoding unit 405 is used to decode the sampling rate code I2SSR[3:0] pre-configured by the software through the register to obtain the theoretical sampling frequency SR_CODE[5:0].

The sampling rate decoding unit 405 is connected to the comparison unit 404, and sends the decoded theoretical sampling frequency SR_CODE[5:0] to the comparison unit 404.

It should be pointed out that the sampling rate decoding unit may be a sampling decoder.

The device provided by the embodiment of the present application effectively expands the scope of application of the device provided by the embodiment of the present application on the basis of effectively detecting the sampling frequency of the digital audio signal in real time, by adding a frequency divider and a synchronization unit before the computing unit At the same time, a counting and averaging unit is provided in the calculation unit to average the total number of pulses in multiple cycles of the reference clock signal to obtain the number of pulses in one cycle of the reference clock signal, thereby avoiding Misjudgment caused by reference clock signal fluctuations.

The above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in this document, but should conform to the widest scope consistent with the principles and novel features disclosed in this document.

Claims

A method for detecting the sampling frequency of a digital audio signal, characterized in that it includes:

Obtain reference clock signal and sampling rate clock signal;

Calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal;

Calculating the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal;

Judging whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain a judgment result;

If the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.
The method according to claim 1, wherein the calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal further comprises:

Frequency-dividing the reference clock signal to obtain a reference clock signal whose frequency is less than the frequency of the sampling rate clock signal.
The method according to claim 1, wherein the calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal further comprises:

Adjusting the reference clock signal to obtain a reference clock signal synchronized with the sampling rate clock signal.
The method according to claim 1, wherein the calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal comprises:

Calculating the total pulse number of the sampling rate clock signal in N cycles of the reference clock signal, where N is a preset positive integer;

Divide the total number of pulses by N to obtain the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal.
The method according to claim 1, wherein the judging whether the sampling frequency of the digital audio signal matches a pre-configured theoretical sampling frequency to obtain a judgment result includes:

Calculating the difference between the sampling frequency of the digital audio signal and the theoretical sampling frequency;

Determine whether the absolute value of the difference is less than a preset threshold;

Wherein, if the absolute value of the difference is greater than or equal to the threshold, it is determined that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency; if the absolute value of the difference is less than the threshold, then It is determined that the sampling frequency of the digital audio signal matches the theoretical sampling frequency.
The method of claim 1, wherein the frequency of the reference clock signal is less than the frequency of the sampling rate clock signal and is synchronized with the sampling rate clock signal.
An apparatus for detecting the sampling frequency of a digital audio signal is characterized in that it includes:

A calculation unit, configured to acquire a reference clock signal and a sampling rate clock signal, and calculate the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal;

The comparison unit is used to calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal, and determine whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain a judgment As a result, if the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.
The apparatus according to claim 7, wherein the calculation unit comprises:

The counting unit is used to obtain the reference clock signal and the sampling rate clock signal, and calculate the pulse number of the sampling rate clock signal within one cycle of the reference clock signal;

The latch unit is used to store the calculated pulse number.
The apparatus according to claim 7, wherein the calculation unit comprises:

The counting unit is used to obtain a reference clock signal and a sampling rate clock signal, and calculate the total number of pulses of the sampling rate clock signal in N cycles of the reference clock signal, where N is a preset positive integer;

Latch unit, used to save the calculated total pulse number;

A counting and averaging unit is used to obtain the total number of pulses, and divide the total number of pulses by N to obtain the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal.
The device according to claim 7, further comprising:

A frequency divider, configured to obtain the reference clock signal and divide the reference clock signal to obtain a reference clock signal whose frequency is less than the frequency of the sampling rate clock signal;

Wherein, the reference clock signal acquired by the calculation unit is: a reference clock signal whose frequency output by the frequency divider is less than the frequency of the sampling rate clock signal.
The device according to claim 7, further comprising:

A synchronization unit, configured to obtain a reference clock signal and a sampling rate clock signal, and adjust the reference clock signal to obtain a reference clock signal synchronized with the sampling rate clock signal;

Wherein, the reference clock signal acquired by the calculation unit is: a reference clock signal output by the synchronization unit and synchronized with the sampling rate clock signal.
The device according to claim 7, further comprising:

The sampling rate decoding unit is used for decoding the pre-configured sampling rate code to obtain the theoretical sampling frequency.
The apparatus according to claim 7, wherein the frequency of the reference clock signal is less than the frequency of the sampling rate clock signal and is synchronized with the sampling rate clock signal.