CN109817230A - A kind of the timing regeneration shaping methods and its device of digital audio and video signals - Google Patents
A kind of the timing regeneration shaping methods and its device of digital audio and video signals Download PDFInfo
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Abstract
A kind of the timing regeneration shaping methods and its device of digital audio and video signals, it includes: acquisition digital audio and video signals which, which regenerates shaping methods, and the response frequency of MCLK signal is determined according to the frequecy characteristic of the first clock signal in digital audio and video signals；Repeatedly frequency dividing is carried out to MCLK signal and obtains BCK signal and LRCK signal；MCLK signal, BCK signal, LRCK signal and DATA signal are synchronized into matching, obtains and exports new digital audio and video signals.Due to obtaining BCK signal and LRCK signal by the frequency dividing mode to MCLK signal, so that the time sequence precision of two signals is promoted, not only have modified the bad timing in digital audio and video signals, also improve its anti-interference ability in complicated use environment, finally ensure integrity and stability of the digital audio and video signals in transmission process, to with high fidelity, truly restore each frame quantitative information and each sound details in digital audio and video signals, and then significantly promote the playback expressive force of HiFi grades of HD Audio decoders.
Description
Technical field
The present invention relates to the digital audio decoding technical fields of HiFi rank high-fidelity, and in particular to a kind of digital audio letter
Number timing regeneration shaping methods and its device.
Background technique
In HiFi (full name High-Fidelity) rank high-fidelity digital audio decoding techniques research field, for number
Clock and timing synchronization accuracy of the digital audio and video signals in transmission demodulating process in word audio decoder has high want
It asks, this is to guarantee that digital audio accurately decodes the accurate prerequisite for resetting high-fidelity reduction.It is any in transmission demodulating process
One flaw can all seriously affect audio signal it is accurate decoding and reduction, such as signal source itself (be related in this day and age or
The equipment that can be used as digital audio source is many, such as smart phone, PC, tablet computer etc.) and be transmitted across
Clock jitter problems caused by the interference introduced in journey, the chaotic even timing step-out problem of timing, traditional digital audio weight
The integrality for depending on the physical characteristic of existing special chip substantially to guarantee signal is put, for example, the biography of Digital Audio Transmission
System method is substantially and is transmitted using I2S traffic spike is modulated into SPDIF audio signal, then solves aligning by SPDIF
Slice weight newly demodulates the I2S digital audio data stream of standard, by it is introduced in secondary coding-decoding and SPDIF transmission process when
Sequence shake and loss are greatly, strictly speaking to have had disengaged from HiFi grades of HD Audio decoders and strictly wanted to signal quality
It asks.
In actual application, DA chip is very high to the integrality of signal source and stability requirement, and required
The time sequence precision of digital audio and video signals is higher, and reproducibility is higher.It can be met when using special digital audio signal processor part
To some problems, first is that use cost is excessively high, second is that the versatility of circuit is very low, it is caused generally to lack cost performance, very
Technical solution to the reduction degree to digital audio and video signals not as good as the application is less convenient for generalization application.
Summary of the invention
The present invention solves the technical problem of the time sequence precisions for how promoting digital audio and video signals to ensure digital sound
Integrity and stability in frequency signals transmission.In order to solve the above technical problems, the application provides a kind of digital audio letter
Number timing regeneration shaping methods and its device.
According in a first aspect, the timing for providing a kind of digital audio and video signals in a kind of embodiment regenerates shaping methods, including
Following steps:
Digital audio and video signals are obtained, the digital audio and video signals include the first clock signal and DATA signal；
The response frequency of a MCLK signal is determined according to the frequecy characteristic of first clock signal；
The MCLK signal is repeatedly divided, a BCK signal and a LRCK signal are obtained；
The MCLK signal, the BCK signal, the LRCK signal and the DATA signal are synchronized into matching, obtained
To new digital audio and video signals；
Export the new digital audio and video signals.
The digital audio and video signals are I2S audio signal or SPDIF audio signal；When the digital audio and video signals are
When SPDIF audio signal, then demodulation obtain the I2S audio signal, by the I2S audio signal frame clock signal or
Bit clock signal is as first clock signal.
The frequecy characteristic of first clock signal determines the response frequency of a MCLK signal, comprising: according to described first
The frequency of clock signal judges the predeterminated frequency range where first clock signal, is determined by the predeterminated frequency range
The response frequency of the MCLK signal is 22.5792MHz, 24.576MHz, 45.1584MHz or 49.152MHz.
The MCLK signal is repeatedly divided, obtains a BCK signal and a LRCK signal, comprising: to the MCLK
Signal carries out frequency dividing three times and obtains the BCK signal, carries out nine frequency dividings to the MCLK signal and obtains the LRCK signal.
The MCLK signal, the BCK signal, the LRCK signal and the DATA signal are synchronized into matching, obtained
To new digital audio and video signals, comprising: to the MCLK signal, the BCK signal, the LRCK signal and the DATA signal
Waveform carries out passive shaping, respectively obtains corresponding reshaping signal；Each reshaping signal is synchronized and is matched
To the new digital audio and video signals.
According to second aspect, a kind of timing regeneration apparatus for shaping of digital audio and video signals is provided in a kind of embodiment, it is special
Sign is, comprising:
Receiving unit, for receiving digital audio and video signals, the digital audio and video signals include the first clock signal and DATA
Signal；
Main control unit is connect with the receiving unit, for determining one according to the frequecy characteristic of first clock signal
The response frequency of MCLK signal；
Phase locking unit is connect with the receiving unit and the main control unit, described in determining in the main control unit
An oscillator is locked when the response frequency of MCLK signal to export the MCLK signal according to the response frequency；
Timing regeneration unit is connect with the phase locking unit and the main control unit, for determining in the main control unit
When the phase locking unit exports the MCLK signal, the MCLK signal is repeatedly divided, a BCK signal and one are obtained
LRCK signal；
Shaping unit is connect with the timing regeneration unit, for the MCLK signal, the BCK signal, described
The waveform of LRCK signal and the DATA signal carries out passive shaping, and each signal after shaping is synchronized matching and obtains institute
State new digital audio and video signals.
The main control unit controls the receiving unit selection and receives I2S audio signal or SPDIF audio signal；Work as institute
When to state digital audio and video signals be SPDIF audio signal, then the receiving unit demodulates to obtain the I2S audio signal, will be described
Frame clock signal or bit clock signal in I2S audio signal are using as first clock signal.
The main control unit judges default where first clock signal according to the frequency of first clock signal
Frequency range, by the predeterminated frequency range determine the MCLK signal response frequency be 22.5792MHz,
24.576MHz, 45.1584MHz or 49.152MHz；
The phase locking unit includes multiple oscillators, when the main control unit determines the response frequency of the MCLK signal
It locks one of oscillator and generates crystal oscillation signal corresponding with the response frequency, it is defeated to be carried out as the MCLK signal
Out.
The timing regeneration unit receives the MCLK signal, is divided three times described in obtaining to MCLK signal progress
BCK signal carries out nine frequency dividings to the MCLK signal and obtains the LRCK signal.
The shaping unit includes the passive shaping channel of multichannel；Passive shaping channel described in each road respectively believes the MCLK
Number, the waveform of the BCK signal, the LRCK signal and the DATA signal carry out passive shaping, by the letter after each road shaping
Number synchronizing matching obtains the new digital audio and video signals, and exports to the new digital audio and video signals.
The beneficial effect of the application is:
The timing regeneration shaping methods and its device of a kind of digital audio and video signals according to above-described embodiment, timing regeneration
Shaping methods include: acquisition digital audio and video signals, are determined according to the frequecy characteristic of the first clock signal in digital audio and video signals
The response frequency of MCLK signal；MCLK signal is repeatedly divided, BCK signal and LRCK signal are obtained；By MCLK signal,
BCK signal, LRCK signal and DATA signal synchronize matching, obtain and export new digital audio and video signals.In a first aspect, due to
The response frequency of MCLK signal is determined according to the frequency of the first clock signal, so that the time sequence precision of MCLK signal obtains greatly
It is promoted, makes it possible to correct the bad timing in digital audio and video signals based on the MCLK signal；Second aspect, due to passing through
BCK signal and LRCK signal are obtained to the frequency dividing mode of MCLK signal, so that the time sequence precision of BCK signal and LRCK signal is able to
It is promoted, not only has modified the bad timing in digital audio and video signals, also improve digital audio and video signals in complicated use environment
Anti-interference ability, finally ensure integrity and stability of the digital audio and video signals in transmission process, thus with high fidelity, very
The each frame quantitative information and each sound details in digital audio and video signals are restored on the spot, and then significantly promote HIFI
The playback expressive force of grade HD Audio decoder；The third aspect, the claimed timing regeneration apparatus for shaping of the application include
Receiving unit, main control unit, phase locking unit, timing regeneration unit and shaping unit, each unit use general circuit structure
Or integrated chip, so that the integrated circuit structure of device is simplified, it can either be by the quality-improving of digital audio and video signals to specially
With the performance class of digital audio signal processor part, additionally it is possible to application cost is reduced, so that the device can completely be applied to
In the digital audio demodulation circuit of all kinds of different-formats；Fourth aspect, take full advantage of the phase locked looped function of phase locking unit into
Row clock frequency precisely follows, and the synchronizing characteristics of signal sequence is improved using timing regeneration unit, thus by digital audio
Signal sequence tracking, timing regeneration reduce digital audio and video signals itself and caused timing jitter in transmission process, keep away
Digital audio and video signals are exempted from because of the shake or step-out phenomenon caused by the defect itself and transmission loss of signal source or interference, greatly
Ground reduces the decoded bit error rate of subsequent decoding chip, and frequency stabilization precision can be allowed to maintain 1ps, and stability range reaches 25ppm extremely
1600ppm further promotes the integrality of audio signal, to comprehensively truly restore digital audio and video signals to the maximum extent
Essence.5th aspect, timing regeneration apparatus for shaping can be adapted for the audio signal input situation of substandard PCM format,
It is readily applicable to the audio signal input situation of high code rate DSD format, while also can be reversed applied to ADC analog-to-digital conversion
Time sequence precision is improved on output circuit, can be applied to the processing occasion of a variety of digital audio and video signals.
Detailed description of the invention
Fig. 1 is the overall structure figure that timing regenerates apparatus for shaping；
Fig. 2 is a kind of circuit diagram of the timing regeneration apparatus for shaping in embodiment；
Fig. 3 is the circuit diagram of receiving unit；
Fig. 4 is the circuit diagram of phase locking unit；
Fig. 5 is the circuit diagram of timing regeneration unit；
Fig. 6 is the circuit diagram of shaping unit；
Fig. 7 is the flow chart that timing regenerates shaping methods in a kind of embodiment；
Fig. 8 is the flow chart that the response frequency of MCLK signal is determined in a kind of embodiment；
Fig. 9 is that simultaneously match obtains the flow chart of new digital audio and video signals in a kind of embodiment.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.Wherein different embodiments
Middle similar component uses associated similar element numbers.In the following embodiments, many datail descriptions be in order to
The application is better understood.However, those skilled in the art can recognize without lifting an eyebrow, part of feature
It is dispensed, or can be substituted by other elements, material, method in varied situations.In some cases, this Shen
Please it is relevant it is some operation there is no in the description show or describe, this is the core in order to avoid the application by mistake
More descriptions are flooded, and to those skilled in the art, these relevant operations, which are described in detail, not to be necessary, they
Relevant operation can be completely understood according to the general technology knowledge of description and this field in specification.
It is formed respectively in addition, feature described in this description, operation or feature can combine in any suitable way
Kind embodiment.Meanwhile each step in method description or movement can also can be aobvious and easy according to those skilled in the art institute
The mode carry out sequence exchange or adjustment seen.Therefore, the various sequences in the description and the appended drawings are intended merely to clearly describe a certain
A embodiment is not meant to be necessary sequence, and wherein some sequentially must comply with unless otherwise indicated.
It is herein component institute serialization number itself, such as " first ", " second " etc., is only used for distinguishing described object,
Without any sequence or art-recognized meanings.And " connection ", " connection " described in the application, unless otherwise instructed, include directly and
It is indirectly connected with (connection).
For the technical solution that the application is expressly understood, some technical terms will be illustrated here.
I2S audio signal refers to the audio digital signals using I2S (Inter-IC Sound Bus) bus standard, this
In I2S bus standard be PHILIPS Co. between digital audio-frequency apparatus audio data transmission and formulate a kind of bus mark
Standard had both defined hardware interface specification, alsied specify the format of audio digital signals.I2S audio signal generally includes four masters
Want signal, respectively MCLK signal (i.e. master clock signal or clock signal of system), SCLK signal (i.e. bit clock signal or serial
Clock signal), LRCK signal (i.e. frame clock signal).Wherein, MCLK signal is the reference signal of system, in order to make energy between system
It is enough preferably synchronous, MCLK signal frequency=256 times or 384 sampling frequencies；LRCK signal is used for the number of switching right and left sound channel
According to, LRCK is that " 1 " indicates that is transmitted is the data of L channel, then indicate that is transmitted is the data of right channel for " 0 ",
Frequency=sample frequency of usual LRCK signal；Each pulse of BCK signal corresponds to each data of digital audio, usually
Frequency=2 of BCK signal × sample frequency × sampling resolution；DATA signal is serial data, usually uses complement of two's two's complement table
The audio data shown.
SPDIF audio signal refers to using SPDIF (Sony/Philips Digital Interface) audio interface mark
Quasi- audio digital signals, S/PDIF audio interface standard are customized by IEC61937 standard, are often used to transmit compressed
Audio signal, that is to say, that SPDIF audio signal is considered a kind of compression modulated signal.SPDIF audio signal can
To transmit a plurality of types of signals, such as PCM, AC-3, DTS or channel digital audio signal.SPDIF digital signal can be with together
Shaft cable transmits, and can also be transmitted with optical fiber.SPDIF audio signal is divided into output (SPDIF OUT) and input (SPDIF
IN) two kinds, most of sound card chip can support SPDIF OUT at present.
Phaselocked loop (PLL), refers to the loop of locking phase, is a kind of typical feedback control circuit, utilizes external input
Reference signal control loop internal oscillation signal frequency and phase, realize output signal frequency to frequency input signal from
Motion tracking is generally used for Closed loop track circuit.Phaselocked loop mainly has VCO (voltage controlled oscillator) and PLL IC (the integrated electricity of phaselocked loop
Road), voltage controlled oscillator provides a signal, and a part, which is used as, to be exported, and another part is generated originally with PLL IC by frequency dividing
Vibration signal makees phase bit comparison, in order to which keep frequency is constant, it is desirable to and phase difference does not change, if dephased variation,
Then the voltage of the voltage output end of PLL IC changes, and removes control VCO, until phase difference recovery, achievees the purpose that locking phase.Institute
It is used to assist PLL with common second-order PLL (2nd PLL) to reduce the shake of master clock, it is consistent to reach crystal oscillator frequency
Purpose.
Embodiment one,
Referring to FIG. 1, the application provides a kind of timing regeneration apparatus for shaping of digital audio and video signals comprising receiving unit
11, main control unit 12, phase locking unit 13, timing regeneration unit 14 and shaping unit 15, illustrate separately below.
Receiving unit 11 for receiving digital audio and video signals, digital audio and video signals here should include the first clock signal and
DATA signal, then receiving unit 11 received digital audio and video signals can be parsed with obtain the first clock signal and
DATA signal, and the two signals are exported.
Main control unit 12 is connect with receiving unit 11, the frequency of the first clock signal for being exported according to receiving unit 11
Feature determines the response frequency of a MCLK signal.
Phase locking unit 13 is connect with receiving unit 11 and main control unit 12, for determining a MCLK signal in main control unit 12
Response frequency when lock an oscillator to export the MCLK signal according to the response frequency.
Timing regeneration unit 14 is connect with phase locking unit 13 and main control unit 12, for determining locking phase list in main control unit 12
When member 13 exports MCLK signal, MCLK signal is repeatedly divided, a BCK signal and a LRCK signal are obtained.
Shaping unit 15 is connect with timing regeneration unit 14, for MCLK signal, BCK signal, LRCK signal and DATA
The waveform of signal carries out passive shaping, respectively obtains corresponding reshaping signal；Also, the shaping unit 15 is also used to will be each
A reshaping signal synchronizes matching and obtains new digital audio and video signals.
In the present embodiment, main control unit 12 controls and receives the selection of unit 11 and receives I2S audio signal or SPDIF audio
Signal.Specifically, when received digital audio and video signals are SPDIF audio signal, then the demodulation of receiving unit 11 obtains I2S audio
Signal selects frame clock signal in I2S audio signal or bit clock signal as the first clock signal.
It should be noted that it is unmodulated I2S audio signal that 11 possibility of receiving unit is received, it is also possible to received to be
SPDIF audio signal after modulation then needs to demodulate it to obtain I2S audio signal if it is SPDIF audio signal.This
Outside, it is preferable that when I2S audio signal is PCM format, then receiving unit 11 parses the letter of the frame clock in I2S audio signal
Number using as the first clock signal；When I2S audio signal is DSD format, then receiving unit 11 parses in I2S audio signal
Bit clock signal using as the first clock signal.It will be understood by those of skill in the art that either frame clock signal is still
Bit clock signal is all to determine and generate new MCLK signal as reference signal, at this as the first clock signal
On the basis of MCLK signal frequency dividing obtain new LRCK signal and BCK signal, thus with new MCLK signal, LRCK signal and
BCK signal replaces master clock signal, frame clock signal and bit clock signal in former digital audio and video signals respectively, recombines one
Fully synchronized regenerated new I2S audio signal, i.e. simultaneously match obtain new digital audio and video signals.
In one embodiment, Fig. 2-Fig. 6 is please referred to, it will be with the frame clock signal in received digital audio and video signals
(LRCK) former as the particular circuit configurations and work that this timing regeneration apparatus for shaping for the first clock signal, is described in detail
Reason.
It can be seen that Fig. 2, receiving unit 11 can receive I2S audio signal and SPDIF sound by the port I2S, the port SPDIF simultaneously
Frequency signal, main control unit 12 switch to audio signal all the way therein by I2C-1 port controlling receiving unit 11, so that receiving
Unit 11 demodulates the road audio signal to obtain DATA signal, MCLK signal, BCK signal, LRCK signal, and passes through phase
The port answered is exported, and MCLK signal therein and BCK signal are given it up in the present embodiment, and LRCK therein is believed
It number is referred to as the first clock signal to regenerate MCLK signal, BCK signal and LRCK signal.
In one embodiment, see that Fig. 3, receiving unit 11 include signal switching and demodulator circuit, main control unit 12 is logical
Cross the port I2C-1 send selection signal come control signal switching and parser circuitry switch over, select I2S audio signal and
One in SPDIF audio signal is demodulated, to obtain the DATA signal and LRCK signal (i.e. frame clock letter in signal
Number), and give it up to the obtained master clock signal of demodulation and bit clock signal.So, signal switching and demodulator circuit can
To export the DATA signal and LRCK signal that demodulation obtains respectively by the port DATA, the port LRCK.It should be noted that this reality
The signal switching and demodulator circuit applied in example can use the prior art, such as ADG413 chip, therefore no longer carry out here detailed
It describes in detail bright.
Referring to fig. 2, main control unit 12 by the port LRCK-IN from receiving unit 11 obtain the first clock signal (here for
LRCK signal), main control unit 12 judges the predeterminated frequency range of the first clock signal according to the frequency of the first clock signal later,
By predeterminated frequency range determine a MCLK signal response frequency be 22.5792MHz, 24.576MHz, 45.1584MHz or
49.152MHz。
Referring to fig. 2, phase locking unit 13 includes multiple oscillators, is indicated respectively with Y1, Y2, Y3, Y4, crystal oscillator frequency is respectively
22.5792MHz, 24.576MHz, 45.1584MHz or 49.152MHz, the port EN1, the port EN2, the end EN3 of main control unit 12
Mouth, the port EN4 can be attached with those oscillators respectively, main when main control unit 12 determines the response frequency of MCLK signal
It controls unit 12 and issues enable signal to start corresponding oscillator, so that phase locking unit 13 locks one of them by corresponding ports
Oscillator generates crystal oscillation signal corresponding with the response frequency, to be exported as the MCLK signal regenerated.It needs
It is noted that the oscillator in the present embodiment can use voltage controlled oscillator, other types of oscillator can also be used, this
In with no restrictions.
Referring to fig. 2 and Fig. 5, phase locking unit 13 are defeated by the MCLK signal that the port MCLK-OUT generates locked oscillator
Out to the port MCLK-IN of timing regeneration unit 14, main control unit 12 sends fractional frequency signal to timing by the port I2C-2 and regenerates
Unit 14 is to select part-frequency point.So, after timing regeneration unit 14 receives MCLK signal and fractional frequency signal, to MCLK signal
Carry out three times frequency dividing obtain a BCK signal, to MCLK signal carry out nine frequency dividings obtain a LRCK signal, wherein LRCK signal,
BCK signal passes through the port LRCK respectively and the port BCK is exported to shaping unit 15, MCLK signal by a filter resistance R into
Row output, and LRCK signal also passes through the port LRCK-II and feeds back to phase locking unit 13.It should be noted that in the present embodiment
Timing regeneration unit 14 can use SR5340 chip, can also use other integrated circuits for having division function, here
With no restrictions, since division function belongs to the prior art, also the working principle of timing regeneration unit is not carried out specifically here
It is bright.
Further, phase locking unit 13 further includes phase discriminator (not illustrating in figure), which will pass through the port LRCK-I
First clock signal of input passes through triggering compared with the LRCK signal fed back by the port LRCK-II carries out frequency
Pulse control voltage is to locked oscillator making frequency adjustment, so that the frequency and control of the crystal oscillation signal that the oscillator generates
The response frequency that unit 12 determines is consistent.
It should be noted that phase locking unit 13 is inputted by oscillator, phase discriminator, by the port LRCK-I in the present embodiment
The first clock signal and the LRCK signal that is fed back by the port LRCK-II constitute a phaselocked loop (PLL), so
The crystal oscillator frequency of oscillator is allowed accurately to be locked in working frequency range.
Further, see that Fig. 2, main control unit 12 include the port MUTE, the port MUTE is for mute with external equipment
Control terminal connection；So, main control unit 12 passes through MUTE port controlling external equipment in the response frequency for determining MCLK signal
It is mute in preset time (such as 0.5s), to avoid MCLK signal caused sonic boom situation during step-out occurs.Specifically
Ground, main control unit 12 control during phase locking unit 13 locks one of oscillator, have one and of short duration relock
The time of frequency causes of short duration MCLK step-out phenomenon, within this time often so as to cause timing disorder or even sonic boom
Situation occurs, then control unit 12 can pass through the end MUTE before control phase locking unit 13 carries out the lock operation of oscillator
Simulation scale-up circuit mute control after mouthful output mute control signal to decoded output simultaneously enables its starting, during mute
The crystal oscillator frequency locking and frequency dividing work for completing oscillator, then turn off it is mute, usually this mute process maintain 0.5 second i.e.
It can.
In one embodiment, see that Fig. 4, the phase discriminator of phase locking unit 13 (can also be used using 74HC4046 chip
SR5340 chip, LMK00804 chip), the port LRCK-I, the port LRCK-II are separately connected by two pins to connect respectively
The first clock signal of input and the LRCK signal of feedback are received, frequency comparison result is exported by resistance R2 to electronic switch；Vibration
Swing device Y1-Y4 and be all made of voltage controlled oscillator chip, the port OE of each oscillator respectively with the port EN1-EN4 of main control unit 12
Connection, and the port VO of each oscillator is connect with the output port of electronic switch respectively, multiple input ports of electronic switch
It is connect respectively with the port OE of each oscillator.In this way, foring a phase lock circuitry, frequency is constantly compared knot by phase discriminator
Fruit (such as difference on the frequency) is transmitted to electronic switch, so that electronic switch carries out the oscillator enabled according to frequency comparison result
Frequency adjustment, to work in correspondingly frequency range with allowing enabled oscillator stabilization.
It should be noted that phase locking unit 14 can also use dedicated voltage-controlled phase-locked loop chip, and can be according to production
The voltage controlled oscillator (VCXO) and phase-locked loop chip of different accuracy class are selected in the required precision of product, so that device is in application process
In it is more flexible and convenient.
Referring to Fig. 6, shaping unit 15 includes the passive shaping channel of multichannel, and each passive shaping channel in road respectively believes MCLK
Number, the waveform of BCK signal, LRCK signal and DATA signal carry out passive shaping, respectively obtain corresponding reshaping signal, from
And each reshaping signal reshaping signal is synchronized into matching and obtains new digital audio and video signals, and then realizes shaping unit 15 to new
Digital audio and video signals are exported.Wherein, the passive shaping channel of MCLK signal can be made of filter resistance R, DATA signal,
BCK signal, LRCK signal respective passive shaping channel can be made of ultrahigh speed switching diode and the resistance being arranged in parallel,
Each passive shaping channel is all made of passive device, can avoid the shadow of the factors such as background noise possessed by active device itself
It rings, can also effectively eliminate the wave noise in each road signal, play preferable shaping effect and can ensure the identification of signal
Degree.Shaping unit 14 is automatically composed to obtain splendid in synchronism output MCLK signal, BCK signal, LRCK signal and DATA signal
The new digital audio and video signals of synchronizing characteristics, new digital audio and video signals obtained in this implementation be still MCLK signal, BCK signal,
The I2S data flow that LRCK signal and DATA signal are constituted, only the I2S data flow has high-precision, high stability, high-fidelity
Property, low noise and complete feature, handled conducive to the audio decoder of subsequent decoding signal, each true for restoring audio signal
Details.
Further, see Fig. 6, it further includes D/A converter which, which regenerates apparatus for shaping, the D/A converter and shaping unit
15 connections, the new digital audio and video signals that shaping unit 15 can be exported are decoded to obtain analog audio signal, then just
Analog signal transmission can be carried out by audio cable, or analog audio signal broadcasting is carried out by audio playing device.Tool
Body, D/A converter is using conventional analog-digital chip, here with no restrictions.
Further, timing regeneration apparatus for shaping further includes control panel, which connect with main control unit 12,
It realizes the functions such as input switching, the frequency dividing frequency point setting of digital audio and video signals, reaches the using effect of human-computer interaction.
Receiving unit 11, main control unit 12 disclosed in the present embodiment, phase locking unit 13, timing regeneration unit 14 and shaping
Unit 15 can realize respective function using existing processing chip, and wherein main control unit 1212 is to other several units
Control action is played, existing control means can be used, can not also be limited here using the following control means occurred
System.
When main control unit 12 is using existing control means, detailed process be can be described as: the control of main control unit 12 connects
It receives the switching of unit 11 and obtains digital audio and video signals all the way, so that the railway digital audio signal is demodulated to obtain by receiving unit 11
DATA signal and the first clock signal；Main control unit 12 directly determines new MCLK signal according to the frequency of the first clock signal
Response frequency, so that corresponding oscillator is started in enabled phase locking unit 13；Main control unit 12 is triggered by fractional frequency signal
Timing regeneration unit 14 carries out scaling down processing, but also phase locking unit 14 passes through the crystal oscillator frequency of phase lock loop locks oscillator；It is whole
Shape unit 15 receives MCLK signal, BCK signal, LRCK signal and DATA signal automatically, so that shaping, simultaneously match are newly counted
Word audio signal.This control means are fairly simple, and most of function is by available circuit structure or existing processing chip automatic
It realizes, the control logic that main control unit is supported only does simple judgement and the output of unit control signal, it is only necessary to which simple control is provided
Program, does not need technical staff and pays creative labor to can be realized as.
Embodiment two,
Referring to FIG. 7, the present embodiment discloses a kind of timing regeneration shaping methods of digital audio and video signals comprising step
S210-S250 illustrates separately below.
Step S210, obtains digital audio and video signals, which includes the first clock signal and DATA signal.
In one embodiment, the digital audio and video signals of acquisition are I2S audio signal or SPDIF audio signal；Work as number
When audio signal is SPDIF audio signal, then demodulation obtains I2S audio signal, so that the frame clock in I2S audio signal be believed
Number or bit clock signal as the first clock signal.
In one embodiment, see that Fig. 2, main control unit 12 send selection signal by the port I2C-1 to control and receive
One in Unit selection I2S audio signal and SPDIF audio signal is demodulated, thus obtain the DATA signal in signal,
MCLK signal, BCK signal, LRCK signal.When control unit 12 judges I2S audio signal or SPDIF audio signal for PCM lattice
When formula, then LRCK signal (i.e. frame clock signal) therein is regard as the first clock signal, and synchronize with DATA signal defeated
Out, and by MCLK signal, BCK signal it gives it up.
In another specific embodiment, when control unit 12 judges I2S audio signal or SPDIF audio signal for DSD
When format, then BCK signal (i.e. bit clock signal) therein is used as the first clock signal, and synchronizes with DATA signal defeated
Out, and by MCLK signal, LRCK signal it gives it up.
Step S220 determines the response frequency of a MCLK signal according to the frequecy characteristic of the first clock signal.Implement one
In example, Fig. 8 is seen, step S220 may include step S221-S222, be respectively described below.
Step S221 judges the predeterminated frequency range where the first clock signal according to the frequency of the first clock signal；
Step S222, by predeterminated frequency range determine MCLK signal response frequency be 22.5792MHZ,
24.576MHZ, 45.1584MHZ or 49.152MHZ.
In one embodiment, main control unit 12 judges the frequency of the first clock signal at (44.1 ± 44.1*10%)
When within the scope of the predeterminated frequency of KHz, it is determined that the response frequency of MCLK signal is 22.5792MHz；Judge the first clock signal
When frequency is within the scope of the predeterminated frequency of (192 ± 192*10%) KHz, it is determined that the response frequency of MCLK signal is
24.576MHz；When judging that the frequency of the first clock signal is within the scope of the predeterminated frequency of (705 ± 705*10%) KHz, it is determined that
The response frequency of MCLK signal is 45.1584MHz；Judge the frequency of the first clock signal in the pre- of (768 ± 768*10%) KHz
If when in frequency range, it is determined that the response frequency of MCLK signal is 49.152MHz.
In one embodiment, see that Fig. 2, main control unit 12 pass through corresponding end in the response frequency for determining MCLK signal
Mouth issues enable signal to start corresponding oscillator, so that phase locking unit 13 locks one of oscillator to generate and the sound
The corresponding crystal oscillation signal of frequency is answered, to be exported as the MCLK signal regenerated.
Step S230 repeatedly divides the MCLK signal generated in step S220, obtains a BCK signal and a LRCK
Signal.In one embodiment, frequency dividing three times is carried out to MCLK signal and obtains new BCK signal, nine times points are carried out to MCLK signal
Frequency obtains new LRCK signal.
In one embodiment, see Fig. 2, when the frequency of the first clock signal is in 44.1KHz and neighbouring range,
Then main control unit 12 determines that the response frequency of MCLK signal is 22.5792MHz, exports high level by the port EN1, passes through simultaneously
The port EN2, the port EN3, the port EN4 export low level, only start oscillator Y1, so that oscillator Y1 work is in 22.5792MHz
Frequency range.Meanwhile main control unit 12 sends frequency dividing instruction to timing regeneration unit 14 by the port I2C-2, control sequential regeneration is single
Member 14 is started in a manner of 512fs, and it is for 2.8224MHz and defeated by the progress of the port BCK to obtain the frequency of BCK signal for frequency dividing three times
Out, nine frequency dividings obtain the frequency of LRCK signal as 44.1KHz and are exported by the port LRCK.In addition, timing regeneration is single
The LRCK signal of frequency 44.1KHz is also fed back to the port LRCK-II of phase locking unit 13 by member 14 by the port LRCK-II.
In another embodiment, Fig. 2 is seen, when the frequency of the first clock signal is in 768KHz and neighbouring range
When, then main control unit 12 determines that the response frequency of MCLK signal is 49.152MHz, exports high level by the port EN4, leads to simultaneously
The port EN1, the port EN2, the port EN3 output low level are crossed, oscillator Y4 is only started, so that oscillator Y4 work is in 49.152 frequencies
Section.Meanwhile main control unit 12 sends frequency dividing instruction to timing regeneration unit 14, control sequential regeneration unit by the port I2C-2
14 are started in a manner of 64fs, and frequency dividing obtains the frequency of BCK signal as 12.288MHz and exported by the port BCK, nine three times
It is secondary to divide the frequency for obtaining LRCK signal as 768KHz and exported by the port LRCK.In addition, timing regeneration unit 14 is also
The LRCK signal of frequency 768KHz is fed back to the port LRCK-II of phase locking unit 13 by the port LRCK-II.
In another embodiment, however, it is determined that the BCK signal in I2S audio signal as the first clock signal, then, when
When main control unit 12 knows that the frequency of the first clock signal is in 2.8224MHz and nearby sphere, then main control unit 12 determines
The response frequency of MCLK signal is 22.5792MHz, starts oscillator Y1 to work in 22.5792MHz frequency range.Meanwhile master control list
First 12 control sequential regeneration units 14 by the frequency that frequency dividing three times obtains BCK signal be 2.8224MHz and by the port BCK into
Row output, the frequency that nine frequency dividings obtain LRCK signal are 44.1KHz and are exported by the port LRCK.In addition, timing is again
The BCK signal of frequency 2.8224MHz can also be fed back to phase locking unit 13 by raw unit 14, enable phase locking unit 13 by
The BCK signal of input and the BCK signal fed back realize phase locked looped function, reaches so as to adjust the crystal oscillator frequency of oscillator Y1
To response frequency 22.5792MHz.
In addition, seeing Fig. 2, main control unit 12 can also pass through MUTE port controlling in the response frequency for determining MCLK signal
External equipment is mute in preset time (such as 0.5s), to avoid MCLK signal caused sonic boom feelings during step-out occur
Shape.
Step S240 carries out MCLK signal newly generated in step S230, BCK signal, LRCK signal and DATA signal
Simultaneously match obtains new digital audio and video signals.In one embodiment, see that Fig. 9, step S240 may include step S241-S242, point
It is not described as follows.
Step S241 carries out passive shaping to the waveform of MCLK signal, BCK signal, LRCK signal and DATA signal, respectively
Obtain corresponding reshaping signal.
Each reshaping signal is synchronized matching and obtains new digital audio and video signals by step S242.
In one embodiment, see Fig. 2, shaping unit 15 automatically from timing regeneration unit 14 obtain LRCK signal and
BCK signal automatically obtains MCLK signal from phase locking unit 13, from receive end member 11 automatically obtain DATA signal, by multichannel without
Source shaping channel carries out passive shaping to each signal, will treated that each reshaping signal synchronizes matching obtains new number
Audio signal.Fig. 6 can be referred to about the technical characteristic of passive shaping channel and simultaneously match, which is not described herein again.
Step S250 exports new digital audio and video signals.
In one embodiment, see that Fig. 2, new digital audio and video signals are exported by the output port of shaping unit.
It should be noted that new digital audio and video signals obtained in this implementation be still MCLK signal, BCK signal, LRCK signal and
The I2S data flow that DATA signal is constituted, only the I2S data flow has high-precision, high stability, hi-fi, low noise
And complete feature, it is handled conducive to the audio decoder of subsequent decoding signal, true each details for restoring audio signal.
It will be understood by those skilled in the art that all or part of function of various methods can pass through in above embodiment
The mode of hardware is realized, can also be realized by way of computer program.When function all or part of in above embodiment
When being realized by way of computer program, which be can be stored in a computer readable storage medium, and storage medium can
To include: read-only memory, random access memory, disk, CD, hard disk etc., it is above-mentioned to realize which is executed by computer
Function.For example, program is stored in the memory of equipment, when executing program in memory by processor, can be realized
State all or part of function.In addition, when function all or part of in above embodiment is realized by way of computer program
When, which also can store in storage mediums such as server, another computer, disk, CD, flash disk or mobile hard disks
In, through downloading or copying and saving into the memory of local device, or version updating is carried out to the system of local device, when logical
When crossing the program in processor execution memory, all or part of function in above embodiment can be realized.
Use above specific case is illustrated the present invention, is merely used to help understand the present invention, not to limit
The system present invention.For those skilled in the art, according to the thought of the present invention, can also make several simple
It deduces, deform or replaces.
Claims (10)
1. a kind of timing of digital audio and video signals regenerates shaping methods, which comprises the following steps:
Digital audio and video signals are obtained, the digital audio and video signals include the first clock signal and DATA signal；
The response frequency of a MCLK signal is determined according to the frequecy characteristic of first clock signal；
The MCLK signal is repeatedly divided, a BCK signal and a LRCK signal are obtained；
The MCLK signal, the BCK signal, the LRCK signal and the DATA signal are synchronized into matching, obtained new
Digital audio and video signals；
Export the new digital audio and video signals.
2. timing as described in claim 1 regenerates shaping methods, which is characterized in that the digital audio and video signals are I2S audio
Signal or SPDIF audio signal；When the digital audio and video signals are SPDIF audio signal, then demodulation obtains the I2S sound
Frequency signal, using in the I2S audio signal frame clock signal or bit clock signal as first clock signal.
3. timing as claimed in claim 2 regenerates shaping methods, which is characterized in that according to the frequency of first clock signal
Feature determines the response frequency of a MCLK signal, comprising:
The predeterminated frequency range where first clock signal is judged according to the frequency of first clock signal, by described
Predeterminated frequency range determine the MCLK signal response frequency be 22.5792MHz, 24.576MHz, 45.1584MHz or
49.152MHz。
4. timing as claimed in claim 3 regenerates shaping methods, which is characterized in that repeatedly divided the MCLK signal
Frequently, a BCK signal and a LRCK signal are obtained, comprising:
Frequency dividing three times is carried out to the MCLK signal and obtains the BCK signal, nine frequency dividings are carried out to the MCLK signal and are obtained
The LRCK signal.
5. timing as claimed in claim 4 regenerates shaping methods, which is characterized in that believe the MCLK signal, the BCK
Number, the LRCK signal and the DATA signal synchronize matching, obtain new digital audio and video signals, comprising:
Passive shaping is carried out to the waveform of the MCLK signal, the BCK signal, the LRCK signal and the DATA signal,
Respectively obtain corresponding reshaping signal；
Each reshaping signal is synchronized into matching and obtains the new digital audio and video signals.
6. a kind of timing of digital audio and video signals regenerates apparatus for shaping characterized by comprising
Receiving unit, for receiving digital audio and video signals, the digital audio and video signals include the first clock signal and DATA signal；
Main control unit is connect with the receiving unit, for determining a MCLK according to the frequecy characteristic of first clock signal
The response frequency of signal；
Phase locking unit is connect with the receiving unit and the main control unit, for determining the MCLK in the main control unit
An oscillator is locked when the response frequency of signal to export the MCLK signal according to the response frequency；
Timing regeneration unit is connect with the phase locking unit and the main control unit, described in determining in the main control unit
When phase locking unit exports the MCLK signal, the MCLK signal is repeatedly divided, obtains a BCK signal and LRCK letter
Number；
Shaping unit is connect with the timing regeneration unit, for believing the MCLK signal, the BCK signal, the LRCK
Number and the waveform of the DATA signal carry out passive shaping, each signal after shaping is synchronized into matching and obtains the new number
Word audio signal.
7. timing as claimed in claim 6 regenerates apparatus for shaping, which is characterized in that it is single that the main control unit controls the reception
Member selection receives I2S audio signal or SPDIF audio signal；When the digital audio and video signals are SPDIF audio signal, then
The receiving unit demodulates to obtain the I2S audio signal, by the frame clock signal or bit clock in the I2S audio signal
Signal is using as first clock signal.
8. timing as claimed in claim 7 regenerates apparatus for shaping, which is characterized in that
The main control unit judges the predeterminated frequency where first clock signal according to the frequency of first clock signal
Range, by the predeterminated frequency range determine the MCLK signal response frequency be 22.5792MHz, 24.576MHz,
45.1584MHz or 49.152MHz；
The phase locking unit includes multiple oscillators, the locking when the main control unit determines the response frequency of the MCLK signal
One of oscillator generates crystal oscillation signal corresponding with the response frequency, to be exported as the MCLK signal.
9. timing as claimed in claim 8 regenerates apparatus for shaping, which is characterized in that described in the timing regeneration unit receives
MCLK signal, carries out frequency dividing three times to the MCLK signal and obtains the BCK signal, carries out nine frequency dividings to the MCLK signal
Obtain the LRCK signal.
10. timing as claimed in claim 9 regenerates apparatus for shaping, which is characterized in that the shaping unit includes that multichannel is passive
Shaping channel；
Passive shaping channel described in each road is respectively to the MCLK signal, the BCK signal, the LRCK signal and the DATA
The waveform of signal carries out passive shaping, and the signal after each road shaping is synchronized matching and obtains the new digital audio and video signals,
And the new digital audio and video signals are exported.
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