CN115437988A

CN115437988A - Synchronization method, device and application of I2S audio clock data

Info

Publication number: CN115437988A
Application number: CN202110644352.0A
Authority: CN
Inventors: 汪卫章
Original assignee: Beijing Shikuang Technology Co ltd
Current assignee: Beijing Shikuang Technology Co ltd
Priority date: 2021-06-04
Filing date: 2021-06-09
Publication date: 2022-12-06

Abstract

The invention provides a method, a device and an application for synchronizing I2S audio clock data, which are characterized in that an I2S audio data stream of a CPU without a slave mode is divided into multi-frame audio data, bit stream data of all 0 are inserted between frame data, a frame header is added to each frame of audio data to form new frame data, and the new frame data are sent to an FGPA chip; after the FGPA chip receives the frame data, frame headers and idle data are removed to obtain new audio data; meanwhile, the FGPA chip generates a TIME signal to the CPU according to a local crystal oscillator or a clock, prompts the CPU to synchronously send audio data volume to the FGPA chip, and writes new audio data into the FIFO chip; the FPGA chip generates BCK data and LRCK data to the digital-to-analog converter according to a local clock or a crystal oscillator, reads audio data in the FIFO chip and sends the audio data to the digital-to-analog converter. The synchronization method of the invention realizes the synchronization of the clock information of the I2S audio data of the CPU without the slave mode and the clock data of the FGPA chip, and realizes the purpose of playing music files with higher quality.

Description

Synchronization method, device and application of I2S audio clock data

Technical Field

The present application relates to the field of audio communication technologies, and in particular, to a method, an apparatus, and an application for synchronizing I2S audio clock data.

Background

The rapid development and wide application of large scale integrated circuits has greatly increased the complexity of digital systems, resulting in increasingly complex design, development, detection and fault diagnosis. In practical applications, many CPUs provide an I2S interface, but there are partial CPUs in which I2S has no slave mode and only master mode, i.e., I2S clock is converted from CPU master clock through PLL. In this case, the clock frequency offset of the audio system is generally large, and the jitter is also large. Therefore, the conventional limited I2S audio clock data method is far from satisfying the user' S needs.

For the existing I2S audio data of the CPU without the slave mode, the synchronization with the clock data information of the FGPA chip cannot be achieved when the I2S audio data is transmitted to the FGPA chip, so that the clock signal of the I2S audio data of the CPU without the slave mode and the clock signal of the FGPA chip are not synchronized, and high-quality playing of various music files cannot be performed.

Therefore, it is desirable to develop a method, an apparatus and an application for synchronizing I2S audio clock data, so as to solve the technical problems in the existing product development.

Disclosure of Invention

In order to solve the technical problems that the synchronization of the I2S audio data of a CPU without a slave mode and the clock data information of an FGPA chip can not be achieved when the I2S audio data is transmitted to the FGPA chip in the prior art, and the high-quality playing of various music files can not be realized, the invention develops a synchronization method, a device and application of I2S audio clock data, and effectively solves the technical problems. The synchronization method of the I2S audio clock data can realize the synchronization of the clock information of the I2S audio data when the I2S audio data of the CPU without the slave mode is transmitted to the FGPA chip, thereby realizing more accurate clock signals and achieving the purpose of playing various music files with higher quality.

In a first aspect of the present invention, a method for synchronizing I2S audio clock data is developed, where the method includes:

step one, preprocessing an I2S audio data stream of a CPU without a slave mode:

cutting an I2S audio data stream of a CPU without a slave mode into audio data of one frame and one frame;

adding a frame header to the audio data (comprising n words, wherein n is more than 1) of each frame to form frame data with the length of n +1 words; the frame header comprises a frame data length and a CRC (cyclic redundancy check) length;

step two, the CPU without the slave mode sends the frame data with the length of n +1 words to a receiving end FGPA chip;

meanwhile, the receiving end FGPA chip generates a TIME signal to the CPU without the slave mode according to a local crystal oscillator or a clock, and the CPU without the slave mode synchronously sends audio data volume to the receiving end FGPA chip after detecting the TIME signal;

step three, the receiving end FGPA chip removes the frame header and the idle data from the received frame data with the length of n +1 words to obtain new audio data; writing the new audio data into an FIFO chip;

and step four, the FPGA chip generates second BCK data and second LRCK data to the digital-to-analog converter according to a clock or a crystal oscillator arranged on the FPGA chip, and reads the new audio data in the step three from the FIFO chip and sends the new audio data to the digital-to-analog converter.

Preferably, the I2S audio data stream of the CPU without the slave mode includes first BCK data and first LRCK data, and the first BCK data and the first LRCK data are generated by an internal clock phase lock of the CPU without the slave mode.

More preferably, all 0 bit stream data or none of all 0 bit stream data is inserted between the audio data of one frame and one frame.

More preferably, the length of the bit stream data of all 0 s can realize the following functions: so that the rate of audio data in the frame of length n +1 words is the same as the rate of audio data required by the clock of the FPGA chip.

More preferably, the synchronization method of the second step includes: the synchronization method in the second step comprises the following steps: if the header CRC of the frame data with the length of n +1 words received by the receiving FGPA chip continuously receives three frames (there may be or may not be all 0 bit stream data in the middle of the frame), the receiving FGPA chip enters a synchronization state, so as to correctly obtain the required audio data.

In a second aspect, the invention develops a synchronization device for I2S audio clock data, where the synchronization device includes a CPU without a slave mode, an FGPA chip, a FIFO chip, and a digital-to-analog converter; setting audio clock data (first BCK data and first LRCK data) acquired from the I2S audio data stream of the CPU without the slave mode, and enabling the frequency of the first BCK data and the first LRCK data to be larger than the local oscillation frequency of the FPGA chip; the CPU without the slave mode sends frame data with the length of n +1 words to the FGPA chip, wherein n is greater than 1; when the FGPA chip receives the frame data with the length of n +1 words, the TIME signal is sent to the CPU without the slave mode according to a local crystal oscillator or a clock, so that the CPU without the slave mode synchronously sends the audio data amount to the receiving end FGPA chip; after the FGPA chip receives the frame data with the length of n +1 words, frame headers and idle data are removed to obtain new audio data, and the new audio data are written into the FIFO chip; and the FPGA chip generates second BCK data and second LRCK data to the digital-to-analog converter according to a local crystal oscillator or a clock, reads the new audio data from the FIFO chip and sends the new audio data to the digital-to-analog converter.

Preferably, the method for acquiring the frame data with the length of n +1 words comprises the following steps: dividing an I2S audio data stream of a CPU without a slave mode into audio data of one frame and one frame; adding a frame header to audio data (comprising n words, wherein n is more than 1) of each frame to form frame data with the length of n +1 words; and the frame header frame data length and the CRC check length.

More preferably, the length of the bit stream data of all 0 s can realize the following functions: and enabling the rate of the frame data with the length of n +1 words to be the same as the rate of the clock data of the FPGA chip.

A third aspect of the present invention is an application of the foregoing method or the foregoing synchronization apparatus to music playing.

The invention has the technical effects that: by the I2S audio clock data synchronization method, the device and the application, the synchronization of the clock information of the I2S audio data is effectively realized when the I2S audio data of the CPU without the slave mode is transmitted to the FGPA chip, so that more accurate clock signals are realized, and the aim of playing various music files with higher quality is fulfilled.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 shows a system schematic of the present invention;

FIG. 2 illustrates a data frame structure of the present invention; where Ln denotes the left channel and Rn denotes the right channel.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments have been given like element numbers associated therewith. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the description of the methods may be transposed or transposed in order, as will be apparent to a person skilled in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).

In the invention, if not specifically stated, the TIME signal refers to a low-frequency signal obtained by frequency division of a high-quality crystal oscillator connected with the FPGA chip and generated by the FPGA chip.

For clear understanding of the technical contents of the present application, some technical terms will be described herein.

The I2S signal (Inter-IC Sound signal) is a bus standard established by philips for audio data transmission between digital audio devices (e.g., CD players, digital audio processors, digital television Sound systems). The method avoids distortion induced by time difference by a design mode of separating a data signal and a clock signal. The standard bus cable for transmitting I2S signals is composed of 3 serial conductors: 1 is a time division multiplexing data line, and 1 is a word selection line; the 1 root is the clock line. Then, the I2S signal mainly includes a frame clock signal (LRCK), a serial clock signal (BCK or SCLK), and a serial DATA signal (DATA or SDATA); the LRCK is used for switching data of left and right channels, and when the LRCK is at a high level (namely '1'), it indicates that right channel data is transmitted, and when the LRCK is at a low level (namely '0'), it indicates that left channel data is transmitted, and the frequency of the LRCK is equal to the sampling frequency; each pulse of the BCK corresponds to each bit of data of the digital audio, and the frequency =2 sampling frequency and sampling bit depth of the BCK; DATA is audio DATA represented by two's complement, and usually transmitted from the most significant bit MSB to the least significant bit LSB in sequence.

The invention provides a method for synchronizing I2S audio clock data, which belongs to the technical field of audio communication and comprises the following steps: dividing an I2S audio data stream of a CPU without a slave mode into audio data of one frame and one frame, and inserting bit stream data of which the number is 0 between the audio data of one frame and one frame; meanwhile, a frame header is added to the audio data of each frame to form frame data with the length of n +1 words, and the CPU without the slave mode sends the frame data with the length of n +1 words to a receiving end FGPA chip; meanwhile, the receiving end FGPA chip generates a TIME signal to the CPU without the slave mode, and the CPU without the slave mode synchronously sends audio data volume to the receiving end FGPA chip after detecting the TIME signal; the receiving end FGPA chip removes the frame header and the idle data from the received frame data with the length of n +1 words to obtain new audio data; writing the new audio data into an FIFO chip; and the FPGA chip generates second BCK data and second LRCK data to the digital-to-analog converter according to a clock or a crystal oscillator arranged on the FPGA chip, and reads the audio data in the third step from the FIFO chip and sends the audio data to the digital-to-analog converter. The synchronization method of the I2S audio clock data can realize the synchronization of the clock information of the I2S audio data when the I2S audio data of the CPU without the slave mode is transmitted to the FGPA chip, thereby realizing more accurate clock signals and achieving the purpose of playing various music files with higher quality.

The technical solution of the present application will be described in detail with reference to the following examples.

The invention provides a method, a device and an application for synchronizing I2S audio clock data.A CPU (Central processing Unit) 2S audio data stream without a slave mode is divided into a plurality of frames of audio data, all 0 BIT stream data are inserted between frame data, a frame header is added on the n words of audio data of each frame to form frame data with the length of n +1 words, and the frame data is sent to an FGPA (fiber-fast packet) chip (in the invention, the length of the audio data of each frame is generally 32BIT or 24BIT according to the width of an audio data channel BIT, each word contains data of a left sound channel and a right sound channel, namely 2 × 32=64BIT or 2 × 24= 48BIT); the FGPA chip removes frame headers and idle data from the received frame data to obtain new audio data; meanwhile, the FGPA chip generates a TIME signal to the CPU according to a local crystal oscillator or a clock, so that the CPU is prompted to synchronously send audio data volume to the FGPA chip; the FPGA writes new audio data into an FIFO chip in the FPGA; the FPGA chip generates BCK data and LRCK data to the digital-to-analog converter according to a local clock or a crystal oscillator, reads audio data and sends the audio data to the digital-to-analog converter. The synchronization method of the invention realizes the synchronization of the clock information of the I2S audio data of the CPU without the slave mode and the clock data of the FGPA chip, and realizes the purpose of playing the music file with higher quality.

Embodiment 1, method for synchronizing I2S audio clock data

The present embodiment provides a method for synchronizing I2S audio clock data, as shown in fig. 1 and fig. 2, the method includes:

step one, preprocessing an I2S audio data stream of a CPU without a slave mode:

and setting audio clock data (first BCK data and first LRCK data) acquired from the I2S audio data stream of the CPU without the slave mode, so that the frequency of the first BCK data and the first LRCK data is greater than the local oscillation frequency of the FPGA chip.

The method comprises the steps of cutting an I2S audio data stream of a CPU without a slave mode into audio data of one frame and one frame (each frame of audio data comprises n words, wherein n is more than 1), adding a frame header on the audio data of each frame to form frame data with the length of n +1 words (in the invention, the length of the audio data of each frame is generally 32BIT according to the BIT width of an audio data channel, each word contains data of left and right channels, namely 2 x 32= 64BIT); wherein the frame header comprises two parts: one part is the length of frame data, and the length of the frame data is in units of words; the other part is CRC check length; the I2S audio data stream of the CPU without the slave mode comprises first BCK data and first LRCK data, and the first BCK data and the first LRCK data are generated by the internal clock phase lock of the CPU without the slave mode.

All 0 words can be inserted between the audio data of one frame and one frame, wherein all 0 words are a string of bit streams all 0, and the number of 0 words is N, which represents null data; the length of inserting all 0 words is inserting the idle space in the redundant clock space after inserting the normal audio data according to the requirement of TIME, so that the speed of the audio data in the frame with the length of n +1 words is the same as the speed of the audio data required by the clock of the FPGA chip. For example, if the frequency of the audio data of the CPU without the slave mode is 44.1Khz, assuming that the TIME signal changes once at 10 HZ; and if the CPU without the slave mode detects a TIME change every TIME, the CPU without the slave mode sends audio data to the receiving end FGPA chip about 4410 TIMEs, and because the frequencies of the BCK data and the LRCK data generated by the CPU without the slave mode are higher, idle data are interleaved between the BCK data and the LRCK data sent by the CPU without the slave mode to the receiving end FGPA chip, so that the rate of the audio data in the frame data of n +1 words is the same as the rate of the audio data required by the clock of the FPGA chip.

And step two, the receiving end FGPA chip generates a TIME signal to the CPU without the slave mode according to a local crystal oscillator or a clock, and after the CPU without the slave mode detects the TIME signal, the data volume sent to the receiving end FGPA chip is synchronized (here, the synchronization method includes but is not limited to that, if the CPU without the slave mode continuously receives three frames of correct CRC, synchronization is realized).

The I2S audio data stream of the CPU without the slave mode comprises first BCK data and first LRCK data, and the first BCK data and the first LRCK data are generated by the internal clock phase lock of the CPU without the slave mode.

And step three, the CPU without the slave mode sends the frame data with the length of n +1 words in the step one to the receiving end FGPA chip in the step two, if the header CRC of the frame data with the length of n +1 words continuously received by the receiving end FGPA chip is correct, the receiving end FGPA chip skips all 0 words possibly existing in the middle of the frame, namely enters a synchronization state, and enters synchronization.

The receiving end FGPA chip removes the frame header and the idle data from the received frame (n is more than 1) data with the length of n +1 words to obtain new audio data; and the FPGA chip writes the new audio data into an FIFO chip in the FPGA chip.

And fourthly, the FPGA chip generates BCK data and LRCK data to a digital-to-analog converter (DAC) according to a clock or a crystal oscillator arranged on the FPGA chip, and reads the audio data in the third step from the FIFO chip and sends the audio data to the digital-to-analog converter (DAC) to finish data transmission.

In this embodiment, a method for synchronizing I2S audio clock data is developed, so as to implement synchronization between the audio clock data of the CPU without the slave mode and the clock data of the FGPA chip, and implement a function of high-quality playing during music playing.

Embodiment 2, a synchronization device for I2S audio clock data

The embodiment develops a synchronization device of I2S audio clock data, and the synchronization device comprises a CPU without a slave mode, an FGPA chip, a FIFO chip and a digital-to-analog converter.

The I2S audio data stream of the CPU without the slave mode is cut into audio data of one frame and one frame (each frame of audio data comprises n words, and n is more than 1), and all 0 bit stream data is inserted between the audio data of one frame and one frame. The length of the bit stream data which is all 0 can realize the following functions: the rate of the frame data with the length of n +1 words is the same as the rate of the clock data of the FPGA chip (in the invention, the length of the audio data of each frame is generally 24BIT according to the width of an audio data channel BIT, each word contains data of a left channel and a right channel, namely 2 × 24= 48BIT).

Adding a frame header to the audio data of each frame to form a frame of data with the length of n +1 words, wherein n is more than 1; the frame header comprises two parts: one part is the length of frame data, and the length of the frame data is in units of words; the other part is CRC check length; the I2S audio data stream of the CPU without the slave mode comprises first BCK data and first LRCK data, and the first BCK data and the first LRCK data are generated by the internal clock phase lock of the CPU without the slave mode.

The CPU without the slave mode sends frame data with the length of n +1 words to the FGPA chip; when the FGPA chip receives the frame data with the length of n +1 words, the local crystal oscillator or the clock sends a TIME signal to the CPU without the slave mode to promote the CPU without the slave mode to synchronously send the audio data volume to the receiving end FGPA chip; and after the FGPA chip receives the frame data with the length of n +1 words, frame headers and idle data are removed to obtain new audio data, and the new audio data is written into an FIFO chip in the FPGA chip.

The FPGA chip sends BCK data and LRCK data to the digital-to-analog converter according to a clock or a crystal oscillator arranged on the FPGA chip, reads the audio data from the FIFO chip and sends the audio data to the digital-to-analog converter.

In this embodiment, a synchronization apparatus for I2S audio clock data is developed, so as to implement synchronization between the audio clock data of the CPU without the slave mode and the clock data of the FGPA chip, and implement a function of high-quality playing during music playing.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by computer programs. When all or part of the functions of the above embodiments are implemented by a computer program, the program may be stored in a computer-readable storage medium, and the storage medium may include: a read only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc., and the program is executed by a computer to realize the above functions. For example, the program may be stored in a memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above can be implemented. In addition, when all or part of the functions in the above embodiments are implemented by a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a portable hard disk, and may be downloaded or copied to a memory of a local device, or may be version-updated in a system of the local device, and when the program in the memory is executed by a processor, all or part of the functions in the above embodiments may be implemented.

The present invention has been described in terms of specific examples, which are provided to aid in understanding the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims

1. A method for synchronizing I2S audio clock data, said method comprising:

step one, preprocessing an I2S audio data stream of a CPU without a slave mode:

adding a frame header to the audio data of each frame to form frame data with the length of n +1 words; wherein the audio data of each frame comprises n words, and n is more than 1; the frame header comprises a frame data length and a CRC check length;

2. The synchronization method of claim 1, wherein the I2S audio data stream of the CPU without slave mode comprises a first BCK data and a first LRCK data, and the first BCK data and the first LRCK data are generated by an internal clock phase lock of the CPU without slave mode.

3. The synchronization method according to claim 1 or 2, wherein all 0 bit stream data or none of the all 0 bit stream data is inserted between the audio data of one frame and one frame.

4. The synchronization method according to claim 3, wherein the bit stream data with all 0's length can implement the following functions: so that the rate of audio data in the frame of length n +1 words is the same as the rate of audio data required by the clock of the FPGA chip.

5. The synchronization method according to claim 3, wherein the synchronization method of step two comprises: if the header CRC of the frame data of which the length is n +1 words continuously received by the receiving end FGPA chip is correct, the receiving end FGPA chip enters a synchronous state.

6. The device for synchronizing the I2S audio clock data is characterized by comprising a CPU without a slave mode, an FGPA chip, a FIFO chip and a digital-to-analog converter;

setting audio clock data obtained from the I2S audio data stream of the CPU without the slave mode, wherein the audio clock data comprises first BCK data and first LRCK data, and the frequency of the first BCK data and the first LRCK data is larger than the local oscillation frequency of the FPGA chip;

the CPU without the slave mode sends frame data with the length of n +1 words to the FGPA chip, wherein n is larger than 1; when the FGPA chip receives the frame data with the length of n +1 words, the TIME signal is sent to the CPU without the slave mode according to a local crystal oscillator or a clock, so that the CPU without the slave mode synchronously sends the audio data amount to the receiving end FGPA chip;

after the FGPA chip receives the frame data with the length of n +1 words, frame headers and idle data are removed to obtain new audio data, and the new audio data are written into the FIFO chip;

and the FPGA chip generates second BCK data and second LRCK data to the digital-to-analog converter according to a local crystal oscillator or a clock, reads the new audio data from the FIFO chip and sends the new audio data to the digital-to-analog converter.

7. The synchronization apparatus according to claim 6, wherein the frame data with length n +1 words is obtained by: dividing an I2S audio data stream of a CPU without a slave mode into audio data of one frame and one frame; adding a frame header to the audio data of each frame to form frame data with the length of n +1 words; wherein the audio data of each frame comprises n words, and n is more than 1; the frame header comprises a frame data length and a CRC check length.

8. The synchronization apparatus as claimed in claim 7, wherein all 0 bit stream data or none of all 0 bit stream data is inserted between the audio data of one frame.

9. The synchronization apparatus as claimed in claim 7, wherein the bit stream data with all 0's length can implement the following functions: the rate of the frame data with the length of n +1 words is the same as the rate of the clock data of the FPGA chip.

10. Use of the method according to claim 4 or 5, or the synchronization device according to any of claims 6 to 9, for music playback.