JP3451971B2 - Packet transfer device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet transfer device for receiving event sequence data such as audio data on a high speed serial network to which a plurality of devices are connected.

[0002]

2. Description of the Related Art A plurality of electronic musical instruments and audio equipment are sequentially connected by a cable to form an "IEEE1394" standard serial network, and audio data (voice, audio,
Music and MIDI data transmission technology is called "Protocol for audio and music data transfer" (Audio
and Music Data Transmission Protocol, Version1.0,19
97-5, 1394 Trade Association).

FIG. 10 is an explanatory diagram showing the flow of packets on the network. There are a plurality of nodes on the network, in this example, three transmitting nodes A101, transmitting nodes B102, transmitting nodes C103, and receiving nodes 104. In the illustrated example, a plurality of transmitting nodes A10
Audio data input from an external device at 1, B102, and C103 is reproduced by the external device at the receiving node. Sending nodes A101, B102, C10
3 transmits the respective packets, and the receiving node 104 receives the packets transmitted from the plurality of transmitting nodes, and reproduces the audio data included in the packets from the desired transmitting nodes at a predetermined sampling rate.
105a to 105d are packets transmitted from the transmission node A101, and 106a to 106c are transmission nodes B1.
A packet transmitted from 02, 107 is a transmitting node C1
It is a packet transmitted from 03.

The entire network is time-controlled by the cycle master node. A cycle start packet is transmitted from the cycle master node to other nodes every 125 μsec. On other nodes,
Each time this cycle start packet is received, the cycle timer inside the node is timed with the absolute time information in the packet to synchronize with the cycle master node.

Each transmitting node A101, B102, C10
In No. 3, a time stamp (hereinafter abbreviated as syt is used) based on the time of the cycle timer is applied to the audio data reproduced at a predetermined sampling clock by an external device connected to its own node, and a sampling clock (8 One data block) is generated.
Then, one or a plurality of channels of audio data are put in the data field, and syt is put in the syt field to create and transmit a packet. The reproduction time on the reception side of the event sequence (audio channel) is designated by syt (time stamp). DBC (Da
ta Block Count) is the value of the total number of data blocks transmitted so far. A data block is usually composed of data of a plurality of event sequences generated by the same sampling clock.

FIG. 11 is an explanatory diagram of a packet format during isochronous transfer. Isochronous transfer is data transfer defined in the link layer of IEEE 1394, a transmission delay is guaranteed, and each node secures a "bandwidth" in advance. Packet formats are isochronous header, CIP (Common i
sochronous packet format) It consists of a header and a data field. 32 bits are the basic unit. The isochronous header has fields of data length, tag, channel (isochronous transfer channel), "1010" bit string (tcode) representing an isochronous data packet, synchronization (sync), and header CRC.

[0007] The CIP header contains various items necessary for reception, such as DBS (Data Block Size), DBC (Data Block Count), syt (time stamp), etc. Sy of the packet that has a field of
The value of no data is entered in the t field. Audio data, MIDI data, etc. are entered in the data field. Regarding the data format in the data field, although not shown, (1) AM824: generic format,
(2) AM824: IEC958conformant, (3) AM824: Rawaudi
o, (4) AM824: MIDI conformant, (5) 32bit Data fo
There are rmat and (6) 24 * 4 Audio pack format.

FIG. 12 is a diagram for explaining the operation of isochronous transfer. This figure is for explaining transfer control.
In the above-mentioned FIG. 10, syt is added for every 8 data blocks (8 sampling clocks), but in FIG. 12, syt is added for every 4 data blocks (4 sampling clocks), and the sampling frequency Fs
Is 26.7 kHz. The upper side is the transmission side, which shows one event sequence (sampling data) included in the data block, and the middle stage shows the packet. The lower part is the receiving side, and shows one event sequence (sampling data) included in each data block. In this example, sampling data reproduced at a predetermined sampling clock is input as an event sequence. The cycle timer of the transmitting node outputs the time value. The transmitting node shall have a nominal isochronous cycle (1
Once every 25 μsec), a data block for the secured bandwidth is created, a syt of a value considering transmission delay is added, and the packet is transmitted.

In the first packet, DBC = 3 (three data blocks have already been transmitted) and syt = R1 are included in the packet together with three data blocks. In the second packet, DBC = 6 (six data blocks have already been transmitted) and syt = R2 are put in a predetermined field together with four data blocks. Similarly, the third to fifth packets are transmitted. However, the fourth packet does not include the data block of the sampling clock corresponding to the syt interval.
Is not added.

The packet is transmission-delayed and received by the receiving node. Then, a reproduction sampling clock is generated. In the figure, the index value is the number (0-3) of the plurality of data blocks included in the packet.
It is a value indicating whether the data block corresponds to the time of the t interval, and is obtained by calculation from the value of DBC and the syt interval.

Returning to FIG. 10, description will be made again. In the packet 105a transmitted by the transmitting node A1, the DBC
= 3 is added. In the packet 105b, the DB
C = 7 and syt = 1000 are added. This syt =
The data block at the same time as the time of 1000 is DA0. In the packet 105d, DBC = 16, s
yt = 9000 is added. The data block at the same time as the time of syt = 9000 is DA8. DA
8 is a data block 8 data blocks after DA0. On the other hand, in the packet 106a transmitted by the transmitting node B 102, DBC = 7 and syt = 7000 are added. In the packet 106b, DBC = 1
2 is added, and in the packet 106c, DBC =
16, syt = F000 is added.

The IEEE 1394 standard 1-3 cables are physical layer ICs in charge of physical layers in each node.
This physical layer IC is connected to (Integrated Circuit)
Is connected to the link layer controller IC which is in charge of the link layer. This link layer controller IC has an IEEE
E1394 Digital audio / MIDI transfer LSI
(Large scale integration, hereinafter referred to as a packet handler) is connected to execute the above-mentioned “protocol regarding audio and music data transfer”. When event sequence data such as real-time audio and music data is transmitted in the isochronous transfer mode packet format, since it is not synchronous transmission, the arrival time of the packet to the receiving node and the receiving interval are not constant. Therefore, it is necessary to reproduce the received audio data at the time designated by the transmitting side and output the audio data to an external device in synchronization with the input sampling clock of the transmitting side.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a packet transfer device which receives a packet containing event sequence data and reproduces it at the time designated by the transmitting side.

[0014]

The present invention SUMMARY OF THE INVENTION, in the invention according to claim 1, a packet transfer apparatus that receives a packet from the desired number of multiple transmitting nodes on the network, synchronized with the network Cycle timer
Cycle timer that outputs the time and whether the sending node
, One or more events in each sampling period.
One data block is composed of sequence data
And include one or more of the data block.
The time stamp for each specified number of data blocks
When a packet with is added is received,
Take out the time stamp together with the data block
And the unpacket means for outputting, and the desired plurality of transmissions.
One of the receiving nodes is used as a synchronous playback reference node, and
The synchronous reproduction reference node output from the packet means
Play using the time stamp included in the packet from
Playback sample that synchronously reproduces and outputs the sampling clock
Pulling clock output means and the unpacket means
From the reception block that sequentially stores the data blocks output from
From the playback sampling clock output means
Receiving according to the output reproduction sampling clock
By reading the data block from the buffer
Data output to output the event sequence data
Output from the unpacket means,
The time stamp included in the packet from the synchronous playback reference node.
The time corresponding to the tamper and the output from the cycle timer
At the timing when the cycle timer time
The data output means outputs the data from the reception buffer.
By correcting the data block removal position,
Time stamp when the data output means matches
Playback time to output the data block corresponding to the time
It is provided with a control means .

Also, the event sequence from each transmitting node
The time stamp from each sending node.
It can be output according to the set time. More specifically, when the time stamp output means outputs the time stamps from a plurality of transmission nodes at the same time, the time correction means can correct the event sequence data from a plurality of transmission nodes at the same time. Further, when the time stamp output means sequentially outputs the time stamps from the plurality of transmission nodes, the time correction means,
Event sequence data from a plurality of transmitting nodes can be time-corrected sequentially. In the latter case, one that outputs one time stamp to a plurality of transmission nodes and one that corrects the time to one transmission node can be used, so the configuration is simple. It is also possible to adopt a structure in which simultaneous processing and sequential processing are combined.

In the invention according to claim 2, the net
Desired first transmission node and second transmission node on the work
A packet transfer device that receives packets from the
When the cycle timer is synchronized in the network
And a first transmission node
From the second sending node,
One or more event sequence data in the cycle
One data block consists of
The data block contains one or more data blocks.
A packet with a time stamp added for each specified number of
Packet and receives the data block from the packet.
An amper that both extracts and outputs the time stamp
Output from the packet means and the unpacket means,
Note Times included in the packet from the first transmitting node
Synchronized playback of playback sampling clock using tamps
Sampling clock output means for outputting
From the first transmitting node output from the packet means
First receiving buffer for sequentially storing the data blocks of
Output from the reproduction sampling clock output means
According to the reproduced sampling clock
By reading the data block from the signal buffer
The first sequence that outputs the event sequence data.
Output from the data output means and the unpacket means.
The packet contained in the packet from the first transmitting node.
From the time corresponding to the time stamp and the cycle timer
Timing when the output cycle timer time matches
Then, the first reception buffer by the first data output means is
Correct the data block extraction position from the buffer
To match the first data output means.
The data block corresponding to the time of the time stamp
A first reproduction time correction means for outputting a clock,
Is the second transmitting node output from the packet means?
Second receiving buffer for sequentially storing the blocks
And output from the reproduction sampling clock output means.
The second reception according to the reproduced sampling clock
By reading the data block from the buffer
The second sequence that outputs the event sequence data.
Output from the data output means and the unpacket means.
The packet contained in the packet from the second transmitting node.
From the time corresponding to the time stamp and the cycle timer
Timing when the output cycle timer time matches
And the second data reception means by the second data output means.
Correct the data block extraction position from the buffer
To match the second data output means.
The data block corresponding to the time of the time stamp
A second reproduction time correction means for outputting a clock is provided .

[0017]

[0018]

1 is a functional block diagram of a packet handler according to an embodiment of a packet transfer apparatus of the present invention. In the figure, 1 is a transmitter, 2 is a receiver, and 3 is a DIR.
(Digital audio receiver), 4a to 4e are audio interfaces, and 5 is a CPU (Central Processing Unit).
nit) interface, 6 is a CPU bus, 7a, 7b
Is a switching unit and 8a is a transmission FIFO (first
in first out), 8b and 8c are non-audio transmission FI
FO, 8d is a transmission FIFO for syt, 9 is a packetizing unit, and 10 is a link interface. 11 is an unpacketizing unit, and 12a to 12h are audio reception FIs.
FO, 12i and 12j are reception buffers for non-audio,
12k and 12l are reception buffers for syt, 13 is a patch section, 14a to 14e are audio interface sections,
Reference numeral 15 is a CPU interface unit, 16a and 16b are switching units, 17 is a DIT (Digital audio transmitter),
Reference numerals 18a and 18b are adders, 19 is a synchronizing unit, 20 is a link layer controller, and 32a and 32b are delay offset registers. Although not shown in this functional block diagram, each function is executed by executing a program using a CPU and hardware such as a memory.

In the transmitter 1, 8-channel audio data output from a digital audio device such as a mixer is input to the audio interfaces 4b to 4e from the input terminals DAI0 to DAI3. Each of the input terminals DAI0 to DAI3 is time-division multiplexed with 2-channel audio data. In some cases, instead of the input terminal DAI0, data of the IEC958 standard is input from the input terminals IEC958I through the DIR3 by the switching devices 7a and 7b. The output of the DIR3 is supplied to the output terminal DIRO via the audio interface 4a.

On the other hand, the MIDI data is M of the external CPU.
Input FIFO from the IDI interface and transmit via the CPU bus 6 and CPU interface 5 FIFO 8
b, 8c. Audio interface 4
b-4e output (audio0-audio7) and transmission F
The outputs of the IFOs 8b and 8c are input to the transmission FIFO 8a. “FIFO” is a specific memory function.
The data is stored in order at the time of an input request, and the stored data is read out on a first-come-first-served basis in response to a read request that occurs asynchronously with the input request, but it is used as a means for realizing the function of the buffer.

The syt (time stamp) is input to the transmission FIFO 8d every 8 data blocks. Transmission FIF
The output of O8a is input to the packetization unit 9 together with the output of the transmission FIFO 8d, added with a header, and output to the link interface 10. The link interface 10 outputs the packet to the link layer controller 20. The link layer controller 20 transmits / receives packets to / from the packet handler via a 16-bit wide isochronous bus.

Packets transmitted from a plurality of transmission nodes are input to the link interface 10 via the link layer controller 20, input to the unpacketizing unit 11, and unpacketized based on header information and the like. . The packet is interpreted, and the plurality of audio data and the like are temporarily stored in the plurality of reception FIFOs 12a to 12j. By looking at the isochronous transfer channel in the packet header, it is possible to process only the packet from the desired transmission node.

Using the time information of the received sys, the reproduction time of the received audio data is adjusted to the time of the cycle timer of the receiving section, and the reproduction timing clock is synchronized with the input sampling clock of the transmitting side.
Output to external device. Therefore, for audio reception F
IFOs 12a to 12h, first and second reception FI for syt
FO12k and 12l are provided.

Each of the audio data separated from the packet by the unpacketizing unit 11 is an audio reception F.
It is written in the IFOs 12a to 12h. Similarly, the non-audio channel data is also written in the non-audio reception FIFOs 12i and 12j. The sys extracted from the packet is the first reception FIFO1 for the sys.
It is written in the 2k or second reception FIFO 121 for syt. Sys read from the first receive FIFO 12k for the sys and the second receive FIFO 12l for the sys
Are set for each transmitting node in the adders 18a and 18b, respectively, and the delay offset registers 32a and
It is added to the predetermined offset value stored in 32 b and input to the synchronization unit 19. The synchronization unit 19 controls the read timing and the read pointer of the audio data from the audio reception FIFOs 12a to 12h. The synchronization unit 19 has an external output terminal PLLout and an external input terminal PLLin of the reproduction sampling clock, and enables an external output or an external input of the reproduction sampling clock. The operation of the synchronization unit 19 will be described in detail with reference to FIGS.

Audio reception FIFOs 12a-12h
Is provided for each audio node and for each audio channel. Therefore, even if the audio channels separated from the packets from different transmission nodes are mixed, it is not only easy to start reading and synchronous reproduction independently for each channel,
It is easy to flexibly change the number of channels even when the specifications of the packet handler are changed.

Receive FIFOs 12a-12 for audio
The output of h is output to the patch unit 13. Here, the audio data read from the eight audio reception FIFOs 12a to 12h is transferred to the audio channel (au
Allocate to dio0 to audio7). This 8-channel audio data is the audio interface 14b.
14e are time-division-multiplexed by 2 channels and output. This assignment is taken out by the unpacketizing unit 11 from which transmitting node, what kind of audio channel sampling data is formatted in what arrangement, in the data block of the packet. It is done from the information in the header.

The control of the patch unit 13 is performed by using a setting operator provided outside the packet handler.
It can also be done by an external setting input. For example, the received audio data can be switched and output to an output terminal different from the original output destination, or one received audio data can be simultaneously supplied to a plurality of output terminals. The reason why such user setting is possible is that the audio reception FIFOs 12a to 12h are provided for each transmission node and for each audio channel.

On the other hand, the non-audio reception FIFO 12
The data of 2 channels which is the output of i, 12j is CP
It is output to a MIDI input / output interface of an external CPU (not shown) via the U interface 15 and the CPU bus 6. When the data for IEC958 is received, the two audio channels (audio0, audio1) are output to the output terminal IEC958 via the switches 16a, 16b and DIT17. In the switching state of the switching devices 16a and 16b, the audio data from the input terminal DITI is output to the DIT 17 via the audio interface 14a.

FIG. 6 is a flow chart for explaining the outline of the operation of the packet handler shown in FIG. FIG. 6A is a flowchart for explaining an outline of processing as a transmitting node, and FIG. 6B is a flowchart for explaining an outline of processing as a receiving node. In the transmission node process shown in FIG. 6A, in S51, audio data of a plurality of channels is taken in from the external input terminals DAI0 to DAI3 at a predetermined sampling rate to form one data block, and the plurality of data blocks are connected. To form a data field, S52
Proceed to. In the case of MIDI data, external C
It is fetched from the MIDI interface of PU via the CPU bus. In S52, a header is formed, and this header is attached to the data field to form a packet, and the process proceeds to S53.

In S53, it is determined whether or not a processing error has occurred inside the transmission unit. If no error has occurred, the process proceeds to S54, and if any error occurs, the process proceeds to S55. Proceed. As the processing error, for example, the cycle of the sampling clock, which is the input timing of the data block, is calculated based on the time of the time stamp, and the difference between this calculation output and the preset sampling clock cycle exceeds the allowable range. There are times such as when. In S54, the packet is transmitted. In S55, the transmission of the normal packet is stopped to mute the transmission data, and the interrupt packet for reporting the error is transmitted to generate the interrupt signal on the receiving node side.

In the receiving node process shown in FIG. 6B, in S61, the packet data is unpacketized based on the header information, and the audio data and the non-audio data and syt are respectively received by the reception FIFO 12a.
To 12h, 12i, 12j, 12k, 12l. At that time, the write pointer (WP) of each of the reception FIFOs 12a to 12l is managed.

FIG. 2 is a block diagram showing a receiving node reproducing process of the packet handler according to the embodiment of the present invention. In the figure, the same parts as those in FIG. The synchronization unit 19 shown in FIG.
Is a comparator 33a, 33b, a cycle timer 34, PL
It corresponds to an L (Phase locked loop) 35, a read control unit 36, a switching unit 37, and a CPU register 38. Reference numeral 31 is a write control unit. The cycle timer 34 may be built in the packet handler or provided externally.

The packetized audio data is 1
Or it is transmitted from multiple transmitting nodes. The audio reception FIFO 12 is provided for each packet from each transmitting node and for each audio channel in the packet.
a to 12h are assigned one by one.

The receiving node outputs the received audio data at the reproduction sampling clock synchronized with the input sampling clock at the transmitting node.
The input sampling clock at this transmitter node is
Synchronous reproduction is performed based on the time of the transmitted sys to be restored. Each transmitting node transmits a packet by inserting "syt" in a predetermined header field of the packet. Although it is possible to synchronously reproduce the sampling clock for each transmitting node using syt from each transmitting node, the synchronous reproduction of the sampling clock is performed by any one transmitting node, for example, the packet is first received. This is performed using syt included in the packet of the transmitting node A1. Hereinafter, the transmitting node that has transmitted syt for synchronously reproducing the sampling clock is referred to as a synchronous reproduction reference node for convenience.

The write controller 31 uses the first and second sy
A write pointer (W) to the reception buffers 12k and 12l for t and the reception FIFOs 12a to 12h for audio.
The value of P) and the write timing signal are output. The syt from the synchronous playback reference node is set to the first s
Each time it writes to the reception FIFO 12k for yt, the first s
The write pointer (WP) of the yt reception buffer 12k is incremented. On the other hand, the first reception FIFO for syt
Receive FIFO for audio of the same transmitting node as O12k
The value of the write pointer (WP) of O is calculated based on the value of the write pointer (WP) of the reception FIFO 12k for the first syt, and the data of 8 data blocks (8 sampling clocks) are sequentially written. The write pointer (WP) for the second correction reception FIFO 12l for correction, which will be described later, is the second reception FIFO 12 for sys.
It is incremented every time syt from a certain transmitting node is written in l . The value of the write pointer (WP) of the audio reception FIFO of the same transmission node as that of the second reception FIFO 121 for the second sys is the second s.
It is incremented each time syt is written in the yt reception FIFO 12l .

To simplify the explanation, the case where the value stored in the delay offset register 32a is 0 and therefore the same case as when the adder 18a is not provided will be described. In the comparator 33a, the reception FI for syt
When the time of syt that has already been read from the FO 12k and the time of the cycle timer 34 of the receiving node match, a match pulse is output to the PLL 35 and the read control unit 36.

The PLL 35 controls the frequency of the VCO so that the output phase of the built-in VCO (voltage controlled oscillator) becomes 0 when the coincidence pulse is input. This VCO is
It is designed to be self-propelled at a cycle of about 1/8 of the cycle of the coincidence pulse (determined by the syt interval). PL
In L35, the first SYT reception FI is obtained by phase-locking the output of the VCO with the above-mentioned coincidence pulse.
The sampling clock is synchronously reproduced at a cycle of ⅛ of the time difference between adjacent syts read from the FO 12k.
Since the time interval of the coincidence pulse has a time difference between adjacent syts, the coincidence pulse is multiplied by 8 to obtain the reproduction sampling clock. The PLL 35
The phase synchronization need not be performed every time the coincidence pulse is output, and the phase synchronization may be performed by appropriately thinned out coincidence pulses. The reproduction sampling clock output from the PLL 35 is read via the switching unit 37 by the read control unit 36.
And reproduction sampling clock output terminal PLLout
Is output to.

The read control unit 36 uses the first and second sy
The read pointers (R) to the reception buffers 12k and 12l for t and the reception FIFOs 12a to 12h for audio.
The value of P) and the read timing signal are output. Transmission node A101 which is a reference node for synchronous reproduction
It is assumed that the audio data from is temporarily stored in the audio reception FIFOs 12a and 12b, for example. In the read control unit 36, the first reception FI for syt is generated every time a coincidence pulse is generated from the comparator 33a.
The read pointer (RP) of the FO 12k is incremented to read the next syt. At the same time, when the first match pulse is generated from the comparator 33a, the audio reception FIFOs 12a and 12b are read so as to start reading the data block corresponding to the time of the sys read from the first sys reception FIFO 12k. The value of the read pointer is calculated and corrected (time adjustment), and the data block is read. After that, the value of the read pointer is incremented by the reproduction sampling clock output from the PLL 35, and the data block is read.

As a result, the audio data from the transmission node A 101 is synchronized with the cycle timer 34 after the time when the time of the syt of the transmission node A 101 first matches the time of the cycle timer 34 of the reception node.
The reading is started from the audio reception FIFOs 12a and 12b in synchronization with the reproduction sampling clock of.
Even in the period before this point, the read pointer values of the audio reception FIFOs 12a and 12b are incremented for each reproduction sampling clock,
It is also possible to read out and output audio data whose time is not guaranteed.

On the other hand, it is assumed that the audio data from the transmission node B102 other than the synchronous reproduction reference node is temporarily stored in the audio reception FIFOs 12c and 12d, and the read pointers (RP) are corrected (time adjustment). Is performed by the second reception FIFO 12l for syt. Each bit position of the CPU register 38 corresponds to the audio reception FIFOs 12a to 12h. The audio reception FIFO corresponding to the bit position in which the flag bit is inserted is the target of time adjustment by the second sys reception FIFO 12l. When the number of audio reception FIFOs to be corrected by the read pointer once is limited to one, one flag bit may be sequentially shifted to each bit position of the CPU register 38 , so that the configuration is simple. However, if the read pointers are simultaneously corrected for one or more audio reception FIFOs 12c and 12d that temporarily store the event sequence (audio data) from the same transmitting node, the correction can be performed in a short time. It can be carried out. The following operation example illustrates the latter case.

For example, the sys from the transmitting node B 102
Is written in the second reception FIFO 121 for syt. The audio data from the transmitting node B 102 is the reception FI.
It is assumed that they are written in the FOs 12c and 12d. To simplify the description, the delay offset register 31
The value stored in b is 0, and a case similar to the case without the adder 18b will be described.

In the comparator 33b, when the time of syt temporarily stored and read in the second reception FIFO 12l for syt coincides with the time of the cycle timer 34 and a match pulse is output, this match pulse is output. , To the read control unit 36. In the read control unit 36,
Each time a coincidence pulse is generated, the reception F for the second syt is received.
The read pointer (RP) of the IFO 12l is incremented.
At the same time, the second s
sys read from the yt reception FIFO 12l
The values of the read pointers of the audio reception FIFOs 12c and 12d are calculated so that the reading of the data block corresponding to the time is started, and the data block is read.
After that, with the reproduction sampling clock output from the PLL 35, the value of the read pointer is incremented and
Read the data block.

As a result, the audio data from the transmitting node B 102 is also synchronized with the PLL 35 synchronized with the cycle timer 34 from the time when the time of the syt of the transmitting node B 102 first matches the time of the cycle timer 34 of the receiving node.
The data is read from the audio reception FIFOs 12c and 12d in synchronization with the reproduction sampling clock. Note that audio data whose time is not guaranteed can be read and output even in the period before this time.

Once the time-aligned read pointer can be obtained, the pointer may simply be stepped up for each reproduction sampling clock, as long as synchronization is not lost. Therefore, audio data from yet another transmitting node, for example, transmitting node C103,
For example, when temporarily stored in the audio reception FIFOs 12e and 12f, the second reception FIFO for syt is used.
The function of O12l is the reception FIFO for audio 12e,
Switch to correction of each 12f read pointer.

That is, sy from the transmitting node C103
t is written in the second reception FIFO 121 for syt.
In the comparator 33b, the second SYT reception FIFO1
When the time of the syt temporarily stored and read in the 2l matches the time of the cycle timer 34 and a match pulse is output, the read control unit 36 causes the read control unit 36 to read the read pointer (() of the receive FIFO 12l for the second syt. RP). At the same time, the audio reception FIFOs 12e and 12f
After the switching to the correction of the read pointers, the second reception FIFO for the syst is generated at the first occurrence of the coincidence pulse.
The values of the read pointers of the audio reception FIFOs 12e and 12f are calculated and the data block is read so that the data block corresponding to the time of syt read from 12l is started. As a result, after the time of the syt of the transmitting node C103 first matches the time of the cycle timer 34 of the receiving node, the transmitting node C
The audio data from 103 is also stored in the cycle timer 34.
Are read from the audio reception FIFOs 12e and 12f in synchronism with the reproduction sampling clock of the PLL 35 synchronized with.

As described above, it is not necessary to provide the same number of reception FIFOs for sys as the number of reception FIFOs for audio, and the audio data from each transmission node is transmitted based on the time of the cycle timer 34 of the reception node. It can be output from the node at the time designated by syt. Also, audio data can be output at the reproduction sampling clock synchronized with the input sampling clock at each transmission node. As a result, synchronization is possible with the accuracy of one sampling clock.

In the above description, the read control unit 36.
Each time the second comparator 33b generates a coincidence pulse, it advances the read pointer (RP) of the reception FIFO 12l for the second syt. But the second syt
Reception FIFO 12l for audio reception FI
When the audio data written in the FO is used for adjusting the time of the cycle timer 34 only once at the beginning, after the time is adjusted, the sync from the transmitting node is set when the coincidence pulse is generated thereafter. No need to read.

The correction for time adjustment is not performed when the time of syt read from the first and second SYT reception FIFOs 12l coincides with the time of the cycle timer 34 only once. After that, the time may be strictly adjusted by performing the correction on the condition that the read time of the syt and the time of the cycle timer 34 match a plurality of times in succession. Further, after the correction is performed once, the data blocks are read from the audio reception FIFOs 12a to 12h by the reproduction sampling clock synchronized with the input sampling clock for a while. Alternatively, when the time of the syt coincides with the time of the cycle timer 34, the time adjustment may be corrected again. In this way, to determine a match, only once, multiple consecutive matches, multiple matches with an interval, etc.
Although there are various modes, it may be appropriately determined according to the strictness of time management required for actual use. On the contrary, in the case of home use where strict time management of audio data is not required, time adjustment may not be performed and only a function of obtaining a reproduction sampling clock synchronized with the input sampling clock may be provided. In this case, the reception FIFO 12l for the second syt, the second comparator 33b, etc. are not necessary.

In the above description, since the reception FIFOs 12k and 12l for the first and second syts and the first and second comparators 33a and 33b are operated at the same time, two transmission nodes from the two transmission nodes are simultaneously operated. The time of the audio data can be adjusted. In addition to this, the second syt
If one or a plurality of reception FIFOs 12l for use with the same are further provided, the number of audio data channels that can be time adjusted simultaneously can be increased, and the time adjustment time can be shortened. It is also possible to allocate one audio reception FIFO 12a to 12h for each of the audio reception FIFOs 12a to 12h similar to the second reception FIFO 12l for each audio reception without distinguishing whether the audio data is from the same transmission node. .

FIG. 3 is a first explanatory diagram showing an example of the operation of the block diagram shown in FIG. 1 and 2 in the figure
The same parts as those in FIG. FIG. 4 is a second explanatory diagram showing an example of the operation of the block configuration diagram shown in FIG. FIG. 7 is a flowchart for explaining the reproduction process of the receiving node. The specific example illustrated is shown in FIG. Each transmitting node has two audio channels (for example, a left channel and a right channel) for one block of data.

As shown in FIG. 3, the reception FI for audio is used.
The FO 12a temporarily stores the left-channel audio data that composes the data blocks DA0 to DAf, and the audio reception FIFO 12b temporarily stores the right-channel audio data. DA0
Is a data block at a time corresponding to syt = 1000, and DA8 is a data block at a time corresponding to syt = 9000. On the other hand, audio reception FIFO
Two-channel audio data forming each data block of DB0 to DBf ... Is temporarily stored in the O12c and 12d. DB0 is a data block corresponding to syt = 7000, and DB8 is syt = F00.
It is a data block corresponding to 0.

The operation of the audio data reproducing process in the receiving node will be specifically described with reference to the flowchart shown in FIG. The reception node reproduction processing 1 explains the reception FIFO 12k for syt. In S71, the comparator 3 shown in FIGS.
3a, the time of the cycle timer 34 and the first s
It is determined whether or not the time of the syt after the offset value (set to 0) read from the yt reception FIFO 12k is added matches. Alternatively, since the first reception FIFO 12k for sys updates the read pointer,
It is also determined whether or not a predetermined time has elapsed. When they match,
Alternatively, the process proceeds to S72 when the predetermined time has elapsed, and otherwise returns to S71.

When the time of syt is earlier than the time of the cycle timer 34 of the receiving node (the cycle timer value of syt is small) for some reason, the time of syt and the cycle timer 34 are forever. Time does not match. Therefore, when the predetermined time has elapsed, the process is forcibly advanced to S72, and the next s
It is controlled to read yt. In the specific example shown in FIG. 3, syt = 1000 is read from the first syt reception buffer 12k. When the time of the cycle timer 34 reaches 1000, the comparator 33a operates as shown in FIG.
The coincidence pulse is output as shown in.

In S72 of FIG. 7, the read pointer of the first receive FIFO for reception 12k is incremented, and in S73 the first receive FIFO1 for reception 1k is incremented.
The next syt is read based on the 2k read pointer, and in S74, the offset time is added to the read syt time and sent to the comparator 33a, and the process proceeds to S75. In the specific example of FIG. 3, in S72, s
yt = 9000 is read and sent to the comparator 33a.

In S75 of FIG. 7, the PLL 35 generates a reproduction sampling clock synchronized with the coincidence pulse, and advances the processing to S76. At the same time, the receiving node reproducing process 2 described later is executed in parallel. In S76, it is determined whether an error has occurred. For example, the occurrence of an error is detected when the value of the counter that counts the received data blocks does not match the value of the DBC included in the CIP header of the packet. Alternatively, based on the received syt, the change in time (incremental value) of the received syt does not match the set time interval of syt,
Alternatively, the occurrence of an error is detected when the count value of the number of reproduction sampling clocks in the interval of the adjacent coincident pulse does not coincide with the value (8) determined by the syt interval (out of phase synchronization in the PLL 35). At the same time, it also detects the reception of an interrupt packet indicating the occurrence of an error from the transmitting node. When an error occurs or an interrupt packet is received, S
The process proceeds to 77, and otherwise returns to S71 to continue the reproducing process. In S77, the audio output is muted (silenced). When the error recovery processing is performed, reading of the audio reception FIFOs 12a to 12h can be started again when the time of sys received from each transmission node matches the time of the cycle timer.

In the example shown in FIG. 3, since no error has occurred, the process is returned to S71. When the cycle timer 34 of the receiving node next outputs 9000, the comparator 33a outputs a coincidence pulse as shown in FIG. The read pointer of the first reception FIFO 12k for syt is incremented again, syt = 11000 is read, and output to the comparator 33a. The reception FIFO 12l for the second syt operates simultaneously with the reception FIFO 12k for the first syt and writes the syt of the transmission node B102.
Although not shown in the figure, the processing flow of is substantially the same as that of S71 to S77 except that S75 is not provided.

Next, the reproduction processing 2 of the receiving node will be described. In S78, the audio reception FIFO 12
Acquire and manage the read pointers of a to 12h. First, the read pointers of the audio reception FIFOs 12a and 12b will be described. The data block corresponding to the time of syt when the coincidence pulse is output from the comparator 33a is DA0. Therefore, the read control unit 36 sets the read pointers of the audio reception FIFOs 12a and 12b to the position of DA0 and starts reading from DA0. After that, the read pointer is incremented for each reproduction sampling clock output from the PLL 35 via the read control unit 36.

As a result, in FIG. 3, the read pointers of the audio reception FIFOs 12a and 12b are set to "syt".
When the coincidence pulse is output when = 1000 is output, DA0 is at the stored position and DA0 is output.
Is read. Next, when the reproduction sampling clock shown in FIG. 4 is output from the PLL 35 via the read control unit 36, the read pointer is incremented and DA1 is read. Similarly, DA2 to DA7 are read in synchronization with the reproduction sampling clock. When syt = 9000, when the coincidence pulse shown in FIG.
The read pointers 12a and 12b are located at the positions where DA8 is stored, and DA8 is read. Thereafter, the subsequent data blocks are read in the same manner.

Next, the audio reception FIFO 12c,
The 12d read pointer will be described. In FIG. 3, from the second reception buffer 12l for syt, syt =
7000 is read. When the cycle timer 34 of the receiving node outputs 7000, the comparator 33b
The coincidence pulse shown in FIG. 4 is output. This time is a timing at which the audio data read from the audio reception FIFOs 12c and 12d is read at a time adjusted. Since the data block corresponding to the time of this sys is DB0, the read control unit 36
Reads DB0 by setting the read pointers of the audio reception FIFOs 12c and 12d to the position of DB0.
After that, the read pointer is incremented for each reproduction sampling clock output from the PLL 34.

In S79 of FIG. 7, audio data of one data block is supplied to the patch section 13 from each of the audio reception FIFOs 12a to 12f. In the normal mode, one data block is composed of audio data of a plurality of channels output with the same reproduction sampling clock. Each audio data is simultaneously read as parallel data for each reproduction sampling clock. In S80, the patch unit 13
Preset playback channels (audio
0 to audio7), the read audio data is supplied.

In the patch unit 13 in FIG. 1, which reproduction channel is to output the event sequence (audio data) of a plurality of channels according to the data structure in the data field in the packet of the received transmission node or the user setting. Is set. For example, if the audio data from the transmission node A 101 read from the audio reception FIFOs 12a and 12b is the first
And to the second reproduction channel (audio0, audio1). Audio data of the other transmitting node B 102 and the like are simultaneously assigned so as to be output to another reproduction channel. In S81, in each reproduction channel (audio0 to audio7), audio data is reproduced and output under the conditions (volume, effect, etc.) set in advance for this channel.

FIG. 5 is a block diagram for explaining an example in which a plurality of packet handlers shown in FIG. 1 are used. In the figure, 41 to 43 are the packet handlers shown in FIG. In FIG. 5, the master-slave setting terminal S
LV and control input terminal SEQ for simultaneous use
I and the control output terminal SEQO are clearly shown. By setting the SLV terminal of the packet handler 41 to LO, the packet handler 41 is set as a master, and by setting the SLV terminals of the packet handlers 42 and 43 to HI, these are set as slaves. The switching unit 37 of each of the packet handlers 41 to 43 is switched depending on whether it is a master or a slave.

The packet handlers 41 to 43 are commonly connected to the link layer controller 20 by a parallel bus. First, the master packet handler 41 receives a packet. However, a new sending node is added,
Alternatively, when a new audio channel is added to an existing transmission node, the reception FI for audio is used.
When the FOs 12a to 12h are full, their own SEQ
Set the O terminal to HI. As a result, the packet handler 42
Causes the SEQI terminal to be set to HI to receive the above-mentioned new transmission node or the above-mentioned new audio channel packet.

The packet handler 42 also sets its own SEQO terminal to HI when the audio reception FIFOs 12a to 12h are full. As a result, the packet handler 43 sets the SEQI terminal to HI and receives the packet. However, the packet handler 43 also sets its own SEQO terminal to HI when the audio reception FIFOs 12a to 12h are full. As a result, the master packet handler 41
The QI terminal is set to HI, and the packet is received again.

At this time, if there is a vacancy in the audio reception FIFOs 12a to 12h of the packet handler 41, S
Since the EQO terminal is LO, the received packet will be processed. However, when there is no free space, the SEQO terminal of the packet handler 41 is set to HI. If all the packet handlers 41 to 43 have no vacancy, the SEQO terminals of all the packet handlers 41 to 43 are HI, and a new packet cannot be received and processed.

In the packet handler 41 serving as the master, the reproduction sampling clock output from the PLL 35 is output to the PLLin of the packet handler 42 via the switching unit 37 and PLLout. In the packet handler 42, since it is a slave, the switching unit 37 is switched to the PLLin side. Therefore, PLLi
The reproduction sampling clock input to n is output to the read control unit 36 and also to PLLin of the packet handler 43 via PLLout. The packet handler 43 is similar to the packet handler 42.

As described above, the reproduction sampling clock is generated by the master, and the slave receives the reproduction sampling clock, whereby the packet handler 4
The reproduced sampling clocks 1 to 43 are made common.
However, each packet handler needs a configuration for matching the generation time of the audio data received by each packet handler 41-43 with the cycle timer 34 of the receiving node. Therefore, even in the slave packet handlers 42 and 43, the second s
When the time stamps from the plurality of received transmission nodes are sequentially assigned to the yt reception FIFO 12l and output, and the time obtained by adding a predetermined offset value to the time of this time stamp matches the time of the cycle timer 34,
The output of the audio data forming the data block corresponding to the time of this time stamp is read.

The packet handler 4 which is the slave
In Nos. 2 and 43, the operation of the first FIFO 12k for the syt and the operation of the PLL 35 are not necessary. Therefore, if these processing functions are stopped, the processing load of the CPU incorporated in the packet handlers 42 and 43 is reduced. Alternatively, the power consumption of hardware can be reduced. Or first
It is also possible to cause the FIFO 12k for syt to perform only the correction operation. In this case, in addition to fixing the time to a specific transmitting node and adjusting the time, the second FIFO 12 for system
The first and second syt FIFOs 1 are operated simultaneously with l.
The syts from a plurality of transmission nodes may be alternately and sequentially assigned to 2k and 12l to perform the correction operation.

In the example of FIG. 5, the packet handlers 41 to 4 are
Although all 3 have the same internal configuration, a packet handler dedicated to the master or dedicated to the slave may be manufactured. In this case, the unnecessary functions can be omitted. For example, as can be seen from FIG. 5, the switching unit 37
Of course is unnecessary, the reproduction sampling clock input terminal is not required in the packet handler dedicated to the master, and the PLL35 is used in the packet handler dedicated to the slave.
Is unnecessary, and in the packet handler for slaves connected to the end like the packet handler 43, the reproduction sampling clock output terminal is also unnecessary.

As described above, by simultaneously using the plurality of packet handlers 41 to 43, it is possible to flexibly change the system scale according to the required specifications of the receiving node. This is possible because, as the structure of the packet handlers 41 to 43, a plurality of independent audio channel reception FIFOs 12a to 12h share the link layer controller 20. Further, on the transmission side, each of the packet handlers 41 to 43 has a plurality of data input terminals, and each of them can independently generate a packet and output it to one link layer controller 20, so that it is free. A transmission method with high frequency becomes possible.

In the above description, the case where the delay offsets are all zero has been described. When always setting the delay offset to 0, the offset register 32
It is not necessary to provide a, 32b and adders 18a, 18b. However, the delay offset registers 32a and 32b shown in FIG. 1 and FIG. 2 are for arbitrarily delaying the read timing when reading the first and second syts from the reception FIFOs 12k and 12l. The value stored in the delay offset register 32a is the offset value set in the reference synchronous reproduction node, and the value stored in the delay offset register 32b is the transmission node targeted for read control by the second sys reception FIFO. Is an offset value set to. The offset values stored in the delay offset registers 32a and 32b can be set from outside the packet handlers 41 to 43. The transmission node can be identified by the isochronous transfer channel number in the isochronous header field.

On the transmission side, the time of syt is set as the value of the reproduction time on the reception side in consideration of the propagation delay. However, on the receiving side, the reproduction time of the audio data from each transmission node can be shifted from the time of syt by adjusting this offset value. As a result, on the receiving node side, the reproduction time of the audio data to be reproduced can be finely adjusted according to the transmission node or the like that is the transmission source of the sequence data. Further, it becomes possible to normally reproduce the sequence data of the past time due to various factors. Inserting a delay in anticipation of the propagation delay at the time of transmission is only an expected value. On the other hand, if the delay can be freely set by setting the offset value on the receiving side, it is possible to deal with the delay time as a result of delaying actually through a complicated network.

FIG. 8 is an explanatory diagram of a first transmission / reception operation example of the packet handler shown in FIG. 8A is an explanatory diagram of the transmitting side, FIG. 8B is an explanatory diagram of packets input to and output from the link layer controller 20, and FIG. 8C is an explanatory diagram of the receiving side. Description will be given with reference to the block diagram of the packet handler shown in FIG. This first transmission / reception operation example is an operation example in the case of packetizing audio data which is an event sequence of 6 channels of an input sampling clock of 48 kHz. In synchronization with the sampling clock WCKI, the audio data D0 and D1 are transferred from the input terminal DAI0 to the input terminal DAI1.
Audio data D2, D3 from the input terminal DAI2
To input audio data D4 and D5, respectively.

A type of 3D sound system,
Taking "5.1 system" as an example, front left (FL)
To D0, front right (FR) to D1, rear left (R
L) to D2, rear right (RR) to D3, center (C)
To D4 and subwoofer (SU) to D5.
In FIG. 8A, two channels of audio data are time-division multiplexed and input to each of the input terminals DAI0 to DAI2.
4e, each channel (D0 to D5) is demultiplexed into parallel data and output as audio channels (audio0 to audio5) shown in FIG. Transmission FIFO
8a, when the sampling clock WCKI falls, the data D0 of the sampling cycle (n)
(N), D2 (n), D4 (n) are written, and at the rising edge of the sampling clock WCKI, data D1 (n), D3 (n), D5 of the sampling period (n) are written.
Write (n).

Subsequently, the sampling clock WCKI
Of the sampling period (n + 1), data D0 (n + 1), D2 (n + 1), D4 (n + 1) are written at the falling edge of
1), D3 (n + 1), D5 (n + 1) are written, and thereafter, audio channels (audio0 to audio0
5) Write the audio data. Transmission FIFO 8a
Is the data D at the timing requested by the packetizing unit 9.
0 (n) to D5 (n), D0 (n + 1) to D5 (n +
1), D0 (n + 2) to D5 (n + 2) are sequentially read.

As shown in FIG. 8B, the packetizing unit 9
Is a header and data blocks DA0, DA1,
A packet composed of DA2 is formed and parallel data is output to the link layer controller 20. Since one data block is in units of 32 bits, and each data block is composed of 6 event sequences, that is, audio data of 6 channels, the data block size DBS = 6 is put in the header part.

In FIG. 8 (c), the receiving side performs the opposite process to the transmitting side. Link layer controller 20
The packet from 1 is divided into a header, audio data, non-audio data, syt, etc. in the unpacketizing unit 11 via the link interface 10. As for the audio data in the packet shown in FIG. 8B, one data block is separated into 6 event sequences (6 channels of audio data) from the header information of DBS = 6. Therefore, the data block DA0 includes a plurality of audio channels D0 (n).
To D5 (n) (32 bits each) and output.

Subsequently, the data blocks DA1 and DA2 are
, But each has a plurality of audio channels D0 (n +
1) to D5 (n + 1), D0 (n + 2) to D5 (n +
It is separated into 2) and output. In addition, 24 already explained
In bit * 4 audio pack format,
Each audio data is converted into 32 bits and output from the unpacketizing unit 11.

In the unpacketizing section 11, the audio data D0 to D5 are respectively received in the audio reception FIFO in accordance with the arrangement order in the data field.
12a to 12f. Receive FI for audio
The FOs 12a to 12f temporarily store 32-bit parallel data. The audio data D0 to D5 read out at the reproduction sampling period are output to the audio reproduction channel 0 as preset in the patch unit 13.
~ 7 (audio0-audio7) is assigned. In this operation example, D0 is assigned to the audio playback channel 0, D1 is assigned to the audio playback channel 1, D2 is assigned to the audio playback channel 2, and so on.

As shown in FIG. 8C, the audio interface 14b has audio reproduction channels 0,
Time-division multiplexed 1 audio data and output terminal DAO
Serial output to 0. Similarly, in the audio interface 14c, the audio data of the audio reproduction channels 2 and 3 are time-division multiplexed and serially output to the output terminal DAO1. In the audio interface 14d, the audio reproduction channels 4 and 5 are output.
Audio data is time-division multiplexed and output terminal DAO2
Serial output to. As a result, audio data corresponding to FIG. 8A is output.

FIG. 9 is an explanatory diagram of a second transmission / reception operation example of the packet handler shown in FIG. 9A is an explanatory diagram of the transmitting side, FIG. 9B is an explanatory diagram of packets input to and output from the link layer controller, and FIG. 9C is an explanatory diagram of the receiving side. In this second transmission / reception operation example, even if the input sampling clock on the transmission side remains at 48 kHz, the 3-channel audio data A / D converted by the sampling clock at 96 kHz which is twice 48 kHz is packetized and transmitted. It is an example of the operation when performing. The audio data D0 is input from the input terminal DAI0, the audio data D1 is input from the input terminal DAI1, and the input terminal DAI is synchronized with the half cycle of the sampling clock WCK.
Audio data D2 is serially input from each of the two.

A type of 3D sound system,
Taking "2.1 system" as an example, the front left (FL)
To D0, front right (FR) to D1, center (C)
To D2. As shown in FIG. 9A, the 3-channel audio data is input to the input channel (D0) in the audio interfaces 4b to 4e of FIG.
To D2) are converted into parallel data and distributed, and the first to fifth audio channels (audio0 to a) are distributed.
It is output as udio5). In the transmission FIFO 8a, when the sampling clock WCKI falls,
Data D0 (n), D1 of sampling period (n)
(N) and D2 (n) are input, and the sampling clock W
Sampling cycle (n + 1) at the rising edge of CKI
Data D0 (n + 1), D1 (n + 1), D2 (n +
Enter 1).

Subsequently, the sampling clock WCKI
Data D0 (n + 2), D1 (n + 2), D2 (n + 2) of the sampling period (n + 2) are input at the falling edge of, and the data D0 (n +) of the sampling period (n + 3) is input at the rising edge of the sampling clock WCKI.
3), D1 (n + 3), D2 (n + 3) are input, and thereafter, in the same manner, audio channels (audio0-aud)
Write the audio data of io5). Transmission FIFO8
a is a timing requested by the packetizing unit 9 and represents audio data D0 (n) to D2 (n), D0 (n + 1) to D0 (n).
D2 (n + 1), D0 (n + 2) to D2 (n + 2),
.. Read out D0 (n + 5) to D2 (n + 5).

As shown in FIG. 9B, the packetizing unit 9
Form a packet including a header and data blocks DA0 to DA5, and link layer controller 20
Output to. One data block is a unit of 32 bits, and each data block has three event sequences,
That is, since it is composed of audio data of 3 channels, the data block size DB is included in the header part.
S = 3 is entered.

In FIG. 9 (c), the reverse process of the transmitting unit is performed. The packet output from the link layer controller 20 is divided into a header, audio data, non-audio data, syt, etc. in the unpacketizing unit 11 via the link interface 10. Regarding the audio data in the packet shown in FIG. 9B, one data block is separated into three event sequences (audio channels) from the header information of DBS = 3. Therefore, the data block DA0
Is audio data D0 (n) to D2 of 3 channels
(N) (each 32 bits) is separated and output. Subsequently, the data blocks DA1 to DA5 are respectively 3
Channel audio data D0 (n + 1) to D2
(N + 1) and D0 (n + 2) to D2 (n + 2) are output.

In the unpacketizing section 11, the audio data D is arranged in the order of arrangement in the data field.
0 (n), D1 (n), D2 (n), D0 (n + 1),
Receive D1 (n + 1) and D2 (n + 1) for audio F
It is assigned to the IFOs 12a to 12f. Similarly,
Next audio data D0 (n + 2), D1 (n +
2), D2 (n + 2), D0 (n + 3), D1 (n +
3) and D2 (n + 3) again to receive FI for audio
It is supplied to the FO 12a to the FIFO 12f. The audio data D0 to D2 temporarily stored as 32-bit parallel data in the audio reception FIFOs 12a to 12f are respectively A / D at a sampling frequency of 96 kHz.
It has been converted.

In the patch section 13, the audio reproduction channels 0 to 5 (audit) are set as preset.
Assigned to o0-audio7). In this operation example, D0 stored in the audio reception FIFO 12a is assigned to the audio channel 0, and the audio reception FIFO 12 is set to the audio channel 0.
D0 stored in b is assigned to audio channel 1, D1 stored in the audio reception FIFO 12c is assigned to audio channel 2, and so on.

As shown in FIG. 9C, in the audio interface 14b, audio data of audio channels 0 and 1 are time-division multiplexed and serially output to the output terminal DA0. Similarly, in the audio interface 14c, the audio data of the audio channels 2 and 3 are time-division multiplexed and serially output to the output terminal DA1, and in the audio interface 14d, the audio data of the audio channels 4 and 5 are time-divided. The signals are multiplexed and serially output to the output terminal DA2. As a result, since the audio data corresponding to FIG. 9A is output, even if the reproduction sampling clock remains at 48 kHz, 96 kHz
It is possible to read the audio data D0 to D2 which are A / D converted in the sampling cycle of.

Switching between the two transfer modes as shown in FIGS. 8 and 9 can be performed by the information contained in the header portion of the packet format shown in FIG. At that time, the two transfer modes can be identified by the value of DBS. As described above, the patch unit 13
Receives the audio reception FIFO1 according to the transfer mode.
The output destination of the audio data stored in 2a to 12f is assigned. Even in one transfer mode, the patch unit 13 can change the assignment destination of the audio data by changing the assignment according to the user setting in the receiving node. For example, in the above-mentioned "5.1 system", the left channel (FL, RL) and the right channel (FR, RR) are exchanged, or the front channel (FL, FR) and the rear channel (RL, RR) are replaced. The sound image localization can be changed by replacing the sound image.

The two transfer modes shown in FIGS. 8 and 9 are:
By utilizing the fact that the sampling clock has a duty ratio of 50%, 2 per 1 sampling cycle is synchronized with the rising and falling of the sampling clock.
The sample was time-division multiplexed and externally input or output. In this case, there is an advantage that input and output can be easily performed in synchronization with the sampling clock signal. Instead, m samples (m is a natural number of 3 or more) per sampling period are externally input or output by time division multiplexing, and in the same manner, in addition to the transfer mode of the reproduction sampling clock f _s kHz. It is also possible to provide a transfer mode of the reproduction sampling clock m × f _s kHz.

In the above description, the reception FI for audio is used.
The event sequence (audit data) temporarily stored in one of the FOs 12a to 12h is 1-channel audio data. However, the event sequence (audio data) of a plurality of channels is set as one unit, and the unit event sequence is used as the audio reception FIFO 12
It may be temporarily stored in one of a to 12h.
For example, one input terminal is time-division multiplexed and input, and one output terminal is time-division multiplexed and output.
For example, audio channels 0, 1 (audio0, audio
1) ... Audio channels 6 and 7 (audio6, aud
io7) as one unit, and the unit audio channels are set to the same audio reception FIFOs 12a, 12
b, 12c, 12d may be temporarily stored.

In the above description, the audio data sampling clock is used as the input timing clock on the transmitting node side and the reproduction timing clock on the receiving side. However, this sampling clock is n times (n is 2).
As a timing clock having a frequency of the above natural number) or 1 / n times, one data block may be configured with this timing clock as a unit.

[0093]

As is apparent from the above description, the present invention can receive a packet including event sequence data such as audio and music data, and reproduce the packet at a time designated by the transmitting side. effective.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a packet handler according to an embodiment of a packet transfer device of the present invention.

FIG. 2 is a block diagram illustrating a receiving node reproducing process of the packet handler according to the embodiment of this invention.

3 is a first explanatory diagram showing an example of the operation of the block configuration diagram shown in FIG. 2. FIG.

FIG. 4 is a second explanatory diagram showing an example of the operation of the block configuration diagram shown in FIG.

5 is a block diagram for explaining an example in which a plurality of packet handlers shown in FIG. 1 are used.

FIG. 6 is a flowchart for explaining an outline of operation of the packet handler shown in FIG.

FIG. 7 is a flowchart for explaining a reproduction process of a receiving node.

8 is an explanatory diagram of a first transmission / reception operation example of the packet handler shown in FIG.

9 is an explanatory diagram of a second transmission / reception operation example of the packet handler shown in FIG.

FIG. 10 is an explanatory diagram showing a packet flow on a network.

FIG. 11 is an explanatory diagram of a packet format at the time of isochronous transfer.

FIG. 12 is a diagram illustrating an operation of isochronous transfer.

[Explanation of symbols]

1 transmitter, 2 receiver, 4a to 4e audio interface, 5 CPU interface, 6 CP
U bus, 11 unpacketizing section, 12a to 12h audio receiving FIFO, 12i, 12j non-audio receiving buffer, 12k, 12l syt receiving buffer, 13 patch section, 14a to 14e audio interface section, 16a, 16b switching section , 18a, 1
8b adder, 19 synchronization unit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-8-97807 (JP, A) JP-A-7-326127 (JP, A) JP-A-10-257080 (JP, A) JP-A-10- 145753 (JP, A) JP 7-327287 (JP, A) JP 10-164108 (JP, A) JP 8-190515 (JP, A) JP 12-278276 (JP, A) JP-A-12-278353 (JP, A) JP-A-12-278354 (JP, A) JP-A-12-278326 (JP, A) JP-A-12-276441 (JP, A) JP-A-12-278277 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/28-12/46 G11B 20/10 H04L 7/00

Claims (2)

(57) [Claims] 1. A packet transfer apparatus that receives a packet from the desired number of multiple transmitting nodes on the network, a synchronized cycle timer time in the network
From the output cycle timer and the transmitting node, 1 in each sampling period
Or multiple event sequence data into one data block
When the lock is configured and the data block is 1
Or including multiple, for each predetermined number of the data block
When a packet with a time stamp is received,
From the packet with the data block and the time
An unpacket means for extracting and outputting a tamper and one of the desired plurality of transmitting nodes are set as a synchronous reproduction reference node.
Output from the unpacketing means,
The time stamp included in the packet from the synchronous playback reference node.
Synchronized playback of playback sampling clock using tamps
Reproduction sampling clock output means for outputting the data block and the data block output from the unpacket means.
A reception buffer for sequentially storing the click is output from the reproduction sampling clock output means
Depending on the reproduction sampling clock, the reception buffer
By reading the data block from the
Data output means for outputting input sequence data, and the synchronous reproduction base output from the unpacket means.
The time stamp included in the packet from the quasi node
Corresponding time and cycle output from the cycle timer
The data is output at the timing when the timer
The data block from the receive buffer by means of input means.
Output the data by correcting the extraction position
For the method, the time stamp
Reproduction time control means for outputting a response data block, packet transfer apparatus, comprising the. 2. A desired first transmission node on the network.
Packet receiving packet from the second sending node
A transfer device, the cycle timer time synchronized in the network
And cycle timer for outputting, from the first transmission node and the second transmission node, its
One or more events in each sampling period
Bent sequence data constitutes one data block
And one or more data blocks
Includes a time stamp for each specified number of data blocks.
Received a packet with a
Take the time stamp with the data block
The unpacket means for outputting and outputting, and the first transmission node output from the unpacket means.
Using the time stamp included in the packet from the
Playback sampling clock synchronized playback and output
Pulling clock output means and the first transmission node output from the unpacket means.
A first receiver for sequentially storing the data blocks from the hard disk.
Output from the reproduction buffer and the reproduction sampling clock output means.
According to the reproduction sampling clock, the first reception buffer
By reading the data block from the
First data output to output event sequence data
The first transmission output from the output means and the unpacket means.
Corresponds to the time stamp included in the packet from the node
And the cycle output from the cycle timer
At the timing when the timer time matches, the first data
The data from the first receive buffer by the data output means.
By correcting the data block removal position,
The time when a match is made to the first data output means.
Output the data block corresponding to the time of tamping
1 reproduction time correction means and the second transmission output from the unpacket means
A second receive bar for sequentially storing the blocks from the node
And Ffa, output from the reproduction sampling clock output means
According to the reproduction sampling clock, the second reception buffer
By reading the data block from the
Second data output to output event sequence data
The second transmission output from the output means and the unpacket means.
Corresponds to the time stamp included in the packet from the node
And the cycle output from the cycle timer
At the timing when the timer time matches, the second data
Said de from the second receiving buffer that by the data output means
By correcting the data block removal position,
When the second data output means, the time
Output the data block corresponding to the time of tamping
2. A packet transfer device comprising a reproduction time correction means of 2 .